1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v12_0.h" 30 31 #include "mp/mp_12_0_0_offset.h" 32 #include "mp/mp_12_0_0_sh_mask.h" 33 #include "gc/gc_9_0_offset.h" 34 #include "sdma0/sdma0_4_0_offset.h" 35 #include "nbio/nbio_7_4_offset.h" 36 37 #include "oss/osssys_4_0_offset.h" 38 #include "oss/osssys_4_0_sh_mask.h" 39 40 MODULE_FIRMWARE("amdgpu/renoir_asd.bin"); 41 MODULE_FIRMWARE("amdgpu/renoir_ta.bin"); 42 MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin"); 43 MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin"); 44 45 /* address block */ 46 #define smnMP1_FIRMWARE_FLAGS 0x3010024 47 48 static int psp_v12_0_init_microcode(struct psp_context *psp) 49 { 50 struct amdgpu_device *adev = psp->adev; 51 const char *chip_name; 52 char fw_name[30]; 53 int err = 0; 54 const struct ta_firmware_header_v1_0 *ta_hdr; 55 DRM_DEBUG("\n"); 56 57 switch (adev->asic_type) { 58 case CHIP_RENOIR: 59 if (adev->apu_flags & AMD_APU_IS_RENOIR) 60 chip_name = "renoir"; 61 else 62 chip_name = "green_sardine"; 63 break; 64 default: 65 BUG(); 66 } 67 68 err = psp_init_asd_microcode(psp, chip_name); 69 if (err) 70 goto out; 71 72 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 73 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 74 if (err) { 75 release_firmware(adev->psp.ta_fw); 76 adev->psp.ta_fw = NULL; 77 dev_info(adev->dev, 78 "psp v12.0: Failed to load firmware \"%s\"\n", 79 fw_name); 80 } else { 81 err = amdgpu_ucode_validate(adev->psp.ta_fw); 82 if (err) 83 goto out2; 84 85 ta_hdr = (const struct ta_firmware_header_v1_0 *) 86 adev->psp.ta_fw->data; 87 adev->psp.ta_hdcp_ucode_version = 88 le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 89 adev->psp.ta_hdcp_ucode_size = 90 le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 91 adev->psp.ta_hdcp_start_addr = 92 (uint8_t *)ta_hdr + 93 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 94 95 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 96 97 adev->psp.ta_dtm_ucode_version = 98 le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 99 adev->psp.ta_dtm_ucode_size = 100 le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 101 adev->psp.ta_dtm_start_addr = 102 (uint8_t *)adev->psp.ta_hdcp_start_addr + 103 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 104 } 105 106 return 0; 107 108 out2: 109 release_firmware(adev->psp.ta_fw); 110 adev->psp.ta_fw = NULL; 111 out: 112 if (err) { 113 dev_err(adev->dev, 114 "psp v12.0: Failed to load firmware \"%s\"\n", 115 fw_name); 116 } 117 118 return err; 119 } 120 121 static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp) 122 { 123 int ret; 124 uint32_t psp_gfxdrv_command_reg = 0; 125 struct amdgpu_device *adev = psp->adev; 126 uint32_t sol_reg; 127 128 /* Check sOS sign of life register to confirm sys driver and sOS 129 * are already been loaded. 130 */ 131 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 132 if (sol_reg) 133 return 0; 134 135 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 136 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 137 0x80000000, 0x80000000, false); 138 if (ret) 139 return ret; 140 141 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 142 143 /* Copy PSP System Driver binary to memory */ 144 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 145 146 /* Provide the sys driver to bootloader */ 147 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 148 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 149 psp_gfxdrv_command_reg = 1 << 16; 150 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 151 psp_gfxdrv_command_reg); 152 153 /* there might be handshake issue with hardware which needs delay */ 154 mdelay(20); 155 156 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 157 0x80000000, 0x80000000, false); 158 159 return ret; 160 } 161 162 static int psp_v12_0_bootloader_load_sos(struct psp_context *psp) 163 { 164 int ret; 165 unsigned int psp_gfxdrv_command_reg = 0; 166 struct amdgpu_device *adev = psp->adev; 167 uint32_t sol_reg; 168 169 /* Check sOS sign of life register to confirm sys driver and sOS 170 * are already been loaded. 171 */ 172 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 173 if (sol_reg) 174 return 0; 175 176 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 177 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 178 0x80000000, 0x80000000, false); 179 if (ret) 180 return ret; 181 182 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 183 184 /* Copy Secure OS binary to PSP memory */ 185 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 186 187 /* Provide the PSP secure OS to bootloader */ 188 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 189 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 190 psp_gfxdrv_command_reg = 2 << 16; 191 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 192 psp_gfxdrv_command_reg); 193 194 /* there might be handshake issue with hardware which needs delay */ 195 mdelay(20); 196 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 197 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 198 0, true); 199 200 return ret; 201 } 202 203 static void psp_v12_0_reroute_ih(struct psp_context *psp) 204 { 205 struct amdgpu_device *adev = psp->adev; 206 uint32_t tmp; 207 208 /* Change IH ring for VMC */ 209 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 210 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 211 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 212 213 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 214 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 215 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 216 217 mdelay(20); 218 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 219 0x80000000, 0x8000FFFF, false); 220 221 /* Change IH ring for UMC */ 222 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 223 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 224 225 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 226 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 227 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 228 229 mdelay(20); 230 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 231 0x80000000, 0x8000FFFF, false); 232 } 233 234 static int psp_v12_0_ring_init(struct psp_context *psp, 235 enum psp_ring_type ring_type) 236 { 237 int ret = 0; 238 struct psp_ring *ring; 239 struct amdgpu_device *adev = psp->adev; 240 241 psp_v12_0_reroute_ih(psp); 242 243 ring = &psp->km_ring; 244 245 ring->ring_type = ring_type; 246 247 /* allocate 4k Page of Local Frame Buffer memory for ring */ 248 ring->ring_size = 0x1000; 249 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 250 AMDGPU_GEM_DOMAIN_VRAM, 251 &adev->firmware.rbuf, 252 &ring->ring_mem_mc_addr, 253 (void **)&ring->ring_mem); 254 if (ret) { 255 ring->ring_size = 0; 256 return ret; 257 } 258 259 return 0; 260 } 261 262 static int psp_v12_0_ring_create(struct psp_context *psp, 263 enum psp_ring_type ring_type) 264 { 265 int ret = 0; 266 unsigned int psp_ring_reg = 0; 267 struct psp_ring *ring = &psp->km_ring; 268 struct amdgpu_device *adev = psp->adev; 269 270 if (amdgpu_sriov_vf(psp->adev)) { 271 /* Write low address of the ring to C2PMSG_102 */ 272 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 273 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 274 /* Write high address of the ring to C2PMSG_103 */ 275 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 276 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 277 278 /* Write the ring initialization command to C2PMSG_101 */ 279 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 280 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 281 282 /* there might be handshake issue with hardware which needs delay */ 283 mdelay(20); 284 285 /* Wait for response flag (bit 31) in C2PMSG_101 */ 286 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 287 0x80000000, 0x8000FFFF, false); 288 289 } else { 290 /* Write low address of the ring to C2PMSG_69 */ 291 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 292 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 293 /* Write high address of the ring to C2PMSG_70 */ 294 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 295 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 296 /* Write size of ring to C2PMSG_71 */ 297 psp_ring_reg = ring->ring_size; 298 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 299 /* Write the ring initialization command to C2PMSG_64 */ 300 psp_ring_reg = ring_type; 301 psp_ring_reg = psp_ring_reg << 16; 302 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 303 304 /* there might be handshake issue with hardware which needs delay */ 305 mdelay(20); 306 307 /* Wait for response flag (bit 31) in C2PMSG_64 */ 308 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 309 0x80000000, 0x8000FFFF, false); 310 } 311 312 return ret; 313 } 314 315 static int psp_v12_0_ring_stop(struct psp_context *psp, 316 enum psp_ring_type ring_type) 317 { 318 int ret = 0; 319 struct amdgpu_device *adev = psp->adev; 320 321 /* Write the ring destroy command*/ 322 if (amdgpu_sriov_vf(adev)) 323 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 324 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 325 else 326 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 327 GFX_CTRL_CMD_ID_DESTROY_RINGS); 328 329 /* there might be handshake issue with hardware which needs delay */ 330 mdelay(20); 331 332 /* Wait for response flag (bit 31) */ 333 if (amdgpu_sriov_vf(adev)) 334 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 335 0x80000000, 0x80000000, false); 336 else 337 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 338 0x80000000, 0x80000000, false); 339 340 return ret; 341 } 342 343 static int psp_v12_0_ring_destroy(struct psp_context *psp, 344 enum psp_ring_type ring_type) 345 { 346 int ret = 0; 347 struct psp_ring *ring = &psp->km_ring; 348 struct amdgpu_device *adev = psp->adev; 349 350 ret = psp_v12_0_ring_stop(psp, ring_type); 351 if (ret) 352 DRM_ERROR("Fail to stop psp ring\n"); 353 354 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 355 &ring->ring_mem_mc_addr, 356 (void **)&ring->ring_mem); 357 358 return ret; 359 } 360 361 static int psp_v12_0_mode1_reset(struct psp_context *psp) 362 { 363 int ret; 364 uint32_t offset; 365 struct amdgpu_device *adev = psp->adev; 366 367 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 368 369 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 370 371 if (ret) { 372 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 373 return -EINVAL; 374 } 375 376 /*send the mode 1 reset command*/ 377 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 378 379 msleep(500); 380 381 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 382 383 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 384 385 if (ret) { 386 DRM_INFO("psp mode 1 reset failed!\n"); 387 return -EINVAL; 388 } 389 390 DRM_INFO("psp mode1 reset succeed \n"); 391 392 return 0; 393 } 394 395 static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp) 396 { 397 uint32_t data; 398 struct amdgpu_device *adev = psp->adev; 399 400 if (amdgpu_sriov_vf(adev)) 401 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 402 else 403 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 404 405 return data; 406 } 407 408 static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 409 { 410 struct amdgpu_device *adev = psp->adev; 411 412 if (amdgpu_sriov_vf(adev)) { 413 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 414 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 415 } else 416 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 417 } 418 419 static const struct psp_funcs psp_v12_0_funcs = { 420 .init_microcode = psp_v12_0_init_microcode, 421 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv, 422 .bootloader_load_sos = psp_v12_0_bootloader_load_sos, 423 .ring_init = psp_v12_0_ring_init, 424 .ring_create = psp_v12_0_ring_create, 425 .ring_stop = psp_v12_0_ring_stop, 426 .ring_destroy = psp_v12_0_ring_destroy, 427 .mode1_reset = psp_v12_0_mode1_reset, 428 .ring_get_wptr = psp_v12_0_ring_get_wptr, 429 .ring_set_wptr = psp_v12_0_ring_set_wptr, 430 }; 431 432 void psp_v12_0_set_psp_funcs(struct psp_context *psp) 433 { 434 psp->funcs = &psp_v12_0_funcs; 435 } 436