16a7a0bdbSAaron Liu /* 26a7a0bdbSAaron Liu * Copyright 2019 Advanced Micro Devices, Inc. 36a7a0bdbSAaron Liu * 46a7a0bdbSAaron Liu * Permission is hereby granted, free of charge, to any person obtaining a 56a7a0bdbSAaron Liu * copy of this software and associated documentation files (the "Software"), 66a7a0bdbSAaron Liu * to deal in the Software without restriction, including without limitation 76a7a0bdbSAaron Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 86a7a0bdbSAaron Liu * and/or sell copies of the Software, and to permit persons to whom the 96a7a0bdbSAaron Liu * Software is furnished to do so, subject to the following conditions: 106a7a0bdbSAaron Liu * 116a7a0bdbSAaron Liu * The above copyright notice and this permission notice shall be included in 126a7a0bdbSAaron Liu * all copies or substantial portions of the Software. 136a7a0bdbSAaron Liu * 146a7a0bdbSAaron Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 156a7a0bdbSAaron Liu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 166a7a0bdbSAaron Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 176a7a0bdbSAaron Liu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 186a7a0bdbSAaron Liu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 196a7a0bdbSAaron Liu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 206a7a0bdbSAaron Liu * OTHER DEALINGS IN THE SOFTWARE. 216a7a0bdbSAaron Liu */ 226a7a0bdbSAaron Liu 236a7a0bdbSAaron Liu #include <linux/firmware.h> 242568cedcSStephen Rothwell #include <linux/module.h> 256a7a0bdbSAaron Liu #include "amdgpu.h" 266a7a0bdbSAaron Liu #include "amdgpu_psp.h" 276a7a0bdbSAaron Liu #include "amdgpu_ucode.h" 286a7a0bdbSAaron Liu #include "soc15_common.h" 296a7a0bdbSAaron Liu #include "psp_v12_0.h" 306a7a0bdbSAaron Liu 316a7a0bdbSAaron Liu #include "mp/mp_12_0_0_offset.h" 326a7a0bdbSAaron Liu #include "mp/mp_12_0_0_sh_mask.h" 336a7a0bdbSAaron Liu #include "gc/gc_9_0_offset.h" 346a7a0bdbSAaron Liu #include "sdma0/sdma0_4_0_offset.h" 356a7a0bdbSAaron Liu #include "nbio/nbio_7_4_offset.h" 366a7a0bdbSAaron Liu 376a7a0bdbSAaron Liu #include "oss/osssys_4_0_offset.h" 386a7a0bdbSAaron Liu #include "oss/osssys_4_0_sh_mask.h" 396a7a0bdbSAaron Liu 406a7a0bdbSAaron Liu MODULE_FIRMWARE("amdgpu/renoir_asd.bin"); 416627d1c1SChangfeng MODULE_FIRMWARE("amdgpu/renoir_ta.bin"); 4268697982SAaron Liu MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin"); 4326642192SRoman Li MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin"); 446627d1c1SChangfeng 456a7a0bdbSAaron Liu /* address block */ 466a7a0bdbSAaron Liu #define smnMP1_FIRMWARE_FLAGS 0x3010024 476a7a0bdbSAaron Liu 486a7a0bdbSAaron Liu static int psp_v12_0_init_microcode(struct psp_context *psp) 496a7a0bdbSAaron Liu { 506a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 516a7a0bdbSAaron Liu const char *chip_name; 526627d1c1SChangfeng char fw_name[30]; 536a7a0bdbSAaron Liu int err = 0; 546627d1c1SChangfeng const struct ta_firmware_header_v1_0 *ta_hdr; 556627d1c1SChangfeng DRM_DEBUG("\n"); 566a7a0bdbSAaron Liu 576a7a0bdbSAaron Liu switch (adev->asic_type) { 586a7a0bdbSAaron Liu case CHIP_RENOIR: 5968697982SAaron Liu if (adev->apu_flags & AMD_APU_IS_RENOIR) 606a7a0bdbSAaron Liu chip_name = "renoir"; 6168697982SAaron Liu else 6268697982SAaron Liu chip_name = "green_sardine"; 636a7a0bdbSAaron Liu break; 646a7a0bdbSAaron Liu default: 656a7a0bdbSAaron Liu BUG(); 666a7a0bdbSAaron Liu } 676a7a0bdbSAaron Liu 68f4503f9eSHawking Zhang err = psp_init_asd_microcode(psp, chip_name); 696627d1c1SChangfeng if (err) 706627d1c1SChangfeng goto out; 716627d1c1SChangfeng 726627d1c1SChangfeng snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 736627d1c1SChangfeng err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 746627d1c1SChangfeng if (err) { 756627d1c1SChangfeng release_firmware(adev->psp.ta_fw); 766627d1c1SChangfeng adev->psp.ta_fw = NULL; 776627d1c1SChangfeng dev_info(adev->dev, 786627d1c1SChangfeng "psp v12.0: Failed to load firmware \"%s\"\n", 796627d1c1SChangfeng fw_name); 806627d1c1SChangfeng } else { 816627d1c1SChangfeng err = amdgpu_ucode_validate(adev->psp.ta_fw); 826627d1c1SChangfeng if (err) 836627d1c1SChangfeng goto out2; 846627d1c1SChangfeng 856627d1c1SChangfeng ta_hdr = (const struct ta_firmware_header_v1_0 *) 866627d1c1SChangfeng adev->psp.ta_fw->data; 876627d1c1SChangfeng adev->psp.ta_hdcp_ucode_version = 886627d1c1SChangfeng le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 896627d1c1SChangfeng adev->psp.ta_hdcp_ucode_size = 906627d1c1SChangfeng le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 916627d1c1SChangfeng adev->psp.ta_hdcp_start_addr = 926627d1c1SChangfeng (uint8_t *)ta_hdr + 936627d1c1SChangfeng le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 946627d1c1SChangfeng 956627d1c1SChangfeng adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 966627d1c1SChangfeng 976627d1c1SChangfeng adev->psp.ta_dtm_ucode_version = 986627d1c1SChangfeng le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 996627d1c1SChangfeng adev->psp.ta_dtm_ucode_size = 1006627d1c1SChangfeng le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 1016627d1c1SChangfeng adev->psp.ta_dtm_start_addr = 1026627d1c1SChangfeng (uint8_t *)adev->psp.ta_hdcp_start_addr + 1036627d1c1SChangfeng le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 1046627d1c1SChangfeng } 1056627d1c1SChangfeng 1066627d1c1SChangfeng return 0; 1076627d1c1SChangfeng 1086627d1c1SChangfeng out2: 1096627d1c1SChangfeng release_firmware(adev->psp.ta_fw); 1106627d1c1SChangfeng adev->psp.ta_fw = NULL; 1116627d1c1SChangfeng out: 1126627d1c1SChangfeng if (err) { 1136627d1c1SChangfeng dev_err(adev->dev, 1146627d1c1SChangfeng "psp v12.0: Failed to load firmware \"%s\"\n", 1156627d1c1SChangfeng fw_name); 1166627d1c1SChangfeng } 1176627d1c1SChangfeng 1186a7a0bdbSAaron Liu return err; 1196a7a0bdbSAaron Liu } 1206a7a0bdbSAaron Liu 1216a7a0bdbSAaron Liu static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp) 1226a7a0bdbSAaron Liu { 1236a7a0bdbSAaron Liu int ret; 1246a7a0bdbSAaron Liu uint32_t psp_gfxdrv_command_reg = 0; 1256a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 1266a7a0bdbSAaron Liu uint32_t sol_reg; 1276a7a0bdbSAaron Liu 1286a7a0bdbSAaron Liu /* Check sOS sign of life register to confirm sys driver and sOS 1296a7a0bdbSAaron Liu * are already been loaded. 1306a7a0bdbSAaron Liu */ 1316a7a0bdbSAaron Liu sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 132d4d27897SHawking Zhang if (sol_reg) 1336a7a0bdbSAaron Liu return 0; 1346a7a0bdbSAaron Liu 1356a7a0bdbSAaron Liu /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 1366a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 1376a7a0bdbSAaron Liu 0x80000000, 0x80000000, false); 1386a7a0bdbSAaron Liu if (ret) 1396a7a0bdbSAaron Liu return ret; 1406a7a0bdbSAaron Liu 1416a7a0bdbSAaron Liu memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1426a7a0bdbSAaron Liu 1436a7a0bdbSAaron Liu /* Copy PSP System Driver binary to memory */ 1446a7a0bdbSAaron Liu memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 1456a7a0bdbSAaron Liu 1466a7a0bdbSAaron Liu /* Provide the sys driver to bootloader */ 1476a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 1486a7a0bdbSAaron Liu (uint32_t)(psp->fw_pri_mc_addr >> 20)); 1496a7a0bdbSAaron Liu psp_gfxdrv_command_reg = 1 << 16; 1506a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 1516a7a0bdbSAaron Liu psp_gfxdrv_command_reg); 1526a7a0bdbSAaron Liu 1536a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */ 1546a7a0bdbSAaron Liu mdelay(20); 1556a7a0bdbSAaron Liu 1566a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 1576a7a0bdbSAaron Liu 0x80000000, 0x80000000, false); 1586a7a0bdbSAaron Liu 1596a7a0bdbSAaron Liu return ret; 1606a7a0bdbSAaron Liu } 1616a7a0bdbSAaron Liu 1626a7a0bdbSAaron Liu static int psp_v12_0_bootloader_load_sos(struct psp_context *psp) 1636a7a0bdbSAaron Liu { 1646a7a0bdbSAaron Liu int ret; 1656a7a0bdbSAaron Liu unsigned int psp_gfxdrv_command_reg = 0; 1666a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 1676a7a0bdbSAaron Liu uint32_t sol_reg; 1686a7a0bdbSAaron Liu 1696a7a0bdbSAaron Liu /* Check sOS sign of life register to confirm sys driver and sOS 1706a7a0bdbSAaron Liu * are already been loaded. 1716a7a0bdbSAaron Liu */ 1726a7a0bdbSAaron Liu sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 1736a7a0bdbSAaron Liu if (sol_reg) 1746a7a0bdbSAaron Liu return 0; 1756a7a0bdbSAaron Liu 1766a7a0bdbSAaron Liu /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 1776a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 1786a7a0bdbSAaron Liu 0x80000000, 0x80000000, false); 1796a7a0bdbSAaron Liu if (ret) 1806a7a0bdbSAaron Liu return ret; 1816a7a0bdbSAaron Liu 1826a7a0bdbSAaron Liu memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1836a7a0bdbSAaron Liu 1846a7a0bdbSAaron Liu /* Copy Secure OS binary to PSP memory */ 1856a7a0bdbSAaron Liu memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 1866a7a0bdbSAaron Liu 1876a7a0bdbSAaron Liu /* Provide the PSP secure OS to bootloader */ 1886a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 1896a7a0bdbSAaron Liu (uint32_t)(psp->fw_pri_mc_addr >> 20)); 1906a7a0bdbSAaron Liu psp_gfxdrv_command_reg = 2 << 16; 1916a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 1926a7a0bdbSAaron Liu psp_gfxdrv_command_reg); 1936a7a0bdbSAaron Liu 1946a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */ 1956a7a0bdbSAaron Liu mdelay(20); 1966a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 1976a7a0bdbSAaron Liu RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 1986a7a0bdbSAaron Liu 0, true); 1996a7a0bdbSAaron Liu 2006a7a0bdbSAaron Liu return ret; 2016a7a0bdbSAaron Liu } 2026a7a0bdbSAaron Liu 2036a7a0bdbSAaron Liu static void psp_v12_0_reroute_ih(struct psp_context *psp) 2046a7a0bdbSAaron Liu { 2056a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 2066a7a0bdbSAaron Liu uint32_t tmp; 2076a7a0bdbSAaron Liu 2086a7a0bdbSAaron Liu /* Change IH ring for VMC */ 2096a7a0bdbSAaron Liu tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 2106a7a0bdbSAaron Liu tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 2116a7a0bdbSAaron Liu tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 2126a7a0bdbSAaron Liu 2136a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 2146a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 2156a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 2166a7a0bdbSAaron Liu 2176a7a0bdbSAaron Liu mdelay(20); 2186a7a0bdbSAaron Liu psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 2196a7a0bdbSAaron Liu 0x80000000, 0x8000FFFF, false); 2206a7a0bdbSAaron Liu 2216a7a0bdbSAaron Liu /* Change IH ring for UMC */ 2226a7a0bdbSAaron Liu tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 2236a7a0bdbSAaron Liu tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 2246a7a0bdbSAaron Liu 2256a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 2266a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 2276a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 2286a7a0bdbSAaron Liu 2296a7a0bdbSAaron Liu mdelay(20); 2306a7a0bdbSAaron Liu psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 2316a7a0bdbSAaron Liu 0x80000000, 0x8000FFFF, false); 2326a7a0bdbSAaron Liu } 2336a7a0bdbSAaron Liu 2346a7a0bdbSAaron Liu static int psp_v12_0_ring_init(struct psp_context *psp, 2356a7a0bdbSAaron Liu enum psp_ring_type ring_type) 2366a7a0bdbSAaron Liu { 2376a7a0bdbSAaron Liu int ret = 0; 2386a7a0bdbSAaron Liu struct psp_ring *ring; 2396a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 2406a7a0bdbSAaron Liu 2416a7a0bdbSAaron Liu psp_v12_0_reroute_ih(psp); 2426a7a0bdbSAaron Liu 2436a7a0bdbSAaron Liu ring = &psp->km_ring; 2446a7a0bdbSAaron Liu 2456a7a0bdbSAaron Liu ring->ring_type = ring_type; 2466a7a0bdbSAaron Liu 2476a7a0bdbSAaron Liu /* allocate 4k Page of Local Frame Buffer memory for ring */ 2486a7a0bdbSAaron Liu ring->ring_size = 0x1000; 2496a7a0bdbSAaron Liu ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 2506a7a0bdbSAaron Liu AMDGPU_GEM_DOMAIN_VRAM, 2516a7a0bdbSAaron Liu &adev->firmware.rbuf, 2526a7a0bdbSAaron Liu &ring->ring_mem_mc_addr, 2536a7a0bdbSAaron Liu (void **)&ring->ring_mem); 2546a7a0bdbSAaron Liu if (ret) { 2556a7a0bdbSAaron Liu ring->ring_size = 0; 2566a7a0bdbSAaron Liu return ret; 2576a7a0bdbSAaron Liu } 2586a7a0bdbSAaron Liu 2596a7a0bdbSAaron Liu return 0; 2606a7a0bdbSAaron Liu } 2616a7a0bdbSAaron Liu 2626a7a0bdbSAaron Liu static int psp_v12_0_ring_create(struct psp_context *psp, 2636a7a0bdbSAaron Liu enum psp_ring_type ring_type) 2646a7a0bdbSAaron Liu { 2656a7a0bdbSAaron Liu int ret = 0; 2666a7a0bdbSAaron Liu unsigned int psp_ring_reg = 0; 2676a7a0bdbSAaron Liu struct psp_ring *ring = &psp->km_ring; 2686a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 2696a7a0bdbSAaron Liu 270a2676149SHawking Zhang if (amdgpu_sriov_vf(psp->adev)) { 2716a7a0bdbSAaron Liu /* Write low address of the ring to C2PMSG_102 */ 2726a7a0bdbSAaron Liu psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 2736a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 2746a7a0bdbSAaron Liu /* Write high address of the ring to C2PMSG_103 */ 2756a7a0bdbSAaron Liu psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 2766a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 2776a7a0bdbSAaron Liu 2786a7a0bdbSAaron Liu /* Write the ring initialization command to C2PMSG_101 */ 2796a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 2806a7a0bdbSAaron Liu GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 2816a7a0bdbSAaron Liu 2826a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */ 2836a7a0bdbSAaron Liu mdelay(20); 2846a7a0bdbSAaron Liu 2856a7a0bdbSAaron Liu /* Wait for response flag (bit 31) in C2PMSG_101 */ 2866a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 2876a7a0bdbSAaron Liu 0x80000000, 0x8000FFFF, false); 2886a7a0bdbSAaron Liu 2896a7a0bdbSAaron Liu } else { 2906a7a0bdbSAaron Liu /* Write low address of the ring to C2PMSG_69 */ 2916a7a0bdbSAaron Liu psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 2926a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 2936a7a0bdbSAaron Liu /* Write high address of the ring to C2PMSG_70 */ 2946a7a0bdbSAaron Liu psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 2956a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 2966a7a0bdbSAaron Liu /* Write size of ring to C2PMSG_71 */ 2976a7a0bdbSAaron Liu psp_ring_reg = ring->ring_size; 2986a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 2996a7a0bdbSAaron Liu /* Write the ring initialization command to C2PMSG_64 */ 3006a7a0bdbSAaron Liu psp_ring_reg = ring_type; 3016a7a0bdbSAaron Liu psp_ring_reg = psp_ring_reg << 16; 3026a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 3036a7a0bdbSAaron Liu 3046a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */ 3056a7a0bdbSAaron Liu mdelay(20); 3066a7a0bdbSAaron Liu 3076a7a0bdbSAaron Liu /* Wait for response flag (bit 31) in C2PMSG_64 */ 3086a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 3096a7a0bdbSAaron Liu 0x80000000, 0x8000FFFF, false); 3106a7a0bdbSAaron Liu } 3116a7a0bdbSAaron Liu 3126a7a0bdbSAaron Liu return ret; 3136a7a0bdbSAaron Liu } 3146a7a0bdbSAaron Liu 3156a7a0bdbSAaron Liu static int psp_v12_0_ring_stop(struct psp_context *psp, 3166a7a0bdbSAaron Liu enum psp_ring_type ring_type) 3176a7a0bdbSAaron Liu { 3186a7a0bdbSAaron Liu int ret = 0; 3196a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 3206a7a0bdbSAaron Liu 3216a7a0bdbSAaron Liu /* Write the ring destroy command*/ 322a2676149SHawking Zhang if (amdgpu_sriov_vf(adev)) 3236a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 3246a7a0bdbSAaron Liu GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 3256a7a0bdbSAaron Liu else 3266a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 3276a7a0bdbSAaron Liu GFX_CTRL_CMD_ID_DESTROY_RINGS); 3286a7a0bdbSAaron Liu 3296a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */ 3306a7a0bdbSAaron Liu mdelay(20); 3316a7a0bdbSAaron Liu 3326a7a0bdbSAaron Liu /* Wait for response flag (bit 31) */ 333a2676149SHawking Zhang if (amdgpu_sriov_vf(adev)) 3346a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 3356a7a0bdbSAaron Liu 0x80000000, 0x80000000, false); 3366a7a0bdbSAaron Liu else 3376a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 3386a7a0bdbSAaron Liu 0x80000000, 0x80000000, false); 3396a7a0bdbSAaron Liu 3406a7a0bdbSAaron Liu return ret; 3416a7a0bdbSAaron Liu } 3426a7a0bdbSAaron Liu 3436a7a0bdbSAaron Liu static int psp_v12_0_ring_destroy(struct psp_context *psp, 3446a7a0bdbSAaron Liu enum psp_ring_type ring_type) 3456a7a0bdbSAaron Liu { 3466a7a0bdbSAaron Liu int ret = 0; 3476a7a0bdbSAaron Liu struct psp_ring *ring = &psp->km_ring; 3486a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 3496a7a0bdbSAaron Liu 3506a7a0bdbSAaron Liu ret = psp_v12_0_ring_stop(psp, ring_type); 3516a7a0bdbSAaron Liu if (ret) 3526a7a0bdbSAaron Liu DRM_ERROR("Fail to stop psp ring\n"); 3536a7a0bdbSAaron Liu 3546a7a0bdbSAaron Liu amdgpu_bo_free_kernel(&adev->firmware.rbuf, 3556a7a0bdbSAaron Liu &ring->ring_mem_mc_addr, 3566a7a0bdbSAaron Liu (void **)&ring->ring_mem); 3576a7a0bdbSAaron Liu 3586a7a0bdbSAaron Liu return ret; 3596a7a0bdbSAaron Liu } 3606a7a0bdbSAaron Liu 3616a7a0bdbSAaron Liu static int psp_v12_0_mode1_reset(struct psp_context *psp) 3626a7a0bdbSAaron Liu { 3636a7a0bdbSAaron Liu int ret; 3646a7a0bdbSAaron Liu uint32_t offset; 3656a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 3666a7a0bdbSAaron Liu 3676a7a0bdbSAaron Liu offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 3686a7a0bdbSAaron Liu 3696a7a0bdbSAaron Liu ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 3706a7a0bdbSAaron Liu 3716a7a0bdbSAaron Liu if (ret) { 3726a7a0bdbSAaron Liu DRM_INFO("psp is not working correctly before mode1 reset!\n"); 3736a7a0bdbSAaron Liu return -EINVAL; 3746a7a0bdbSAaron Liu } 3756a7a0bdbSAaron Liu 3766a7a0bdbSAaron Liu /*send the mode 1 reset command*/ 3776a7a0bdbSAaron Liu WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 3786a7a0bdbSAaron Liu 3796a7a0bdbSAaron Liu msleep(500); 3806a7a0bdbSAaron Liu 3816a7a0bdbSAaron Liu offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 3826a7a0bdbSAaron Liu 3836a7a0bdbSAaron Liu ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 3846a7a0bdbSAaron Liu 3856a7a0bdbSAaron Liu if (ret) { 3866a7a0bdbSAaron Liu DRM_INFO("psp mode 1 reset failed!\n"); 3876a7a0bdbSAaron Liu return -EINVAL; 3886a7a0bdbSAaron Liu } 3896a7a0bdbSAaron Liu 3906a7a0bdbSAaron Liu DRM_INFO("psp mode1 reset succeed \n"); 3916a7a0bdbSAaron Liu 3926a7a0bdbSAaron Liu return 0; 3936a7a0bdbSAaron Liu } 3946a7a0bdbSAaron Liu 39513a390a6SHawking Zhang static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp) 39613a390a6SHawking Zhang { 39713a390a6SHawking Zhang uint32_t data; 39813a390a6SHawking Zhang struct amdgpu_device *adev = psp->adev; 39913a390a6SHawking Zhang 400a2676149SHawking Zhang if (amdgpu_sriov_vf(adev)) 40113a390a6SHawking Zhang data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 40213a390a6SHawking Zhang else 40313a390a6SHawking Zhang data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 40413a390a6SHawking Zhang 40513a390a6SHawking Zhang return data; 40613a390a6SHawking Zhang } 40713a390a6SHawking Zhang 40813a390a6SHawking Zhang static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 40913a390a6SHawking Zhang { 41013a390a6SHawking Zhang struct amdgpu_device *adev = psp->adev; 41113a390a6SHawking Zhang 412a2676149SHawking Zhang if (amdgpu_sriov_vf(adev)) { 41313a390a6SHawking Zhang WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 41413a390a6SHawking Zhang WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 41513a390a6SHawking Zhang } else 41613a390a6SHawking Zhang WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 41713a390a6SHawking Zhang } 41813a390a6SHawking Zhang 4196a7a0bdbSAaron Liu static const struct psp_funcs psp_v12_0_funcs = { 4206a7a0bdbSAaron Liu .init_microcode = psp_v12_0_init_microcode, 4216a7a0bdbSAaron Liu .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv, 4226a7a0bdbSAaron Liu .bootloader_load_sos = psp_v12_0_bootloader_load_sos, 4236a7a0bdbSAaron Liu .ring_init = psp_v12_0_ring_init, 4246a7a0bdbSAaron Liu .ring_create = psp_v12_0_ring_create, 4256a7a0bdbSAaron Liu .ring_stop = psp_v12_0_ring_stop, 4266a7a0bdbSAaron Liu .ring_destroy = psp_v12_0_ring_destroy, 4276a7a0bdbSAaron Liu .mode1_reset = psp_v12_0_mode1_reset, 42813a390a6SHawking Zhang .ring_get_wptr = psp_v12_0_ring_get_wptr, 42913a390a6SHawking Zhang .ring_set_wptr = psp_v12_0_ring_set_wptr, 4306a7a0bdbSAaron Liu }; 4316a7a0bdbSAaron Liu 4326a7a0bdbSAaron Liu void psp_v12_0_set_psp_funcs(struct psp_context *psp) 4336a7a0bdbSAaron Liu { 4346a7a0bdbSAaron Liu psp->funcs = &psp_v12_0_funcs; 4356a7a0bdbSAaron Liu } 436