16a7a0bdbSAaron Liu /* 26a7a0bdbSAaron Liu * Copyright 2019 Advanced Micro Devices, Inc. 36a7a0bdbSAaron Liu * 46a7a0bdbSAaron Liu * Permission is hereby granted, free of charge, to any person obtaining a 56a7a0bdbSAaron Liu * copy of this software and associated documentation files (the "Software"), 66a7a0bdbSAaron Liu * to deal in the Software without restriction, including without limitation 76a7a0bdbSAaron Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 86a7a0bdbSAaron Liu * and/or sell copies of the Software, and to permit persons to whom the 96a7a0bdbSAaron Liu * Software is furnished to do so, subject to the following conditions: 106a7a0bdbSAaron Liu * 116a7a0bdbSAaron Liu * The above copyright notice and this permission notice shall be included in 126a7a0bdbSAaron Liu * all copies or substantial portions of the Software. 136a7a0bdbSAaron Liu * 146a7a0bdbSAaron Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 156a7a0bdbSAaron Liu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 166a7a0bdbSAaron Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 176a7a0bdbSAaron Liu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 186a7a0bdbSAaron Liu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 196a7a0bdbSAaron Liu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 206a7a0bdbSAaron Liu * OTHER DEALINGS IN THE SOFTWARE. 216a7a0bdbSAaron Liu */ 226a7a0bdbSAaron Liu 236a7a0bdbSAaron Liu #include <linux/firmware.h> 242568cedcSStephen Rothwell #include <linux/module.h> 256a7a0bdbSAaron Liu #include "amdgpu.h" 266a7a0bdbSAaron Liu #include "amdgpu_psp.h" 276a7a0bdbSAaron Liu #include "amdgpu_ucode.h" 286a7a0bdbSAaron Liu #include "soc15_common.h" 296a7a0bdbSAaron Liu #include "psp_v12_0.h" 306a7a0bdbSAaron Liu 316a7a0bdbSAaron Liu #include "mp/mp_12_0_0_offset.h" 326a7a0bdbSAaron Liu #include "mp/mp_12_0_0_sh_mask.h" 336a7a0bdbSAaron Liu #include "gc/gc_9_0_offset.h" 346a7a0bdbSAaron Liu #include "sdma0/sdma0_4_0_offset.h" 356a7a0bdbSAaron Liu #include "nbio/nbio_7_4_offset.h" 366a7a0bdbSAaron Liu 376a7a0bdbSAaron Liu #include "oss/osssys_4_0_offset.h" 386a7a0bdbSAaron Liu #include "oss/osssys_4_0_sh_mask.h" 396a7a0bdbSAaron Liu 406a7a0bdbSAaron Liu MODULE_FIRMWARE("amdgpu/renoir_asd.bin"); 416a7a0bdbSAaron Liu /* address block */ 426a7a0bdbSAaron Liu #define smnMP1_FIRMWARE_FLAGS 0x3010024 436a7a0bdbSAaron Liu 446a7a0bdbSAaron Liu static int psp_v12_0_init_microcode(struct psp_context *psp) 456a7a0bdbSAaron Liu { 466a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 476a7a0bdbSAaron Liu const char *chip_name; 486a7a0bdbSAaron Liu char fw_name[30]; 496a7a0bdbSAaron Liu int err = 0; 506a7a0bdbSAaron Liu const struct psp_firmware_header_v1_0 *asd_hdr; 516a7a0bdbSAaron Liu 526a7a0bdbSAaron Liu DRM_DEBUG("\n"); 536a7a0bdbSAaron Liu 546a7a0bdbSAaron Liu switch (adev->asic_type) { 556a7a0bdbSAaron Liu case CHIP_RENOIR: 566a7a0bdbSAaron Liu chip_name = "renoir"; 576a7a0bdbSAaron Liu break; 586a7a0bdbSAaron Liu default: 596a7a0bdbSAaron Liu BUG(); 606a7a0bdbSAaron Liu } 616a7a0bdbSAaron Liu 626a7a0bdbSAaron Liu snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 636a7a0bdbSAaron Liu err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 646a7a0bdbSAaron Liu if (err) 656a7a0bdbSAaron Liu goto out1; 666a7a0bdbSAaron Liu 676a7a0bdbSAaron Liu err = amdgpu_ucode_validate(adev->psp.asd_fw); 686a7a0bdbSAaron Liu if (err) 696a7a0bdbSAaron Liu goto out1; 706a7a0bdbSAaron Liu 716a7a0bdbSAaron Liu asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 726a7a0bdbSAaron Liu adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 736a7a0bdbSAaron Liu adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 746a7a0bdbSAaron Liu adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 756a7a0bdbSAaron Liu adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 766a7a0bdbSAaron Liu le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 776a7a0bdbSAaron Liu 786a7a0bdbSAaron Liu return 0; 796a7a0bdbSAaron Liu 806a7a0bdbSAaron Liu out1: 816a7a0bdbSAaron Liu release_firmware(adev->psp.asd_fw); 826a7a0bdbSAaron Liu adev->psp.asd_fw = NULL; 836a7a0bdbSAaron Liu 846a7a0bdbSAaron Liu return err; 856a7a0bdbSAaron Liu } 866a7a0bdbSAaron Liu 876a7a0bdbSAaron Liu static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp) 886a7a0bdbSAaron Liu { 896a7a0bdbSAaron Liu int ret; 906a7a0bdbSAaron Liu uint32_t psp_gfxdrv_command_reg = 0; 916a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 926a7a0bdbSAaron Liu uint32_t sol_reg; 936a7a0bdbSAaron Liu 946a7a0bdbSAaron Liu /* Check sOS sign of life register to confirm sys driver and sOS 956a7a0bdbSAaron Liu * are already been loaded. 966a7a0bdbSAaron Liu */ 976a7a0bdbSAaron Liu sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 986a7a0bdbSAaron Liu if (sol_reg) { 996a7a0bdbSAaron Liu psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 1006a7a0bdbSAaron Liu printk("sos fw version = 0x%x.\n", psp->sos_fw_version); 1016a7a0bdbSAaron Liu return 0; 1026a7a0bdbSAaron Liu } 1036a7a0bdbSAaron Liu 1046a7a0bdbSAaron Liu /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 1056a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 1066a7a0bdbSAaron Liu 0x80000000, 0x80000000, false); 1076a7a0bdbSAaron Liu if (ret) 1086a7a0bdbSAaron Liu return ret; 1096a7a0bdbSAaron Liu 1106a7a0bdbSAaron Liu memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1116a7a0bdbSAaron Liu 1126a7a0bdbSAaron Liu /* Copy PSP System Driver binary to memory */ 1136a7a0bdbSAaron Liu memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 1146a7a0bdbSAaron Liu 1156a7a0bdbSAaron Liu /* Provide the sys driver to bootloader */ 1166a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 1176a7a0bdbSAaron Liu (uint32_t)(psp->fw_pri_mc_addr >> 20)); 1186a7a0bdbSAaron Liu psp_gfxdrv_command_reg = 1 << 16; 1196a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 1206a7a0bdbSAaron Liu psp_gfxdrv_command_reg); 1216a7a0bdbSAaron Liu 1226a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */ 1236a7a0bdbSAaron Liu mdelay(20); 1246a7a0bdbSAaron Liu 1256a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 1266a7a0bdbSAaron Liu 0x80000000, 0x80000000, false); 1276a7a0bdbSAaron Liu 1286a7a0bdbSAaron Liu return ret; 1296a7a0bdbSAaron Liu } 1306a7a0bdbSAaron Liu 1316a7a0bdbSAaron Liu static int psp_v12_0_bootloader_load_sos(struct psp_context *psp) 1326a7a0bdbSAaron Liu { 1336a7a0bdbSAaron Liu int ret; 1346a7a0bdbSAaron Liu unsigned int psp_gfxdrv_command_reg = 0; 1356a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 1366a7a0bdbSAaron Liu uint32_t sol_reg; 1376a7a0bdbSAaron Liu 1386a7a0bdbSAaron Liu /* Check sOS sign of life register to confirm sys driver and sOS 1396a7a0bdbSAaron Liu * are already been loaded. 1406a7a0bdbSAaron Liu */ 1416a7a0bdbSAaron Liu sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 1426a7a0bdbSAaron Liu if (sol_reg) 1436a7a0bdbSAaron Liu return 0; 1446a7a0bdbSAaron Liu 1456a7a0bdbSAaron Liu /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 1466a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 1476a7a0bdbSAaron Liu 0x80000000, 0x80000000, false); 1486a7a0bdbSAaron Liu if (ret) 1496a7a0bdbSAaron Liu return ret; 1506a7a0bdbSAaron Liu 1516a7a0bdbSAaron Liu memset(psp->fw_pri_buf, 0, PSP_1_MEG); 1526a7a0bdbSAaron Liu 1536a7a0bdbSAaron Liu /* Copy Secure OS binary to PSP memory */ 1546a7a0bdbSAaron Liu memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 1556a7a0bdbSAaron Liu 1566a7a0bdbSAaron Liu /* Provide the PSP secure OS to bootloader */ 1576a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 1586a7a0bdbSAaron Liu (uint32_t)(psp->fw_pri_mc_addr >> 20)); 1596a7a0bdbSAaron Liu psp_gfxdrv_command_reg = 2 << 16; 1606a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 1616a7a0bdbSAaron Liu psp_gfxdrv_command_reg); 1626a7a0bdbSAaron Liu 1636a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */ 1646a7a0bdbSAaron Liu mdelay(20); 1656a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 1666a7a0bdbSAaron Liu RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 1676a7a0bdbSAaron Liu 0, true); 1686a7a0bdbSAaron Liu 1696a7a0bdbSAaron Liu return ret; 1706a7a0bdbSAaron Liu } 1716a7a0bdbSAaron Liu 1726a7a0bdbSAaron Liu static void psp_v12_0_reroute_ih(struct psp_context *psp) 1736a7a0bdbSAaron Liu { 1746a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 1756a7a0bdbSAaron Liu uint32_t tmp; 1766a7a0bdbSAaron Liu 1776a7a0bdbSAaron Liu /* Change IH ring for VMC */ 1786a7a0bdbSAaron Liu tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 1796a7a0bdbSAaron Liu tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 1806a7a0bdbSAaron Liu tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 1816a7a0bdbSAaron Liu 1826a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 1836a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 1846a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 1856a7a0bdbSAaron Liu 1866a7a0bdbSAaron Liu mdelay(20); 1876a7a0bdbSAaron Liu psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 1886a7a0bdbSAaron Liu 0x80000000, 0x8000FFFF, false); 1896a7a0bdbSAaron Liu 1906a7a0bdbSAaron Liu /* Change IH ring for UMC */ 1916a7a0bdbSAaron Liu tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 1926a7a0bdbSAaron Liu tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 1936a7a0bdbSAaron Liu 1946a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 1956a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 1966a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 1976a7a0bdbSAaron Liu 1986a7a0bdbSAaron Liu mdelay(20); 1996a7a0bdbSAaron Liu psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 2006a7a0bdbSAaron Liu 0x80000000, 0x8000FFFF, false); 2016a7a0bdbSAaron Liu } 2026a7a0bdbSAaron Liu 2036a7a0bdbSAaron Liu static int psp_v12_0_ring_init(struct psp_context *psp, 2046a7a0bdbSAaron Liu enum psp_ring_type ring_type) 2056a7a0bdbSAaron Liu { 2066a7a0bdbSAaron Liu int ret = 0; 2076a7a0bdbSAaron Liu struct psp_ring *ring; 2086a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 2096a7a0bdbSAaron Liu 2106a7a0bdbSAaron Liu psp_v12_0_reroute_ih(psp); 2116a7a0bdbSAaron Liu 2126a7a0bdbSAaron Liu ring = &psp->km_ring; 2136a7a0bdbSAaron Liu 2146a7a0bdbSAaron Liu ring->ring_type = ring_type; 2156a7a0bdbSAaron Liu 2166a7a0bdbSAaron Liu /* allocate 4k Page of Local Frame Buffer memory for ring */ 2176a7a0bdbSAaron Liu ring->ring_size = 0x1000; 2186a7a0bdbSAaron Liu ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 2196a7a0bdbSAaron Liu AMDGPU_GEM_DOMAIN_VRAM, 2206a7a0bdbSAaron Liu &adev->firmware.rbuf, 2216a7a0bdbSAaron Liu &ring->ring_mem_mc_addr, 2226a7a0bdbSAaron Liu (void **)&ring->ring_mem); 2236a7a0bdbSAaron Liu if (ret) { 2246a7a0bdbSAaron Liu ring->ring_size = 0; 2256a7a0bdbSAaron Liu return ret; 2266a7a0bdbSAaron Liu } 2276a7a0bdbSAaron Liu 2286a7a0bdbSAaron Liu return 0; 2296a7a0bdbSAaron Liu } 2306a7a0bdbSAaron Liu 2316a7a0bdbSAaron Liu static bool psp_v12_0_support_vmr_ring(struct psp_context *psp) 2326a7a0bdbSAaron Liu { 2336a7a0bdbSAaron Liu if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045) 2346a7a0bdbSAaron Liu return true; 2356a7a0bdbSAaron Liu return false; 2366a7a0bdbSAaron Liu } 2376a7a0bdbSAaron Liu 2386a7a0bdbSAaron Liu static int psp_v12_0_ring_create(struct psp_context *psp, 2396a7a0bdbSAaron Liu enum psp_ring_type ring_type) 2406a7a0bdbSAaron Liu { 2416a7a0bdbSAaron Liu int ret = 0; 2426a7a0bdbSAaron Liu unsigned int psp_ring_reg = 0; 2436a7a0bdbSAaron Liu struct psp_ring *ring = &psp->km_ring; 2446a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 2456a7a0bdbSAaron Liu 2466a7a0bdbSAaron Liu if (psp_v12_0_support_vmr_ring(psp)) { 2476a7a0bdbSAaron Liu /* Write low address of the ring to C2PMSG_102 */ 2486a7a0bdbSAaron Liu psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 2496a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 2506a7a0bdbSAaron Liu /* Write high address of the ring to C2PMSG_103 */ 2516a7a0bdbSAaron Liu psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 2526a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 2536a7a0bdbSAaron Liu 2546a7a0bdbSAaron Liu /* Write the ring initialization command to C2PMSG_101 */ 2556a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 2566a7a0bdbSAaron Liu GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 2576a7a0bdbSAaron Liu 2586a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */ 2596a7a0bdbSAaron Liu mdelay(20); 2606a7a0bdbSAaron Liu 2616a7a0bdbSAaron Liu /* Wait for response flag (bit 31) in C2PMSG_101 */ 2626a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 2636a7a0bdbSAaron Liu 0x80000000, 0x8000FFFF, false); 2646a7a0bdbSAaron Liu 2656a7a0bdbSAaron Liu } else { 2666a7a0bdbSAaron Liu /* Write low address of the ring to C2PMSG_69 */ 2676a7a0bdbSAaron Liu psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 2686a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 2696a7a0bdbSAaron Liu /* Write high address of the ring to C2PMSG_70 */ 2706a7a0bdbSAaron Liu psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 2716a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 2726a7a0bdbSAaron Liu /* Write size of ring to C2PMSG_71 */ 2736a7a0bdbSAaron Liu psp_ring_reg = ring->ring_size; 2746a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 2756a7a0bdbSAaron Liu /* Write the ring initialization command to C2PMSG_64 */ 2766a7a0bdbSAaron Liu psp_ring_reg = ring_type; 2776a7a0bdbSAaron Liu psp_ring_reg = psp_ring_reg << 16; 2786a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 2796a7a0bdbSAaron Liu 2806a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */ 2816a7a0bdbSAaron Liu mdelay(20); 2826a7a0bdbSAaron Liu 2836a7a0bdbSAaron Liu /* Wait for response flag (bit 31) in C2PMSG_64 */ 2846a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 2856a7a0bdbSAaron Liu 0x80000000, 0x8000FFFF, false); 2866a7a0bdbSAaron Liu } 2876a7a0bdbSAaron Liu 2886a7a0bdbSAaron Liu return ret; 2896a7a0bdbSAaron Liu } 2906a7a0bdbSAaron Liu 2916a7a0bdbSAaron Liu static int psp_v12_0_ring_stop(struct psp_context *psp, 2926a7a0bdbSAaron Liu enum psp_ring_type ring_type) 2936a7a0bdbSAaron Liu { 2946a7a0bdbSAaron Liu int ret = 0; 2956a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 2966a7a0bdbSAaron Liu 2976a7a0bdbSAaron Liu /* Write the ring destroy command*/ 2986a7a0bdbSAaron Liu if (psp_v12_0_support_vmr_ring(psp)) 2996a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 3006a7a0bdbSAaron Liu GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 3016a7a0bdbSAaron Liu else 3026a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 3036a7a0bdbSAaron Liu GFX_CTRL_CMD_ID_DESTROY_RINGS); 3046a7a0bdbSAaron Liu 3056a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */ 3066a7a0bdbSAaron Liu mdelay(20); 3076a7a0bdbSAaron Liu 3086a7a0bdbSAaron Liu /* Wait for response flag (bit 31) */ 3096a7a0bdbSAaron Liu if (psp_v12_0_support_vmr_ring(psp)) 3106a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 3116a7a0bdbSAaron Liu 0x80000000, 0x80000000, false); 3126a7a0bdbSAaron Liu else 3136a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 3146a7a0bdbSAaron Liu 0x80000000, 0x80000000, false); 3156a7a0bdbSAaron Liu 3166a7a0bdbSAaron Liu return ret; 3176a7a0bdbSAaron Liu } 3186a7a0bdbSAaron Liu 3196a7a0bdbSAaron Liu static int psp_v12_0_ring_destroy(struct psp_context *psp, 3206a7a0bdbSAaron Liu enum psp_ring_type ring_type) 3216a7a0bdbSAaron Liu { 3226a7a0bdbSAaron Liu int ret = 0; 3236a7a0bdbSAaron Liu struct psp_ring *ring = &psp->km_ring; 3246a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 3256a7a0bdbSAaron Liu 3266a7a0bdbSAaron Liu ret = psp_v12_0_ring_stop(psp, ring_type); 3276a7a0bdbSAaron Liu if (ret) 3286a7a0bdbSAaron Liu DRM_ERROR("Fail to stop psp ring\n"); 3296a7a0bdbSAaron Liu 3306a7a0bdbSAaron Liu amdgpu_bo_free_kernel(&adev->firmware.rbuf, 3316a7a0bdbSAaron Liu &ring->ring_mem_mc_addr, 3326a7a0bdbSAaron Liu (void **)&ring->ring_mem); 3336a7a0bdbSAaron Liu 3346a7a0bdbSAaron Liu return ret; 3356a7a0bdbSAaron Liu } 3366a7a0bdbSAaron Liu 3376a7a0bdbSAaron Liu static int psp_v12_0_cmd_submit(struct psp_context *psp, 3386a7a0bdbSAaron Liu struct amdgpu_firmware_info *ucode, 3396a7a0bdbSAaron Liu uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 3406a7a0bdbSAaron Liu int index) 3416a7a0bdbSAaron Liu { 3426a7a0bdbSAaron Liu unsigned int psp_write_ptr_reg = 0; 3436a7a0bdbSAaron Liu struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem; 3446a7a0bdbSAaron Liu struct psp_ring *ring = &psp->km_ring; 3456a7a0bdbSAaron Liu struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 3466a7a0bdbSAaron Liu struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 3476a7a0bdbSAaron Liu ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 3486a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 3496a7a0bdbSAaron Liu uint32_t ring_size_dw = ring->ring_size / 4; 3506a7a0bdbSAaron Liu uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 3516a7a0bdbSAaron Liu 3526a7a0bdbSAaron Liu /* KM (GPCOM) prepare write pointer */ 3536a7a0bdbSAaron Liu if (psp_v12_0_support_vmr_ring(psp)) 3546a7a0bdbSAaron Liu psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 3556a7a0bdbSAaron Liu else 3566a7a0bdbSAaron Liu psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 3576a7a0bdbSAaron Liu 3586a7a0bdbSAaron Liu /* Update KM RB frame pointer to new frame */ 3596a7a0bdbSAaron Liu /* write_frame ptr increments by size of rb_frame in bytes */ 3606a7a0bdbSAaron Liu /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 3616a7a0bdbSAaron Liu if ((psp_write_ptr_reg % ring_size_dw) == 0) 3626a7a0bdbSAaron Liu write_frame = ring_buffer_start; 3636a7a0bdbSAaron Liu else 3646a7a0bdbSAaron Liu write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 3656a7a0bdbSAaron Liu /* Check invalid write_frame ptr address */ 3666a7a0bdbSAaron Liu if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 3676a7a0bdbSAaron Liu DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 3686a7a0bdbSAaron Liu ring_buffer_start, ring_buffer_end, write_frame); 3696a7a0bdbSAaron Liu DRM_ERROR("write_frame is pointing to address out of bounds\n"); 3706a7a0bdbSAaron Liu return -EINVAL; 3716a7a0bdbSAaron Liu } 3726a7a0bdbSAaron Liu 3736a7a0bdbSAaron Liu /* Initialize KM RB frame */ 3746a7a0bdbSAaron Liu memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 3756a7a0bdbSAaron Liu 3766a7a0bdbSAaron Liu /* Update KM RB frame */ 3776a7a0bdbSAaron Liu write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 3786a7a0bdbSAaron Liu write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 3796a7a0bdbSAaron Liu write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 3806a7a0bdbSAaron Liu write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 3816a7a0bdbSAaron Liu write_frame->fence_value = index; 3826a7a0bdbSAaron Liu 3836a7a0bdbSAaron Liu /* Update the write Pointer in DWORDs */ 3846a7a0bdbSAaron Liu psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 3856a7a0bdbSAaron Liu if (psp_v12_0_support_vmr_ring(psp)) { 3866a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg); 3876a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 3886a7a0bdbSAaron Liu } else 3896a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 3906a7a0bdbSAaron Liu 3916a7a0bdbSAaron Liu return 0; 3926a7a0bdbSAaron Liu } 3936a7a0bdbSAaron Liu 3946a7a0bdbSAaron Liu static int 3956a7a0bdbSAaron Liu psp_v12_0_sram_map(struct amdgpu_device *adev, 3966a7a0bdbSAaron Liu unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 3976a7a0bdbSAaron Liu unsigned int *sram_data_reg_offset, 3986a7a0bdbSAaron Liu enum AMDGPU_UCODE_ID ucode_id) 3996a7a0bdbSAaron Liu { 4006a7a0bdbSAaron Liu int ret = 0; 4016a7a0bdbSAaron Liu 4026a7a0bdbSAaron Liu switch (ucode_id) { 4036a7a0bdbSAaron Liu /* TODO: needs to confirm */ 4046a7a0bdbSAaron Liu #if 0 4056a7a0bdbSAaron Liu case AMDGPU_UCODE_ID_SMC: 4066a7a0bdbSAaron Liu *sram_offset = 0; 4076a7a0bdbSAaron Liu *sram_addr_reg_offset = 0; 4086a7a0bdbSAaron Liu *sram_data_reg_offset = 0; 4096a7a0bdbSAaron Liu break; 4106a7a0bdbSAaron Liu #endif 4116a7a0bdbSAaron Liu 4126a7a0bdbSAaron Liu case AMDGPU_UCODE_ID_CP_CE: 4136a7a0bdbSAaron Liu *sram_offset = 0x0; 4146a7a0bdbSAaron Liu *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 4156a7a0bdbSAaron Liu *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 4166a7a0bdbSAaron Liu break; 4176a7a0bdbSAaron Liu 4186a7a0bdbSAaron Liu case AMDGPU_UCODE_ID_CP_PFP: 4196a7a0bdbSAaron Liu *sram_offset = 0x0; 4206a7a0bdbSAaron Liu *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 4216a7a0bdbSAaron Liu *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 4226a7a0bdbSAaron Liu break; 4236a7a0bdbSAaron Liu 4246a7a0bdbSAaron Liu case AMDGPU_UCODE_ID_CP_ME: 4256a7a0bdbSAaron Liu *sram_offset = 0x0; 4266a7a0bdbSAaron Liu *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 4276a7a0bdbSAaron Liu *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 4286a7a0bdbSAaron Liu break; 4296a7a0bdbSAaron Liu 4306a7a0bdbSAaron Liu case AMDGPU_UCODE_ID_CP_MEC1: 4316a7a0bdbSAaron Liu *sram_offset = 0x10000; 4326a7a0bdbSAaron Liu *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 4336a7a0bdbSAaron Liu *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 4346a7a0bdbSAaron Liu break; 4356a7a0bdbSAaron Liu 4366a7a0bdbSAaron Liu case AMDGPU_UCODE_ID_CP_MEC2: 4376a7a0bdbSAaron Liu *sram_offset = 0x10000; 4386a7a0bdbSAaron Liu *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 4396a7a0bdbSAaron Liu *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 4406a7a0bdbSAaron Liu break; 4416a7a0bdbSAaron Liu 4426a7a0bdbSAaron Liu case AMDGPU_UCODE_ID_RLC_G: 4436a7a0bdbSAaron Liu *sram_offset = 0x2000; 4446a7a0bdbSAaron Liu *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 4456a7a0bdbSAaron Liu *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 4466a7a0bdbSAaron Liu break; 4476a7a0bdbSAaron Liu 4486a7a0bdbSAaron Liu case AMDGPU_UCODE_ID_SDMA0: 4496a7a0bdbSAaron Liu *sram_offset = 0x0; 4506a7a0bdbSAaron Liu *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 4516a7a0bdbSAaron Liu *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 4526a7a0bdbSAaron Liu break; 4536a7a0bdbSAaron Liu 4546a7a0bdbSAaron Liu /* TODO: needs to confirm */ 4556a7a0bdbSAaron Liu #if 0 4566a7a0bdbSAaron Liu case AMDGPU_UCODE_ID_SDMA1: 4576a7a0bdbSAaron Liu *sram_offset = ; 4586a7a0bdbSAaron Liu *sram_addr_reg_offset = ; 4596a7a0bdbSAaron Liu break; 4606a7a0bdbSAaron Liu 4616a7a0bdbSAaron Liu case AMDGPU_UCODE_ID_UVD: 4626a7a0bdbSAaron Liu *sram_offset = ; 4636a7a0bdbSAaron Liu *sram_addr_reg_offset = ; 4646a7a0bdbSAaron Liu break; 4656a7a0bdbSAaron Liu 4666a7a0bdbSAaron Liu case AMDGPU_UCODE_ID_VCE: 4676a7a0bdbSAaron Liu *sram_offset = ; 4686a7a0bdbSAaron Liu *sram_addr_reg_offset = ; 4696a7a0bdbSAaron Liu break; 4706a7a0bdbSAaron Liu #endif 4716a7a0bdbSAaron Liu 4726a7a0bdbSAaron Liu case AMDGPU_UCODE_ID_MAXIMUM: 4736a7a0bdbSAaron Liu default: 4746a7a0bdbSAaron Liu ret = -EINVAL; 4756a7a0bdbSAaron Liu break; 4766a7a0bdbSAaron Liu } 4776a7a0bdbSAaron Liu 4786a7a0bdbSAaron Liu return ret; 4796a7a0bdbSAaron Liu } 4806a7a0bdbSAaron Liu 4816a7a0bdbSAaron Liu static bool psp_v12_0_compare_sram_data(struct psp_context *psp, 4826a7a0bdbSAaron Liu struct amdgpu_firmware_info *ucode, 4836a7a0bdbSAaron Liu enum AMDGPU_UCODE_ID ucode_type) 4846a7a0bdbSAaron Liu { 4856a7a0bdbSAaron Liu int err = 0; 4866a7a0bdbSAaron Liu unsigned int fw_sram_reg_val = 0; 4876a7a0bdbSAaron Liu unsigned int fw_sram_addr_reg_offset = 0; 4886a7a0bdbSAaron Liu unsigned int fw_sram_data_reg_offset = 0; 4896a7a0bdbSAaron Liu unsigned int ucode_size; 4906a7a0bdbSAaron Liu uint32_t *ucode_mem = NULL; 4916a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 4926a7a0bdbSAaron Liu 4936a7a0bdbSAaron Liu err = psp_v12_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 4946a7a0bdbSAaron Liu &fw_sram_data_reg_offset, ucode_type); 4956a7a0bdbSAaron Liu if (err) 4966a7a0bdbSAaron Liu return false; 4976a7a0bdbSAaron Liu 4986a7a0bdbSAaron Liu WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 4996a7a0bdbSAaron Liu 5006a7a0bdbSAaron Liu ucode_size = ucode->ucode_size; 5016a7a0bdbSAaron Liu ucode_mem = (uint32_t *)ucode->kaddr; 5026a7a0bdbSAaron Liu while (ucode_size) { 5036a7a0bdbSAaron Liu fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 5046a7a0bdbSAaron Liu 5056a7a0bdbSAaron Liu if (*ucode_mem != fw_sram_reg_val) 5066a7a0bdbSAaron Liu return false; 5076a7a0bdbSAaron Liu 5086a7a0bdbSAaron Liu ucode_mem++; 5096a7a0bdbSAaron Liu /* 4 bytes */ 5106a7a0bdbSAaron Liu ucode_size -= 4; 5116a7a0bdbSAaron Liu } 5126a7a0bdbSAaron Liu 5136a7a0bdbSAaron Liu return true; 5146a7a0bdbSAaron Liu } 5156a7a0bdbSAaron Liu 5166a7a0bdbSAaron Liu static int psp_v12_0_mode1_reset(struct psp_context *psp) 5176a7a0bdbSAaron Liu { 5186a7a0bdbSAaron Liu int ret; 5196a7a0bdbSAaron Liu uint32_t offset; 5206a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev; 5216a7a0bdbSAaron Liu 5226a7a0bdbSAaron Liu offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 5236a7a0bdbSAaron Liu 5246a7a0bdbSAaron Liu ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 5256a7a0bdbSAaron Liu 5266a7a0bdbSAaron Liu if (ret) { 5276a7a0bdbSAaron Liu DRM_INFO("psp is not working correctly before mode1 reset!\n"); 5286a7a0bdbSAaron Liu return -EINVAL; 5296a7a0bdbSAaron Liu } 5306a7a0bdbSAaron Liu 5316a7a0bdbSAaron Liu /*send the mode 1 reset command*/ 5326a7a0bdbSAaron Liu WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 5336a7a0bdbSAaron Liu 5346a7a0bdbSAaron Liu msleep(500); 5356a7a0bdbSAaron Liu 5366a7a0bdbSAaron Liu offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 5376a7a0bdbSAaron Liu 5386a7a0bdbSAaron Liu ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 5396a7a0bdbSAaron Liu 5406a7a0bdbSAaron Liu if (ret) { 5416a7a0bdbSAaron Liu DRM_INFO("psp mode 1 reset failed!\n"); 5426a7a0bdbSAaron Liu return -EINVAL; 5436a7a0bdbSAaron Liu } 5446a7a0bdbSAaron Liu 5456a7a0bdbSAaron Liu DRM_INFO("psp mode1 reset succeed \n"); 5466a7a0bdbSAaron Liu 5476a7a0bdbSAaron Liu return 0; 5486a7a0bdbSAaron Liu } 5496a7a0bdbSAaron Liu 5506a7a0bdbSAaron Liu static const struct psp_funcs psp_v12_0_funcs = { 5516a7a0bdbSAaron Liu .init_microcode = psp_v12_0_init_microcode, 5526a7a0bdbSAaron Liu .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv, 5536a7a0bdbSAaron Liu .bootloader_load_sos = psp_v12_0_bootloader_load_sos, 5546a7a0bdbSAaron Liu .ring_init = psp_v12_0_ring_init, 5556a7a0bdbSAaron Liu .ring_create = psp_v12_0_ring_create, 5566a7a0bdbSAaron Liu .ring_stop = psp_v12_0_ring_stop, 5576a7a0bdbSAaron Liu .ring_destroy = psp_v12_0_ring_destroy, 5586a7a0bdbSAaron Liu .cmd_submit = psp_v12_0_cmd_submit, 5596a7a0bdbSAaron Liu .compare_sram_data = psp_v12_0_compare_sram_data, 5606a7a0bdbSAaron Liu .mode1_reset = psp_v12_0_mode1_reset, 5616a7a0bdbSAaron Liu }; 5626a7a0bdbSAaron Liu 5636a7a0bdbSAaron Liu void psp_v12_0_set_psp_funcs(struct psp_context *psp) 5646a7a0bdbSAaron Liu { 5656a7a0bdbSAaron Liu psp->funcs = &psp_v12_0_funcs; 5666a7a0bdbSAaron Liu } 567