1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "amdgpu_psp.h" 26 #include "amdgpu_ucode.h" 27 #include "soc15_common.h" 28 #include "psp_v11_0.h" 29 30 #include "mp/mp_11_0_offset.h" 31 #include "mp/mp_11_0_sh_mask.h" 32 #include "gc/gc_9_0_offset.h" 33 #include "sdma0/sdma0_4_0_offset.h" 34 #include "nbio/nbio_7_4_offset.h" 35 36 #include "oss/osssys_4_0_offset.h" 37 #include "oss/osssys_4_0_sh_mask.h" 38 39 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 40 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 41 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 42 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 43 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 44 45 /* address block */ 46 #define smnMP1_FIRMWARE_FLAGS 0x3010024 47 /* navi10 reg offset define */ 48 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 49 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 50 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 51 #define mmSDMA0_UCODE_DATA_NV10 0x5881 52 53 static int psp_v11_0_init_microcode(struct psp_context *psp) 54 { 55 struct amdgpu_device *adev = psp->adev; 56 const char *chip_name; 57 char fw_name[30]; 58 int err = 0; 59 const struct psp_firmware_header_v1_0 *sos_hdr; 60 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 61 const struct psp_firmware_header_v1_0 *asd_hdr; 62 const struct ta_firmware_header_v1_0 *ta_hdr; 63 64 DRM_DEBUG("\n"); 65 66 switch (adev->asic_type) { 67 case CHIP_VEGA20: 68 chip_name = "vega20"; 69 break; 70 case CHIP_NAVI10: 71 chip_name = "navi10"; 72 break; 73 default: 74 BUG(); 75 } 76 77 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 78 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 79 if (err) 80 goto out; 81 82 err = amdgpu_ucode_validate(adev->psp.sos_fw); 83 if (err) 84 goto out; 85 86 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 87 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 88 89 switch (sos_hdr->header.header_version_major) { 90 case 1: 91 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 92 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 93 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 94 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 95 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 96 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 97 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 98 le32_to_cpu(sos_hdr->sos_offset_bytes); 99 if (sos_hdr->header.header_version_minor == 1) { 100 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 101 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 102 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 103 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 104 } 105 break; 106 default: 107 dev_err(adev->dev, 108 "Unsupported psp sos firmware\n"); 109 err = -EINVAL; 110 goto out; 111 } 112 113 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 114 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 115 if (err) 116 goto out1; 117 118 err = amdgpu_ucode_validate(adev->psp.asd_fw); 119 if (err) 120 goto out1; 121 122 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 123 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 124 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 125 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 126 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 127 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 128 129 switch (adev->asic_type) { 130 case CHIP_VEGA20: 131 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 132 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 133 if (err) { 134 release_firmware(adev->psp.ta_fw); 135 adev->psp.ta_fw = NULL; 136 dev_info(adev->dev, 137 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 138 } else { 139 err = amdgpu_ucode_validate(adev->psp.ta_fw); 140 if (err) 141 goto out2; 142 143 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 144 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 145 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 146 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 147 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 148 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 149 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); 150 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); 151 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + 152 le32_to_cpu(ta_hdr->ta_ras_offset_bytes); 153 } 154 break; 155 case CHIP_NAVI10: 156 break; 157 default: 158 BUG(); 159 } 160 161 return 0; 162 163 out2: 164 release_firmware(adev->psp.ta_fw); 165 adev->psp.ta_fw = NULL; 166 out1: 167 release_firmware(adev->psp.asd_fw); 168 adev->psp.asd_fw = NULL; 169 out: 170 dev_err(adev->dev, 171 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 172 release_firmware(adev->psp.sos_fw); 173 adev->psp.sos_fw = NULL; 174 175 return err; 176 } 177 178 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 179 { 180 int ret; 181 uint32_t psp_gfxdrv_command_reg = 0; 182 struct amdgpu_device *adev = psp->adev; 183 uint32_t sol_reg; 184 185 /* Check sOS sign of life register to confirm sys driver and sOS 186 * are already been loaded. 187 */ 188 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 189 if (sol_reg) { 190 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 191 printk("sos fw version = 0x%x.\n", psp->sos_fw_version); 192 return 0; 193 } 194 195 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 196 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 197 0x80000000, 0x80000000, false); 198 if (ret) 199 return ret; 200 201 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 202 203 /* Copy PSP System Driver binary to memory */ 204 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 205 206 /* Provide the sys driver to bootloader */ 207 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 208 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 209 psp_gfxdrv_command_reg = 1 << 16; 210 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 211 psp_gfxdrv_command_reg); 212 213 /* there might be handshake issue with hardware which needs delay */ 214 mdelay(20); 215 216 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 217 0x80000000, 0x80000000, false); 218 219 return ret; 220 } 221 222 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 223 { 224 int ret; 225 unsigned int psp_gfxdrv_command_reg = 0; 226 struct amdgpu_device *adev = psp->adev; 227 uint32_t sol_reg; 228 229 /* Check sOS sign of life register to confirm sys driver and sOS 230 * are already been loaded. 231 */ 232 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 233 if (sol_reg) 234 return 0; 235 236 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 237 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 238 0x80000000, 0x80000000, false); 239 if (ret) 240 return ret; 241 242 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 243 244 /* Copy Secure OS binary to PSP memory */ 245 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 246 247 /* Provide the PSP secure OS to bootloader */ 248 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 249 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 250 psp_gfxdrv_command_reg = 2 << 16; 251 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 252 psp_gfxdrv_command_reg); 253 254 /* there might be handshake issue with hardware which needs delay */ 255 mdelay(20); 256 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 257 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 258 0, true); 259 260 return ret; 261 } 262 263 static void psp_v11_0_reroute_ih(struct psp_context *psp) 264 { 265 struct amdgpu_device *adev = psp->adev; 266 uint32_t tmp; 267 268 /* Change IH ring for VMC */ 269 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 270 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 271 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 272 273 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 274 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 275 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 276 277 mdelay(20); 278 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 279 0x80000000, 0x8000FFFF, false); 280 281 /* Change IH ring for UMC */ 282 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 283 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 284 285 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 286 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 287 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 288 289 mdelay(20); 290 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 291 0x80000000, 0x8000FFFF, false); 292 } 293 294 static int psp_v11_0_ring_init(struct psp_context *psp, 295 enum psp_ring_type ring_type) 296 { 297 int ret = 0; 298 struct psp_ring *ring; 299 struct amdgpu_device *adev = psp->adev; 300 301 psp_v11_0_reroute_ih(psp); 302 303 ring = &psp->km_ring; 304 305 ring->ring_type = ring_type; 306 307 /* allocate 4k Page of Local Frame Buffer memory for ring */ 308 ring->ring_size = 0x1000; 309 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 310 AMDGPU_GEM_DOMAIN_VRAM, 311 &adev->firmware.rbuf, 312 &ring->ring_mem_mc_addr, 313 (void **)&ring->ring_mem); 314 if (ret) { 315 ring->ring_size = 0; 316 return ret; 317 } 318 319 return 0; 320 } 321 322 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp) 323 { 324 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045) 325 return true; 326 return false; 327 } 328 329 static int psp_v11_0_ring_create(struct psp_context *psp, 330 enum psp_ring_type ring_type) 331 { 332 int ret = 0; 333 unsigned int psp_ring_reg = 0; 334 struct psp_ring *ring = &psp->km_ring; 335 struct amdgpu_device *adev = psp->adev; 336 337 if (psp_v11_0_support_vmr_ring(psp)) { 338 /* Write low address of the ring to C2PMSG_102 */ 339 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 340 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 341 /* Write high address of the ring to C2PMSG_103 */ 342 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 343 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 344 345 /* Write the ring initialization command to C2PMSG_101 */ 346 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 347 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 348 349 /* there might be handshake issue with hardware which needs delay */ 350 mdelay(20); 351 352 /* Wait for response flag (bit 31) in C2PMSG_101 */ 353 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 354 0x80000000, 0x8000FFFF, false); 355 356 } else { 357 /* Write low address of the ring to C2PMSG_69 */ 358 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 359 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 360 /* Write high address of the ring to C2PMSG_70 */ 361 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 362 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 363 /* Write size of ring to C2PMSG_71 */ 364 psp_ring_reg = ring->ring_size; 365 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 366 /* Write the ring initialization command to C2PMSG_64 */ 367 psp_ring_reg = ring_type; 368 psp_ring_reg = psp_ring_reg << 16; 369 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 370 371 /* there might be handshake issue with hardware which needs delay */ 372 mdelay(20); 373 374 /* Wait for response flag (bit 31) in C2PMSG_64 */ 375 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 376 0x80000000, 0x8000FFFF, false); 377 } 378 379 return ret; 380 } 381 382 static int psp_v11_0_ring_stop(struct psp_context *psp, 383 enum psp_ring_type ring_type) 384 { 385 int ret = 0; 386 struct amdgpu_device *adev = psp->adev; 387 388 /* Write the ring destroy command*/ 389 if (psp_v11_0_support_vmr_ring(psp)) 390 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 391 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 392 else 393 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 394 GFX_CTRL_CMD_ID_DESTROY_RINGS); 395 396 /* there might be handshake issue with hardware which needs delay */ 397 mdelay(20); 398 399 /* Wait for response flag (bit 31) */ 400 if (psp_v11_0_support_vmr_ring(psp)) 401 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 402 0x80000000, 0x80000000, false); 403 else 404 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 405 0x80000000, 0x80000000, false); 406 407 return ret; 408 } 409 410 static int psp_v11_0_ring_destroy(struct psp_context *psp, 411 enum psp_ring_type ring_type) 412 { 413 int ret = 0; 414 struct psp_ring *ring = &psp->km_ring; 415 struct amdgpu_device *adev = psp->adev; 416 417 ret = psp_v11_0_ring_stop(psp, ring_type); 418 if (ret) 419 DRM_ERROR("Fail to stop psp ring\n"); 420 421 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 422 &ring->ring_mem_mc_addr, 423 (void **)&ring->ring_mem); 424 425 return ret; 426 } 427 428 static int psp_v11_0_cmd_submit(struct psp_context *psp, 429 struct amdgpu_firmware_info *ucode, 430 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 431 int index) 432 { 433 unsigned int psp_write_ptr_reg = 0; 434 struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem; 435 struct psp_ring *ring = &psp->km_ring; 436 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 437 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 438 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 439 struct amdgpu_device *adev = psp->adev; 440 uint32_t ring_size_dw = ring->ring_size / 4; 441 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 442 443 /* KM (GPCOM) prepare write pointer */ 444 if (psp_v11_0_support_vmr_ring(psp)) 445 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 446 else 447 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 448 449 /* Update KM RB frame pointer to new frame */ 450 /* write_frame ptr increments by size of rb_frame in bytes */ 451 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 452 if ((psp_write_ptr_reg % ring_size_dw) == 0) 453 write_frame = ring_buffer_start; 454 else 455 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 456 /* Check invalid write_frame ptr address */ 457 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 458 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 459 ring_buffer_start, ring_buffer_end, write_frame); 460 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 461 return -EINVAL; 462 } 463 464 /* Initialize KM RB frame */ 465 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 466 467 /* Update KM RB frame */ 468 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 469 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 470 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 471 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 472 write_frame->fence_value = index; 473 474 /* Update the write Pointer in DWORDs */ 475 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 476 if (psp_v11_0_support_vmr_ring(psp)) { 477 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg); 478 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 479 } else 480 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 481 482 return 0; 483 } 484 485 static int 486 psp_v11_0_sram_map(struct amdgpu_device *adev, 487 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 488 unsigned int *sram_data_reg_offset, 489 enum AMDGPU_UCODE_ID ucode_id) 490 { 491 int ret = 0; 492 493 switch (ucode_id) { 494 /* TODO: needs to confirm */ 495 #if 0 496 case AMDGPU_UCODE_ID_SMC: 497 *sram_offset = 0; 498 *sram_addr_reg_offset = 0; 499 *sram_data_reg_offset = 0; 500 break; 501 #endif 502 503 case AMDGPU_UCODE_ID_CP_CE: 504 *sram_offset = 0x0; 505 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 506 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 507 break; 508 509 case AMDGPU_UCODE_ID_CP_PFP: 510 *sram_offset = 0x0; 511 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 512 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 513 break; 514 515 case AMDGPU_UCODE_ID_CP_ME: 516 *sram_offset = 0x0; 517 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 518 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 519 break; 520 521 case AMDGPU_UCODE_ID_CP_MEC1: 522 *sram_offset = 0x10000; 523 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 524 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 525 break; 526 527 case AMDGPU_UCODE_ID_CP_MEC2: 528 *sram_offset = 0x10000; 529 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 530 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 531 break; 532 533 case AMDGPU_UCODE_ID_RLC_G: 534 *sram_offset = 0x2000; 535 if (adev->asic_type != CHIP_NAVI10) { 536 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 537 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 538 } else { 539 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10; 540 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10; 541 } 542 break; 543 544 case AMDGPU_UCODE_ID_SDMA0: 545 *sram_offset = 0x0; 546 if (adev->asic_type != CHIP_NAVI10) { 547 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 548 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 549 } else { 550 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10; 551 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10; 552 } 553 break; 554 555 /* TODO: needs to confirm */ 556 #if 0 557 case AMDGPU_UCODE_ID_SDMA1: 558 *sram_offset = ; 559 *sram_addr_reg_offset = ; 560 break; 561 562 case AMDGPU_UCODE_ID_UVD: 563 *sram_offset = ; 564 *sram_addr_reg_offset = ; 565 break; 566 567 case AMDGPU_UCODE_ID_VCE: 568 *sram_offset = ; 569 *sram_addr_reg_offset = ; 570 break; 571 #endif 572 573 case AMDGPU_UCODE_ID_MAXIMUM: 574 default: 575 ret = -EINVAL; 576 break; 577 } 578 579 return ret; 580 } 581 582 static bool psp_v11_0_compare_sram_data(struct psp_context *psp, 583 struct amdgpu_firmware_info *ucode, 584 enum AMDGPU_UCODE_ID ucode_type) 585 { 586 int err = 0; 587 unsigned int fw_sram_reg_val = 0; 588 unsigned int fw_sram_addr_reg_offset = 0; 589 unsigned int fw_sram_data_reg_offset = 0; 590 unsigned int ucode_size; 591 uint32_t *ucode_mem = NULL; 592 struct amdgpu_device *adev = psp->adev; 593 594 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 595 &fw_sram_data_reg_offset, ucode_type); 596 if (err) 597 return false; 598 599 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 600 601 ucode_size = ucode->ucode_size; 602 ucode_mem = (uint32_t *)ucode->kaddr; 603 while (ucode_size) { 604 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 605 606 if (*ucode_mem != fw_sram_reg_val) 607 return false; 608 609 ucode_mem++; 610 /* 4 bytes */ 611 ucode_size -= 4; 612 } 613 614 return true; 615 } 616 617 static int psp_v11_0_mode1_reset(struct psp_context *psp) 618 { 619 int ret; 620 uint32_t offset; 621 struct amdgpu_device *adev = psp->adev; 622 623 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 624 625 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 626 627 if (ret) { 628 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 629 return -EINVAL; 630 } 631 632 /*send the mode 1 reset command*/ 633 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 634 635 msleep(500); 636 637 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 638 639 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 640 641 if (ret) { 642 DRM_INFO("psp mode 1 reset failed!\n"); 643 return -EINVAL; 644 } 645 646 DRM_INFO("psp mode1 reset succeed \n"); 647 648 return 0; 649 } 650 651 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready. 652 * For now, return success and hack the hive_id so high level code can 653 * start testing 654 */ 655 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp, 656 int number_devices, struct psp_xgmi_topology_info *topology) 657 { 658 struct ta_xgmi_shared_memory *xgmi_cmd; 659 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 660 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 661 int i; 662 int ret; 663 664 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 665 return -EINVAL; 666 667 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 668 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 669 670 /* Fill in the shared memory with topology information as input */ 671 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 672 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 673 topology_info_input->num_nodes = number_devices; 674 675 for (i = 0; i < topology_info_input->num_nodes; i++) { 676 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 677 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 678 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 679 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 680 } 681 682 /* Invoke xgmi ta to get the topology information */ 683 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 684 if (ret) 685 return ret; 686 687 /* Read the output topology information from the shared memory */ 688 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 689 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 690 for (i = 0; i < topology->num_nodes; i++) { 691 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 692 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 693 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 694 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 695 } 696 697 return 0; 698 } 699 700 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp, 701 int number_devices, struct psp_xgmi_topology_info *topology) 702 { 703 struct ta_xgmi_shared_memory *xgmi_cmd; 704 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 705 int i; 706 707 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 708 return -EINVAL; 709 710 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 711 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 712 713 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 714 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 715 topology_info_input->num_nodes = number_devices; 716 717 for (i = 0; i < topology_info_input->num_nodes; i++) { 718 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 719 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 720 topology_info_input->nodes[i].is_sharing_enabled = 1; 721 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 722 } 723 724 /* Invoke xgmi ta to set topology information */ 725 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 726 } 727 728 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 729 { 730 struct ta_xgmi_shared_memory *xgmi_cmd; 731 int ret; 732 733 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 734 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 735 736 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 737 738 /* Invoke xgmi ta to get hive id */ 739 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 740 if (ret) 741 return ret; 742 743 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 744 745 return 0; 746 } 747 748 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 749 { 750 struct ta_xgmi_shared_memory *xgmi_cmd; 751 int ret; 752 753 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 754 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 755 756 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 757 758 /* Invoke xgmi ta to get the node id */ 759 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 760 if (ret) 761 return ret; 762 763 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 764 765 return 0; 766 } 767 768 static int psp_v11_0_ras_trigger_error(struct psp_context *psp, 769 struct ta_ras_trigger_error_input *info) 770 { 771 struct ta_ras_shared_memory *ras_cmd; 772 int ret; 773 774 if (!psp->ras.ras_initialized) 775 return -EINVAL; 776 777 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 778 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 779 780 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 781 ras_cmd->ras_in_message.trigger_error = *info; 782 783 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 784 if (ret) 785 return -EINVAL; 786 787 return ras_cmd->ras_status; 788 } 789 790 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr) 791 { 792 #if 0 793 // not support yet. 794 struct ta_ras_shared_memory *ras_cmd; 795 int ret; 796 797 if (!psp->ras.ras_initialized) 798 return -EINVAL; 799 800 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 801 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 802 803 ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON; 804 ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr; 805 806 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 807 if (ret) 808 return -EINVAL; 809 810 return ras_cmd->ras_status; 811 #else 812 return -EINVAL; 813 #endif 814 } 815 816 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp) 817 { 818 return psp_rlc_autoload_start(psp); 819 } 820 821 static const struct psp_funcs psp_v11_0_funcs = { 822 .init_microcode = psp_v11_0_init_microcode, 823 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 824 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 825 .ring_init = psp_v11_0_ring_init, 826 .ring_create = psp_v11_0_ring_create, 827 .ring_stop = psp_v11_0_ring_stop, 828 .ring_destroy = psp_v11_0_ring_destroy, 829 .cmd_submit = psp_v11_0_cmd_submit, 830 .compare_sram_data = psp_v11_0_compare_sram_data, 831 .mode1_reset = psp_v11_0_mode1_reset, 832 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info, 833 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info, 834 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id, 835 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id, 836 .support_vmr_ring = psp_v11_0_support_vmr_ring, 837 .ras_trigger_error = psp_v11_0_ras_trigger_error, 838 .ras_cure_posion = psp_v11_0_ras_cure_posion, 839 .rlc_autoload_start = psp_v11_0_rlc_autoload_start, 840 }; 841 842 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 843 { 844 psp->funcs = &psp_v11_0_funcs; 845 } 846