1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "amdgpu_psp.h" 26 #include "amdgpu_ucode.h" 27 #include "soc15_common.h" 28 #include "psp_v11_0.h" 29 30 #include "mp/mp_11_0_offset.h" 31 #include "mp/mp_11_0_sh_mask.h" 32 #include "gc/gc_9_0_offset.h" 33 #include "sdma0/sdma0_4_0_offset.h" 34 #include "nbio/nbio_7_4_offset.h" 35 36 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 37 38 /* address block */ 39 #define smnMP1_FIRMWARE_FLAGS 0x3010024 40 41 static int 42 psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 43 { 44 switch (ucode->ucode_id) { 45 case AMDGPU_UCODE_ID_SDMA0: 46 *type = GFX_FW_TYPE_SDMA0; 47 break; 48 case AMDGPU_UCODE_ID_SDMA1: 49 *type = GFX_FW_TYPE_SDMA1; 50 break; 51 case AMDGPU_UCODE_ID_CP_CE: 52 *type = GFX_FW_TYPE_CP_CE; 53 break; 54 case AMDGPU_UCODE_ID_CP_PFP: 55 *type = GFX_FW_TYPE_CP_PFP; 56 break; 57 case AMDGPU_UCODE_ID_CP_ME: 58 *type = GFX_FW_TYPE_CP_ME; 59 break; 60 case AMDGPU_UCODE_ID_CP_MEC1: 61 *type = GFX_FW_TYPE_CP_MEC; 62 break; 63 case AMDGPU_UCODE_ID_CP_MEC1_JT: 64 *type = GFX_FW_TYPE_CP_MEC_ME1; 65 break; 66 case AMDGPU_UCODE_ID_CP_MEC2: 67 *type = GFX_FW_TYPE_CP_MEC; 68 break; 69 case AMDGPU_UCODE_ID_CP_MEC2_JT: 70 *type = GFX_FW_TYPE_CP_MEC_ME2; 71 break; 72 case AMDGPU_UCODE_ID_RLC_G: 73 *type = GFX_FW_TYPE_RLC_G; 74 break; 75 case AMDGPU_UCODE_ID_SMC: 76 *type = GFX_FW_TYPE_SMU; 77 break; 78 case AMDGPU_UCODE_ID_UVD: 79 *type = GFX_FW_TYPE_UVD; 80 break; 81 case AMDGPU_UCODE_ID_VCE: 82 *type = GFX_FW_TYPE_VCE; 83 break; 84 case AMDGPU_UCODE_ID_UVD1: 85 *type = GFX_FW_TYPE_UVD1; 86 break; 87 case AMDGPU_UCODE_ID_MAXIMUM: 88 default: 89 return -EINVAL; 90 } 91 92 return 0; 93 } 94 95 static int psp_v11_0_init_microcode(struct psp_context *psp) 96 { 97 struct amdgpu_device *adev = psp->adev; 98 const char *chip_name; 99 char fw_name[30]; 100 int err = 0; 101 const struct psp_firmware_header_v1_0 *hdr; 102 103 DRM_DEBUG("\n"); 104 105 switch (adev->asic_type) { 106 case CHIP_VEGA20: 107 chip_name = "vega20"; 108 break; 109 default: 110 BUG(); 111 } 112 113 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 114 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 115 if (err) 116 goto out; 117 118 err = amdgpu_ucode_validate(adev->psp.sos_fw); 119 if (err) 120 goto out; 121 122 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 123 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 124 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 125 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 126 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 127 le32_to_cpu(hdr->sos_size_bytes); 128 adev->psp.sys_start_addr = (uint8_t *)hdr + 129 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 130 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 131 le32_to_cpu(hdr->sos_offset_bytes); 132 return 0; 133 out: 134 if (err) { 135 dev_err(adev->dev, 136 "psp v11.0: Failed to load firmware \"%s\"\n", 137 fw_name); 138 release_firmware(adev->psp.sos_fw); 139 adev->psp.sos_fw = NULL; 140 } 141 142 return err; 143 } 144 145 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 146 { 147 int ret; 148 uint32_t psp_gfxdrv_command_reg = 0; 149 struct amdgpu_device *adev = psp->adev; 150 uint32_t sol_reg; 151 152 /* Check sOS sign of life register to confirm sys driver and sOS 153 * are already been loaded. 154 */ 155 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 156 if (sol_reg) 157 return 0; 158 159 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 160 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 161 0x80000000, 0x80000000, false); 162 if (ret) 163 return ret; 164 165 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 166 167 /* Copy PSP System Driver binary to memory */ 168 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 169 170 /* Provide the sys driver to bootrom */ 171 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 172 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 173 psp_gfxdrv_command_reg = 1 << 16; 174 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 175 psp_gfxdrv_command_reg); 176 177 /* there might be handshake issue with hardware which needs delay */ 178 mdelay(20); 179 180 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 181 0x80000000, 0x80000000, false); 182 183 return ret; 184 } 185 186 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 187 { 188 int ret; 189 unsigned int psp_gfxdrv_command_reg = 0; 190 struct amdgpu_device *adev = psp->adev; 191 uint32_t sol_reg; 192 193 /* Check sOS sign of life register to confirm sys driver and sOS 194 * are already been loaded. 195 */ 196 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 197 if (sol_reg) 198 return 0; 199 200 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 201 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 202 0x80000000, 0x80000000, false); 203 if (ret) 204 return ret; 205 206 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 207 208 /* Copy Secure OS binary to PSP memory */ 209 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 210 211 /* Provide the PSP secure OS to bootrom */ 212 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 213 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 214 psp_gfxdrv_command_reg = 2 << 16; 215 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 216 psp_gfxdrv_command_reg); 217 218 /* there might be handshake issue with hardware which needs delay */ 219 mdelay(20); 220 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 221 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 222 0, true); 223 224 return ret; 225 } 226 227 static int psp_v11_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, 228 struct psp_gfx_cmd_resp *cmd) 229 { 230 int ret; 231 uint64_t fw_mem_mc_addr = ucode->mc_addr; 232 233 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 234 235 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 236 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 237 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 238 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 239 240 ret = psp_v11_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 241 if (ret) 242 DRM_ERROR("Unknown firmware type\n"); 243 244 return ret; 245 } 246 247 static int psp_v11_0_ring_init(struct psp_context *psp, 248 enum psp_ring_type ring_type) 249 { 250 int ret = 0; 251 struct psp_ring *ring; 252 struct amdgpu_device *adev = psp->adev; 253 254 ring = &psp->km_ring; 255 256 ring->ring_type = ring_type; 257 258 /* allocate 4k Page of Local Frame Buffer memory for ring */ 259 ring->ring_size = 0x1000; 260 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 261 AMDGPU_GEM_DOMAIN_VRAM, 262 &adev->firmware.rbuf, 263 &ring->ring_mem_mc_addr, 264 (void **)&ring->ring_mem); 265 if (ret) { 266 ring->ring_size = 0; 267 return ret; 268 } 269 270 return 0; 271 } 272 273 static int psp_v11_0_ring_create(struct psp_context *psp, 274 enum psp_ring_type ring_type) 275 { 276 int ret = 0; 277 unsigned int psp_ring_reg = 0; 278 struct psp_ring *ring = &psp->km_ring; 279 struct amdgpu_device *adev = psp->adev; 280 281 /* Write low address of the ring to C2PMSG_69 */ 282 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 283 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 284 /* Write high address of the ring to C2PMSG_70 */ 285 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 286 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 287 /* Write size of ring to C2PMSG_71 */ 288 psp_ring_reg = ring->ring_size; 289 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 290 /* Write the ring initialization command to C2PMSG_64 */ 291 psp_ring_reg = ring_type; 292 psp_ring_reg = psp_ring_reg << 16; 293 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 294 295 /* there might be handshake issue with hardware which needs delay */ 296 mdelay(20); 297 298 /* Wait for response flag (bit 31) in C2PMSG_64 */ 299 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 300 0x80000000, 0x8000FFFF, false); 301 302 return ret; 303 } 304 305 static int psp_v11_0_ring_stop(struct psp_context *psp, 306 enum psp_ring_type ring_type) 307 { 308 int ret = 0; 309 struct psp_ring *ring; 310 struct amdgpu_device *adev = psp->adev; 311 312 ring = &psp->km_ring; 313 314 /* Write the ring destroy command to C2PMSG_64 */ 315 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_DESTROY_RINGS); 316 317 /* there might be handshake issue with hardware which needs delay */ 318 mdelay(20); 319 320 /* Wait for response flag (bit 31) in C2PMSG_64 */ 321 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 322 0x80000000, 0x80000000, false); 323 324 return ret; 325 } 326 327 static int psp_v11_0_ring_destroy(struct psp_context *psp, 328 enum psp_ring_type ring_type) 329 { 330 int ret = 0; 331 struct psp_ring *ring = &psp->km_ring; 332 struct amdgpu_device *adev = psp->adev; 333 334 ret = psp_v11_0_ring_stop(psp, ring_type); 335 if (ret) 336 DRM_ERROR("Fail to stop psp ring\n"); 337 338 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 339 &ring->ring_mem_mc_addr, 340 (void **)&ring->ring_mem); 341 342 return ret; 343 } 344 345 static int psp_v11_0_cmd_submit(struct psp_context *psp, 346 struct amdgpu_firmware_info *ucode, 347 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 348 int index) 349 { 350 unsigned int psp_write_ptr_reg = 0; 351 struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem; 352 struct psp_ring *ring = &psp->km_ring; 353 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 354 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 355 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 356 struct amdgpu_device *adev = psp->adev; 357 uint32_t ring_size_dw = ring->ring_size / 4; 358 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 359 360 /* KM (GPCOM) prepare write pointer */ 361 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 362 363 /* Update KM RB frame pointer to new frame */ 364 /* write_frame ptr increments by size of rb_frame in bytes */ 365 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 366 if ((psp_write_ptr_reg % ring_size_dw) == 0) 367 write_frame = ring_buffer_start; 368 else 369 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 370 /* Check invalid write_frame ptr address */ 371 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 372 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 373 ring_buffer_start, ring_buffer_end, write_frame); 374 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 375 return -EINVAL; 376 } 377 378 /* Initialize KM RB frame */ 379 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 380 381 /* Update KM RB frame */ 382 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 383 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 384 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 385 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 386 write_frame->fence_value = index; 387 388 /* Update the write Pointer in DWORDs */ 389 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 390 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 391 392 return 0; 393 } 394 395 static int 396 psp_v11_0_sram_map(struct amdgpu_device *adev, 397 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 398 unsigned int *sram_data_reg_offset, 399 enum AMDGPU_UCODE_ID ucode_id) 400 { 401 int ret = 0; 402 403 switch (ucode_id) { 404 /* TODO: needs to confirm */ 405 #if 0 406 case AMDGPU_UCODE_ID_SMC: 407 *sram_offset = 0; 408 *sram_addr_reg_offset = 0; 409 *sram_data_reg_offset = 0; 410 break; 411 #endif 412 413 case AMDGPU_UCODE_ID_CP_CE: 414 *sram_offset = 0x0; 415 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 416 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 417 break; 418 419 case AMDGPU_UCODE_ID_CP_PFP: 420 *sram_offset = 0x0; 421 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 422 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 423 break; 424 425 case AMDGPU_UCODE_ID_CP_ME: 426 *sram_offset = 0x0; 427 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 428 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 429 break; 430 431 case AMDGPU_UCODE_ID_CP_MEC1: 432 *sram_offset = 0x10000; 433 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 434 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 435 break; 436 437 case AMDGPU_UCODE_ID_CP_MEC2: 438 *sram_offset = 0x10000; 439 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 440 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 441 break; 442 443 case AMDGPU_UCODE_ID_RLC_G: 444 *sram_offset = 0x2000; 445 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 446 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 447 break; 448 449 case AMDGPU_UCODE_ID_SDMA0: 450 *sram_offset = 0x0; 451 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 452 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 453 break; 454 455 /* TODO: needs to confirm */ 456 #if 0 457 case AMDGPU_UCODE_ID_SDMA1: 458 *sram_offset = ; 459 *sram_addr_reg_offset = ; 460 break; 461 462 case AMDGPU_UCODE_ID_UVD: 463 *sram_offset = ; 464 *sram_addr_reg_offset = ; 465 break; 466 467 case AMDGPU_UCODE_ID_VCE: 468 *sram_offset = ; 469 *sram_addr_reg_offset = ; 470 break; 471 #endif 472 473 case AMDGPU_UCODE_ID_MAXIMUM: 474 default: 475 ret = -EINVAL; 476 break; 477 } 478 479 return ret; 480 } 481 482 static bool psp_v11_0_compare_sram_data(struct psp_context *psp, 483 struct amdgpu_firmware_info *ucode, 484 enum AMDGPU_UCODE_ID ucode_type) 485 { 486 int err = 0; 487 unsigned int fw_sram_reg_val = 0; 488 unsigned int fw_sram_addr_reg_offset = 0; 489 unsigned int fw_sram_data_reg_offset = 0; 490 unsigned int ucode_size; 491 uint32_t *ucode_mem = NULL; 492 struct amdgpu_device *adev = psp->adev; 493 494 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 495 &fw_sram_data_reg_offset, ucode_type); 496 if (err) 497 return false; 498 499 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 500 501 ucode_size = ucode->ucode_size; 502 ucode_mem = (uint32_t *)ucode->kaddr; 503 while (ucode_size) { 504 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 505 506 if (*ucode_mem != fw_sram_reg_val) 507 return false; 508 509 ucode_mem++; 510 /* 4 bytes */ 511 ucode_size -= 4; 512 } 513 514 return true; 515 } 516 517 static int psp_v11_0_mode1_reset(struct psp_context *psp) 518 { 519 int ret; 520 uint32_t offset; 521 struct amdgpu_device *adev = psp->adev; 522 523 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 524 525 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 526 527 if (ret) { 528 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 529 return -EINVAL; 530 } 531 532 /*send the mode 1 reset command*/ 533 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 534 535 mdelay(1000); 536 537 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 538 539 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 540 541 if (ret) { 542 DRM_INFO("psp mode 1 reset failed!\n"); 543 return -EINVAL; 544 } 545 546 DRM_INFO("psp mode1 reset succeed \n"); 547 548 return 0; 549 } 550 551 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready. 552 * For now, return success and hack the hive_id so high level code can 553 * start testing 554 */ 555 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp, 556 int number_devices, struct psp_xgmi_topology_info *topology) 557 { 558 return 0; 559 } 560 561 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp, 562 int number_devices, struct psp_xgmi_topology_info *topology) 563 { 564 return 0; 565 } 566 567 static u64 psp_v11_0_xgmi_get_hive_id(struct psp_context *psp) 568 { 569 u64 hive_id = 0; 570 571 /* Remove me when we can get correct hive_id through PSP */ 572 if (psp->adev->gmc.xgmi.num_physical_nodes) 573 hive_id = 0x123456789abcdef; 574 575 return hive_id; 576 } 577 578 static const struct psp_funcs psp_v11_0_funcs = { 579 .init_microcode = psp_v11_0_init_microcode, 580 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 581 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 582 .prep_cmd_buf = psp_v11_0_prep_cmd_buf, 583 .ring_init = psp_v11_0_ring_init, 584 .ring_create = psp_v11_0_ring_create, 585 .ring_stop = psp_v11_0_ring_stop, 586 .ring_destroy = psp_v11_0_ring_destroy, 587 .cmd_submit = psp_v11_0_cmd_submit, 588 .compare_sram_data = psp_v11_0_compare_sram_data, 589 .mode1_reset = psp_v11_0_mode1_reset, 590 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info, 591 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info, 592 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id, 593 }; 594 595 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 596 { 597 psp->funcs = &psp_v11_0_funcs; 598 } 599