1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "amdgpu_psp.h" 26 #include "amdgpu_ucode.h" 27 #include "soc15_common.h" 28 #include "psp_v11_0.h" 29 30 #include "mp/mp_11_0_offset.h" 31 #include "mp/mp_11_0_sh_mask.h" 32 #include "gc/gc_9_0_offset.h" 33 #include "sdma0/sdma0_4_0_offset.h" 34 #include "nbio/nbio_7_4_offset.h" 35 36 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 37 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 38 39 /* address block */ 40 #define smnMP1_FIRMWARE_FLAGS 0x3010024 41 42 static int 43 psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 44 { 45 switch (ucode->ucode_id) { 46 case AMDGPU_UCODE_ID_SDMA0: 47 *type = GFX_FW_TYPE_SDMA0; 48 break; 49 case AMDGPU_UCODE_ID_SDMA1: 50 *type = GFX_FW_TYPE_SDMA1; 51 break; 52 case AMDGPU_UCODE_ID_CP_CE: 53 *type = GFX_FW_TYPE_CP_CE; 54 break; 55 case AMDGPU_UCODE_ID_CP_PFP: 56 *type = GFX_FW_TYPE_CP_PFP; 57 break; 58 case AMDGPU_UCODE_ID_CP_ME: 59 *type = GFX_FW_TYPE_CP_ME; 60 break; 61 case AMDGPU_UCODE_ID_CP_MEC1: 62 *type = GFX_FW_TYPE_CP_MEC; 63 break; 64 case AMDGPU_UCODE_ID_CP_MEC1_JT: 65 *type = GFX_FW_TYPE_CP_MEC_ME1; 66 break; 67 case AMDGPU_UCODE_ID_CP_MEC2: 68 *type = GFX_FW_TYPE_CP_MEC; 69 break; 70 case AMDGPU_UCODE_ID_CP_MEC2_JT: 71 *type = GFX_FW_TYPE_CP_MEC_ME2; 72 break; 73 case AMDGPU_UCODE_ID_RLC_G: 74 *type = GFX_FW_TYPE_RLC_G; 75 break; 76 case AMDGPU_UCODE_ID_SMC: 77 *type = GFX_FW_TYPE_SMU; 78 break; 79 case AMDGPU_UCODE_ID_UVD: 80 *type = GFX_FW_TYPE_UVD; 81 break; 82 case AMDGPU_UCODE_ID_VCE: 83 *type = GFX_FW_TYPE_VCE; 84 break; 85 case AMDGPU_UCODE_ID_UVD1: 86 *type = GFX_FW_TYPE_UVD1; 87 break; 88 case AMDGPU_UCODE_ID_MAXIMUM: 89 default: 90 return -EINVAL; 91 } 92 93 return 0; 94 } 95 96 static int psp_v11_0_init_microcode(struct psp_context *psp) 97 { 98 struct amdgpu_device *adev = psp->adev; 99 const char *chip_name; 100 char fw_name[30]; 101 int err = 0; 102 const struct psp_firmware_header_v1_0 *sos_hdr; 103 const struct ta_firmware_header_v1_0 *ta_hdr; 104 105 DRM_DEBUG("\n"); 106 107 switch (adev->asic_type) { 108 case CHIP_VEGA20: 109 chip_name = "vega20"; 110 break; 111 default: 112 BUG(); 113 } 114 115 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 116 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 117 if (err) 118 goto out; 119 120 err = amdgpu_ucode_validate(adev->psp.sos_fw); 121 if (err) 122 goto out; 123 124 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 125 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 126 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 127 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 128 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->header.ucode_size_bytes) - 129 le32_to_cpu(sos_hdr->sos_size_bytes); 130 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 131 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 132 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 133 le32_to_cpu(sos_hdr->sos_offset_bytes); 134 135 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 136 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 137 if (err) 138 goto out; 139 140 err = amdgpu_ucode_validate(adev->psp.ta_fw); 141 if (err) 142 goto out; 143 144 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 145 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 146 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 147 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 148 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 149 150 return 0; 151 out: 152 if (err) { 153 dev_err(adev->dev, 154 "psp v11.0: Failed to load firmware \"%s\"\n", 155 fw_name); 156 release_firmware(adev->psp.sos_fw); 157 adev->psp.sos_fw = NULL; 158 } 159 160 return err; 161 } 162 163 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 164 { 165 int ret; 166 uint32_t psp_gfxdrv_command_reg = 0; 167 struct amdgpu_device *adev = psp->adev; 168 uint32_t sol_reg; 169 170 /* Check sOS sign of life register to confirm sys driver and sOS 171 * are already been loaded. 172 */ 173 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 174 if (sol_reg) 175 return 0; 176 177 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 178 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 179 0x80000000, 0x80000000, false); 180 if (ret) 181 return ret; 182 183 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 184 185 /* Copy PSP System Driver binary to memory */ 186 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 187 188 /* Provide the sys driver to bootloader */ 189 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 190 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 191 psp_gfxdrv_command_reg = 1 << 16; 192 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 193 psp_gfxdrv_command_reg); 194 195 /* there might be handshake issue with hardware which needs delay */ 196 mdelay(20); 197 198 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 199 0x80000000, 0x80000000, false); 200 201 return ret; 202 } 203 204 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 205 { 206 int ret; 207 unsigned int psp_gfxdrv_command_reg = 0; 208 struct amdgpu_device *adev = psp->adev; 209 uint32_t sol_reg; 210 211 /* Check sOS sign of life register to confirm sys driver and sOS 212 * are already been loaded. 213 */ 214 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 215 if (sol_reg) 216 return 0; 217 218 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 219 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 220 0x80000000, 0x80000000, false); 221 if (ret) 222 return ret; 223 224 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 225 226 /* Copy Secure OS binary to PSP memory */ 227 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 228 229 /* Provide the PSP secure OS to bootloader */ 230 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 231 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 232 psp_gfxdrv_command_reg = 2 << 16; 233 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 234 psp_gfxdrv_command_reg); 235 236 /* there might be handshake issue with hardware which needs delay */ 237 mdelay(20); 238 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 239 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 240 0, true); 241 242 return ret; 243 } 244 245 static int psp_v11_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, 246 struct psp_gfx_cmd_resp *cmd) 247 { 248 int ret; 249 uint64_t fw_mem_mc_addr = ucode->mc_addr; 250 251 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 252 253 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 254 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 255 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 256 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 257 258 ret = psp_v11_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 259 if (ret) 260 DRM_ERROR("Unknown firmware type\n"); 261 262 return ret; 263 } 264 265 static int psp_v11_0_ring_init(struct psp_context *psp, 266 enum psp_ring_type ring_type) 267 { 268 int ret = 0; 269 struct psp_ring *ring; 270 struct amdgpu_device *adev = psp->adev; 271 272 ring = &psp->km_ring; 273 274 ring->ring_type = ring_type; 275 276 /* allocate 4k Page of Local Frame Buffer memory for ring */ 277 ring->ring_size = 0x1000; 278 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 279 AMDGPU_GEM_DOMAIN_VRAM, 280 &adev->firmware.rbuf, 281 &ring->ring_mem_mc_addr, 282 (void **)&ring->ring_mem); 283 if (ret) { 284 ring->ring_size = 0; 285 return ret; 286 } 287 288 return 0; 289 } 290 291 static int psp_v11_0_ring_create(struct psp_context *psp, 292 enum psp_ring_type ring_type) 293 { 294 int ret = 0; 295 unsigned int psp_ring_reg = 0; 296 struct psp_ring *ring = &psp->km_ring; 297 struct amdgpu_device *adev = psp->adev; 298 299 /* Write low address of the ring to C2PMSG_69 */ 300 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 301 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 302 /* Write high address of the ring to C2PMSG_70 */ 303 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 304 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 305 /* Write size of ring to C2PMSG_71 */ 306 psp_ring_reg = ring->ring_size; 307 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 308 /* Write the ring initialization command to C2PMSG_64 */ 309 psp_ring_reg = ring_type; 310 psp_ring_reg = psp_ring_reg << 16; 311 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 312 313 /* there might be handshake issue with hardware which needs delay */ 314 mdelay(20); 315 316 /* Wait for response flag (bit 31) in C2PMSG_64 */ 317 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 318 0x80000000, 0x8000FFFF, false); 319 320 return ret; 321 } 322 323 static int psp_v11_0_ring_stop(struct psp_context *psp, 324 enum psp_ring_type ring_type) 325 { 326 int ret = 0; 327 struct amdgpu_device *adev = psp->adev; 328 329 /* Write the ring destroy command to C2PMSG_64 */ 330 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_DESTROY_RINGS); 331 332 /* there might be handshake issue with hardware which needs delay */ 333 mdelay(20); 334 335 /* Wait for response flag (bit 31) in C2PMSG_64 */ 336 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 337 0x80000000, 0x80000000, false); 338 339 return ret; 340 } 341 342 static int psp_v11_0_ring_destroy(struct psp_context *psp, 343 enum psp_ring_type ring_type) 344 { 345 int ret = 0; 346 struct psp_ring *ring = &psp->km_ring; 347 struct amdgpu_device *adev = psp->adev; 348 349 ret = psp_v11_0_ring_stop(psp, ring_type); 350 if (ret) 351 DRM_ERROR("Fail to stop psp ring\n"); 352 353 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 354 &ring->ring_mem_mc_addr, 355 (void **)&ring->ring_mem); 356 357 return ret; 358 } 359 360 static int psp_v11_0_cmd_submit(struct psp_context *psp, 361 struct amdgpu_firmware_info *ucode, 362 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 363 int index) 364 { 365 unsigned int psp_write_ptr_reg = 0; 366 struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem; 367 struct psp_ring *ring = &psp->km_ring; 368 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 369 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 370 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 371 struct amdgpu_device *adev = psp->adev; 372 uint32_t ring_size_dw = ring->ring_size / 4; 373 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 374 375 /* KM (GPCOM) prepare write pointer */ 376 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 377 378 /* Update KM RB frame pointer to new frame */ 379 /* write_frame ptr increments by size of rb_frame in bytes */ 380 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 381 if ((psp_write_ptr_reg % ring_size_dw) == 0) 382 write_frame = ring_buffer_start; 383 else 384 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 385 /* Check invalid write_frame ptr address */ 386 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 387 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 388 ring_buffer_start, ring_buffer_end, write_frame); 389 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 390 return -EINVAL; 391 } 392 393 /* Initialize KM RB frame */ 394 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 395 396 /* Update KM RB frame */ 397 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 398 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 399 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 400 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 401 write_frame->fence_value = index; 402 403 /* Update the write Pointer in DWORDs */ 404 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 405 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 406 407 return 0; 408 } 409 410 static int 411 psp_v11_0_sram_map(struct amdgpu_device *adev, 412 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 413 unsigned int *sram_data_reg_offset, 414 enum AMDGPU_UCODE_ID ucode_id) 415 { 416 int ret = 0; 417 418 switch (ucode_id) { 419 /* TODO: needs to confirm */ 420 #if 0 421 case AMDGPU_UCODE_ID_SMC: 422 *sram_offset = 0; 423 *sram_addr_reg_offset = 0; 424 *sram_data_reg_offset = 0; 425 break; 426 #endif 427 428 case AMDGPU_UCODE_ID_CP_CE: 429 *sram_offset = 0x0; 430 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 431 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 432 break; 433 434 case AMDGPU_UCODE_ID_CP_PFP: 435 *sram_offset = 0x0; 436 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 437 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 438 break; 439 440 case AMDGPU_UCODE_ID_CP_ME: 441 *sram_offset = 0x0; 442 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 443 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 444 break; 445 446 case AMDGPU_UCODE_ID_CP_MEC1: 447 *sram_offset = 0x10000; 448 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 449 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 450 break; 451 452 case AMDGPU_UCODE_ID_CP_MEC2: 453 *sram_offset = 0x10000; 454 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 455 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 456 break; 457 458 case AMDGPU_UCODE_ID_RLC_G: 459 *sram_offset = 0x2000; 460 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 461 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 462 break; 463 464 case AMDGPU_UCODE_ID_SDMA0: 465 *sram_offset = 0x0; 466 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 467 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 468 break; 469 470 /* TODO: needs to confirm */ 471 #if 0 472 case AMDGPU_UCODE_ID_SDMA1: 473 *sram_offset = ; 474 *sram_addr_reg_offset = ; 475 break; 476 477 case AMDGPU_UCODE_ID_UVD: 478 *sram_offset = ; 479 *sram_addr_reg_offset = ; 480 break; 481 482 case AMDGPU_UCODE_ID_VCE: 483 *sram_offset = ; 484 *sram_addr_reg_offset = ; 485 break; 486 #endif 487 488 case AMDGPU_UCODE_ID_MAXIMUM: 489 default: 490 ret = -EINVAL; 491 break; 492 } 493 494 return ret; 495 } 496 497 static bool psp_v11_0_compare_sram_data(struct psp_context *psp, 498 struct amdgpu_firmware_info *ucode, 499 enum AMDGPU_UCODE_ID ucode_type) 500 { 501 int err = 0; 502 unsigned int fw_sram_reg_val = 0; 503 unsigned int fw_sram_addr_reg_offset = 0; 504 unsigned int fw_sram_data_reg_offset = 0; 505 unsigned int ucode_size; 506 uint32_t *ucode_mem = NULL; 507 struct amdgpu_device *adev = psp->adev; 508 509 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 510 &fw_sram_data_reg_offset, ucode_type); 511 if (err) 512 return false; 513 514 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 515 516 ucode_size = ucode->ucode_size; 517 ucode_mem = (uint32_t *)ucode->kaddr; 518 while (ucode_size) { 519 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 520 521 if (*ucode_mem != fw_sram_reg_val) 522 return false; 523 524 ucode_mem++; 525 /* 4 bytes */ 526 ucode_size -= 4; 527 } 528 529 return true; 530 } 531 532 static int psp_v11_0_mode1_reset(struct psp_context *psp) 533 { 534 int ret; 535 uint32_t offset; 536 struct amdgpu_device *adev = psp->adev; 537 538 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 539 540 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 541 542 if (ret) { 543 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 544 return -EINVAL; 545 } 546 547 /*send the mode 1 reset command*/ 548 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 549 550 msleep(500); 551 552 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 553 554 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 555 556 if (ret) { 557 DRM_INFO("psp mode 1 reset failed!\n"); 558 return -EINVAL; 559 } 560 561 DRM_INFO("psp mode1 reset succeed \n"); 562 563 return 0; 564 } 565 566 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready. 567 * For now, return success and hack the hive_id so high level code can 568 * start testing 569 */ 570 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp, 571 int number_devices, struct psp_xgmi_topology_info *topology) 572 { 573 struct ta_xgmi_shared_memory *xgmi_cmd; 574 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 575 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 576 int i; 577 int ret; 578 579 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 580 return -EINVAL; 581 582 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 583 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 584 585 /* Fill in the shared memory with topology information as input */ 586 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 587 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 588 topology_info_input->num_nodes = number_devices; 589 590 for (i = 0; i < topology_info_input->num_nodes; i++) { 591 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 592 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 593 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 594 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 595 } 596 597 /* Invoke xgmi ta to get the topology information */ 598 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 599 if (ret) 600 return ret; 601 602 /* Read the output topology information from the shared memory */ 603 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 604 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 605 for (i = 0; i < topology->num_nodes; i++) { 606 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 607 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 608 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 609 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 610 } 611 612 return 0; 613 } 614 615 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp, 616 int number_devices, struct psp_xgmi_topology_info *topology) 617 { 618 struct ta_xgmi_shared_memory *xgmi_cmd; 619 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 620 int i; 621 622 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 623 return -EINVAL; 624 625 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 626 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 627 628 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 629 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 630 topology_info_input->num_nodes = number_devices; 631 632 for (i = 0; i < topology_info_input->num_nodes; i++) { 633 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 634 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 635 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 636 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 637 } 638 639 /* Invoke xgmi ta to set topology information */ 640 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 641 } 642 643 static u64 psp_v11_0_xgmi_get_hive_id(struct psp_context *psp) 644 { 645 struct ta_xgmi_shared_memory *xgmi_cmd; 646 int ret; 647 648 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 649 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 650 651 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 652 653 /* Invoke xgmi ta to get hive id */ 654 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 655 if (ret) 656 return 0; 657 else 658 return xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 659 } 660 661 static u64 psp_v11_0_xgmi_get_node_id(struct psp_context *psp) 662 { 663 struct ta_xgmi_shared_memory *xgmi_cmd; 664 int ret; 665 666 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 667 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 668 669 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 670 671 /* Invoke xgmi ta to get the node id */ 672 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 673 if (ret) 674 return 0; 675 else 676 return xgmi_cmd->xgmi_out_message.get_node_id.node_id; 677 } 678 679 static const struct psp_funcs psp_v11_0_funcs = { 680 .init_microcode = psp_v11_0_init_microcode, 681 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 682 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 683 .prep_cmd_buf = psp_v11_0_prep_cmd_buf, 684 .ring_init = psp_v11_0_ring_init, 685 .ring_create = psp_v11_0_ring_create, 686 .ring_stop = psp_v11_0_ring_stop, 687 .ring_destroy = psp_v11_0_ring_destroy, 688 .cmd_submit = psp_v11_0_cmd_submit, 689 .compare_sram_data = psp_v11_0_compare_sram_data, 690 .mode1_reset = psp_v11_0_mode1_reset, 691 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info, 692 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info, 693 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id, 694 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id, 695 }; 696 697 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 698 { 699 psp->funcs = &psp_v11_0_funcs; 700 } 701