1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "amdgpu_psp.h" 26 #include "amdgpu_ucode.h" 27 #include "soc15_common.h" 28 #include "psp_v11_0.h" 29 30 #include "mp/mp_11_0_offset.h" 31 #include "mp/mp_11_0_sh_mask.h" 32 #include "gc/gc_9_0_offset.h" 33 #include "sdma0/sdma0_4_0_offset.h" 34 #include "nbio/nbio_7_4_offset.h" 35 36 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 37 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 38 39 /* address block */ 40 #define smnMP1_FIRMWARE_FLAGS 0x3010024 41 42 static int 43 psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 44 { 45 switch (ucode->ucode_id) { 46 case AMDGPU_UCODE_ID_SDMA0: 47 *type = GFX_FW_TYPE_SDMA0; 48 break; 49 case AMDGPU_UCODE_ID_SDMA1: 50 *type = GFX_FW_TYPE_SDMA1; 51 break; 52 case AMDGPU_UCODE_ID_CP_CE: 53 *type = GFX_FW_TYPE_CP_CE; 54 break; 55 case AMDGPU_UCODE_ID_CP_PFP: 56 *type = GFX_FW_TYPE_CP_PFP; 57 break; 58 case AMDGPU_UCODE_ID_CP_ME: 59 *type = GFX_FW_TYPE_CP_ME; 60 break; 61 case AMDGPU_UCODE_ID_CP_MEC1: 62 *type = GFX_FW_TYPE_CP_MEC; 63 break; 64 case AMDGPU_UCODE_ID_CP_MEC1_JT: 65 *type = GFX_FW_TYPE_CP_MEC_ME1; 66 break; 67 case AMDGPU_UCODE_ID_CP_MEC2: 68 *type = GFX_FW_TYPE_CP_MEC; 69 break; 70 case AMDGPU_UCODE_ID_CP_MEC2_JT: 71 *type = GFX_FW_TYPE_CP_MEC_ME2; 72 break; 73 case AMDGPU_UCODE_ID_RLC_G: 74 *type = GFX_FW_TYPE_RLC_G; 75 break; 76 case AMDGPU_UCODE_ID_SMC: 77 *type = GFX_FW_TYPE_SMU; 78 break; 79 case AMDGPU_UCODE_ID_UVD: 80 *type = GFX_FW_TYPE_UVD; 81 break; 82 case AMDGPU_UCODE_ID_VCE: 83 *type = GFX_FW_TYPE_VCE; 84 break; 85 case AMDGPU_UCODE_ID_UVD1: 86 *type = GFX_FW_TYPE_UVD1; 87 break; 88 case AMDGPU_UCODE_ID_MAXIMUM: 89 default: 90 return -EINVAL; 91 } 92 93 return 0; 94 } 95 96 static int psp_v11_0_init_microcode(struct psp_context *psp) 97 { 98 struct amdgpu_device *adev = psp->adev; 99 const char *chip_name; 100 char fw_name[30]; 101 int err = 0; 102 const struct psp_firmware_header_v1_0 *sos_hdr; 103 const struct ta_firmware_header_v1_0 *ta_hdr; 104 105 DRM_DEBUG("\n"); 106 107 switch (adev->asic_type) { 108 case CHIP_VEGA20: 109 chip_name = "vega20"; 110 break; 111 default: 112 BUG(); 113 } 114 115 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 116 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 117 if (err) 118 goto out; 119 120 err = amdgpu_ucode_validate(adev->psp.sos_fw); 121 if (err) 122 goto out; 123 124 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 125 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 126 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 127 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 128 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->header.ucode_size_bytes) - 129 le32_to_cpu(sos_hdr->sos_size_bytes); 130 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 131 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 132 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 133 le32_to_cpu(sos_hdr->sos_offset_bytes); 134 135 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 136 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 137 if (err) 138 goto out; 139 140 err = amdgpu_ucode_validate(adev->psp.ta_fw); 141 if (err) 142 goto out; 143 144 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 145 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 146 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 147 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 148 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 149 150 return 0; 151 out: 152 if (err) { 153 dev_err(adev->dev, 154 "psp v11.0: Failed to load firmware \"%s\"\n", 155 fw_name); 156 release_firmware(adev->psp.sos_fw); 157 adev->psp.sos_fw = NULL; 158 } 159 160 return err; 161 } 162 163 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 164 { 165 int ret; 166 uint32_t psp_gfxdrv_command_reg = 0; 167 struct amdgpu_device *adev = psp->adev; 168 uint32_t sol_reg; 169 170 /* Check sOS sign of life register to confirm sys driver and sOS 171 * are already been loaded. 172 */ 173 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 174 if (sol_reg) { 175 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 176 printk("sos fw version = 0x%x.\n", psp->sos_fw_version); 177 return 0; 178 } 179 180 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 181 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 182 0x80000000, 0x80000000, false); 183 if (ret) 184 return ret; 185 186 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 187 188 /* Copy PSP System Driver binary to memory */ 189 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 190 191 /* Provide the sys driver to bootloader */ 192 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 193 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 194 psp_gfxdrv_command_reg = 1 << 16; 195 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 196 psp_gfxdrv_command_reg); 197 198 /* there might be handshake issue with hardware which needs delay */ 199 mdelay(20); 200 201 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 202 0x80000000, 0x80000000, false); 203 204 return ret; 205 } 206 207 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 208 { 209 int ret; 210 unsigned int psp_gfxdrv_command_reg = 0; 211 struct amdgpu_device *adev = psp->adev; 212 uint32_t sol_reg; 213 214 /* Check sOS sign of life register to confirm sys driver and sOS 215 * are already been loaded. 216 */ 217 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 218 if (sol_reg) 219 return 0; 220 221 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 222 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 223 0x80000000, 0x80000000, false); 224 if (ret) 225 return ret; 226 227 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 228 229 /* Copy Secure OS binary to PSP memory */ 230 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 231 232 /* Provide the PSP secure OS to bootloader */ 233 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 234 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 235 psp_gfxdrv_command_reg = 2 << 16; 236 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 237 psp_gfxdrv_command_reg); 238 239 /* there might be handshake issue with hardware which needs delay */ 240 mdelay(20); 241 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 242 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 243 0, true); 244 245 return ret; 246 } 247 248 static int psp_v11_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, 249 struct psp_gfx_cmd_resp *cmd) 250 { 251 int ret; 252 uint64_t fw_mem_mc_addr = ucode->mc_addr; 253 254 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 255 256 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 257 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 258 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 259 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 260 261 ret = psp_v11_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 262 if (ret) 263 DRM_ERROR("Unknown firmware type\n"); 264 265 return ret; 266 } 267 268 static int psp_v11_0_ring_init(struct psp_context *psp, 269 enum psp_ring_type ring_type) 270 { 271 int ret = 0; 272 struct psp_ring *ring; 273 struct amdgpu_device *adev = psp->adev; 274 275 ring = &psp->km_ring; 276 277 ring->ring_type = ring_type; 278 279 /* allocate 4k Page of Local Frame Buffer memory for ring */ 280 ring->ring_size = 0x1000; 281 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 282 AMDGPU_GEM_DOMAIN_VRAM, 283 &adev->firmware.rbuf, 284 &ring->ring_mem_mc_addr, 285 (void **)&ring->ring_mem); 286 if (ret) { 287 ring->ring_size = 0; 288 return ret; 289 } 290 291 return 0; 292 } 293 294 static int psp_v11_0_ring_create(struct psp_context *psp, 295 enum psp_ring_type ring_type) 296 { 297 int ret = 0; 298 unsigned int psp_ring_reg = 0; 299 struct psp_ring *ring = &psp->km_ring; 300 struct amdgpu_device *adev = psp->adev; 301 302 if (psp_support_vmr_ring(psp)) { 303 /* Write low address of the ring to C2PMSG_102 */ 304 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 305 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 306 /* Write high address of the ring to C2PMSG_103 */ 307 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 308 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 309 310 /* Write the ring initialization command to C2PMSG_101 */ 311 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 312 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 313 314 /* there might be handshake issue with hardware which needs delay */ 315 mdelay(20); 316 317 /* Wait for response flag (bit 31) in C2PMSG_101 */ 318 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 319 0x80000000, 0x8000FFFF, false); 320 321 } else { 322 /* Write low address of the ring to C2PMSG_69 */ 323 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 324 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 325 /* Write high address of the ring to C2PMSG_70 */ 326 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 327 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 328 /* Write size of ring to C2PMSG_71 */ 329 psp_ring_reg = ring->ring_size; 330 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 331 /* Write the ring initialization command to C2PMSG_64 */ 332 psp_ring_reg = ring_type; 333 psp_ring_reg = psp_ring_reg << 16; 334 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 335 336 /* there might be handshake issue with hardware which needs delay */ 337 mdelay(20); 338 339 /* Wait for response flag (bit 31) in C2PMSG_64 */ 340 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 341 0x80000000, 0x8000FFFF, false); 342 } 343 344 return ret; 345 } 346 347 static int psp_v11_0_ring_stop(struct psp_context *psp, 348 enum psp_ring_type ring_type) 349 { 350 int ret = 0; 351 struct amdgpu_device *adev = psp->adev; 352 353 /* Write the ring destroy command*/ 354 if (psp_support_vmr_ring(psp)) 355 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 356 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 357 else 358 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 359 GFX_CTRL_CMD_ID_DESTROY_RINGS); 360 361 /* there might be handshake issue with hardware which needs delay */ 362 mdelay(20); 363 364 /* Wait for response flag (bit 31) */ 365 if (psp_support_vmr_ring(psp)) 366 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 367 0x80000000, 0x80000000, false); 368 else 369 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 370 0x80000000, 0x80000000, false); 371 372 return ret; 373 } 374 375 static int psp_v11_0_ring_destroy(struct psp_context *psp, 376 enum psp_ring_type ring_type) 377 { 378 int ret = 0; 379 struct psp_ring *ring = &psp->km_ring; 380 struct amdgpu_device *adev = psp->adev; 381 382 ret = psp_v11_0_ring_stop(psp, ring_type); 383 if (ret) 384 DRM_ERROR("Fail to stop psp ring\n"); 385 386 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 387 &ring->ring_mem_mc_addr, 388 (void **)&ring->ring_mem); 389 390 return ret; 391 } 392 393 static int psp_v11_0_cmd_submit(struct psp_context *psp, 394 struct amdgpu_firmware_info *ucode, 395 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 396 int index) 397 { 398 unsigned int psp_write_ptr_reg = 0; 399 struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem; 400 struct psp_ring *ring = &psp->km_ring; 401 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 402 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 403 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 404 struct amdgpu_device *adev = psp->adev; 405 uint32_t ring_size_dw = ring->ring_size / 4; 406 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 407 408 /* KM (GPCOM) prepare write pointer */ 409 if (psp_support_vmr_ring(psp)) 410 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 411 else 412 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 413 414 /* Update KM RB frame pointer to new frame */ 415 /* write_frame ptr increments by size of rb_frame in bytes */ 416 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 417 if ((psp_write_ptr_reg % ring_size_dw) == 0) 418 write_frame = ring_buffer_start; 419 else 420 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 421 /* Check invalid write_frame ptr address */ 422 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 423 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 424 ring_buffer_start, ring_buffer_end, write_frame); 425 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 426 return -EINVAL; 427 } 428 429 /* Initialize KM RB frame */ 430 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 431 432 /* Update KM RB frame */ 433 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 434 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 435 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 436 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 437 write_frame->fence_value = index; 438 439 /* Update the write Pointer in DWORDs */ 440 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 441 if (psp_support_vmr_ring(psp)) { 442 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg); 443 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 444 } else 445 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 446 447 return 0; 448 } 449 450 static int 451 psp_v11_0_sram_map(struct amdgpu_device *adev, 452 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 453 unsigned int *sram_data_reg_offset, 454 enum AMDGPU_UCODE_ID ucode_id) 455 { 456 int ret = 0; 457 458 switch (ucode_id) { 459 /* TODO: needs to confirm */ 460 #if 0 461 case AMDGPU_UCODE_ID_SMC: 462 *sram_offset = 0; 463 *sram_addr_reg_offset = 0; 464 *sram_data_reg_offset = 0; 465 break; 466 #endif 467 468 case AMDGPU_UCODE_ID_CP_CE: 469 *sram_offset = 0x0; 470 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 471 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 472 break; 473 474 case AMDGPU_UCODE_ID_CP_PFP: 475 *sram_offset = 0x0; 476 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 477 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 478 break; 479 480 case AMDGPU_UCODE_ID_CP_ME: 481 *sram_offset = 0x0; 482 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 483 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 484 break; 485 486 case AMDGPU_UCODE_ID_CP_MEC1: 487 *sram_offset = 0x10000; 488 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 489 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 490 break; 491 492 case AMDGPU_UCODE_ID_CP_MEC2: 493 *sram_offset = 0x10000; 494 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 495 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 496 break; 497 498 case AMDGPU_UCODE_ID_RLC_G: 499 *sram_offset = 0x2000; 500 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 501 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 502 break; 503 504 case AMDGPU_UCODE_ID_SDMA0: 505 *sram_offset = 0x0; 506 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 507 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 508 break; 509 510 /* TODO: needs to confirm */ 511 #if 0 512 case AMDGPU_UCODE_ID_SDMA1: 513 *sram_offset = ; 514 *sram_addr_reg_offset = ; 515 break; 516 517 case AMDGPU_UCODE_ID_UVD: 518 *sram_offset = ; 519 *sram_addr_reg_offset = ; 520 break; 521 522 case AMDGPU_UCODE_ID_VCE: 523 *sram_offset = ; 524 *sram_addr_reg_offset = ; 525 break; 526 #endif 527 528 case AMDGPU_UCODE_ID_MAXIMUM: 529 default: 530 ret = -EINVAL; 531 break; 532 } 533 534 return ret; 535 } 536 537 static bool psp_v11_0_compare_sram_data(struct psp_context *psp, 538 struct amdgpu_firmware_info *ucode, 539 enum AMDGPU_UCODE_ID ucode_type) 540 { 541 int err = 0; 542 unsigned int fw_sram_reg_val = 0; 543 unsigned int fw_sram_addr_reg_offset = 0; 544 unsigned int fw_sram_data_reg_offset = 0; 545 unsigned int ucode_size; 546 uint32_t *ucode_mem = NULL; 547 struct amdgpu_device *adev = psp->adev; 548 549 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 550 &fw_sram_data_reg_offset, ucode_type); 551 if (err) 552 return false; 553 554 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 555 556 ucode_size = ucode->ucode_size; 557 ucode_mem = (uint32_t *)ucode->kaddr; 558 while (ucode_size) { 559 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 560 561 if (*ucode_mem != fw_sram_reg_val) 562 return false; 563 564 ucode_mem++; 565 /* 4 bytes */ 566 ucode_size -= 4; 567 } 568 569 return true; 570 } 571 572 static int psp_v11_0_mode1_reset(struct psp_context *psp) 573 { 574 int ret; 575 uint32_t offset; 576 struct amdgpu_device *adev = psp->adev; 577 578 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 579 580 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 581 582 if (ret) { 583 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 584 return -EINVAL; 585 } 586 587 /*send the mode 1 reset command*/ 588 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 589 590 msleep(500); 591 592 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 593 594 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 595 596 if (ret) { 597 DRM_INFO("psp mode 1 reset failed!\n"); 598 return -EINVAL; 599 } 600 601 DRM_INFO("psp mode1 reset succeed \n"); 602 603 return 0; 604 } 605 606 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready. 607 * For now, return success and hack the hive_id so high level code can 608 * start testing 609 */ 610 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp, 611 int number_devices, struct psp_xgmi_topology_info *topology) 612 { 613 struct ta_xgmi_shared_memory *xgmi_cmd; 614 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 615 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 616 int i; 617 int ret; 618 619 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 620 return -EINVAL; 621 622 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 623 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 624 625 /* Fill in the shared memory with topology information as input */ 626 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 627 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 628 topology_info_input->num_nodes = number_devices; 629 630 for (i = 0; i < topology_info_input->num_nodes; i++) { 631 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 632 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 633 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 634 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 635 } 636 637 /* Invoke xgmi ta to get the topology information */ 638 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 639 if (ret) 640 return ret; 641 642 /* Read the output topology information from the shared memory */ 643 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 644 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 645 for (i = 0; i < topology->num_nodes; i++) { 646 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 647 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 648 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 649 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 650 } 651 652 return 0; 653 } 654 655 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp, 656 int number_devices, struct psp_xgmi_topology_info *topology) 657 { 658 struct ta_xgmi_shared_memory *xgmi_cmd; 659 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 660 int i; 661 662 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 663 return -EINVAL; 664 665 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 666 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 667 668 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 669 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 670 topology_info_input->num_nodes = number_devices; 671 672 for (i = 0; i < topology_info_input->num_nodes; i++) { 673 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 674 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 675 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 676 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 677 } 678 679 /* Invoke xgmi ta to set topology information */ 680 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 681 } 682 683 static u64 psp_v11_0_xgmi_get_hive_id(struct psp_context *psp) 684 { 685 struct ta_xgmi_shared_memory *xgmi_cmd; 686 int ret; 687 688 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 689 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 690 691 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 692 693 /* Invoke xgmi ta to get hive id */ 694 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 695 if (ret) 696 return 0; 697 else 698 return xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 699 } 700 701 static u64 psp_v11_0_xgmi_get_node_id(struct psp_context *psp) 702 { 703 struct ta_xgmi_shared_memory *xgmi_cmd; 704 int ret; 705 706 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 707 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 708 709 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 710 711 /* Invoke xgmi ta to get the node id */ 712 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 713 if (ret) 714 return 0; 715 else 716 return xgmi_cmd->xgmi_out_message.get_node_id.node_id; 717 } 718 719 static const struct psp_funcs psp_v11_0_funcs = { 720 .init_microcode = psp_v11_0_init_microcode, 721 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 722 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 723 .prep_cmd_buf = psp_v11_0_prep_cmd_buf, 724 .ring_init = psp_v11_0_ring_init, 725 .ring_create = psp_v11_0_ring_create, 726 .ring_stop = psp_v11_0_ring_stop, 727 .ring_destroy = psp_v11_0_ring_destroy, 728 .cmd_submit = psp_v11_0_cmd_submit, 729 .compare_sram_data = psp_v11_0_compare_sram_data, 730 .mode1_reset = psp_v11_0_mode1_reset, 731 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info, 732 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info, 733 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id, 734 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id, 735 }; 736 737 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 738 { 739 psp->funcs = &psp_v11_0_funcs; 740 } 741