1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include <linux/firmware.h>
24 #include "amdgpu.h"
25 #include "amdgpu_psp.h"
26 #include "amdgpu_ucode.h"
27 #include "soc15_common.h"
28 #include "psp_v11_0.h"
29 
30 #include "mp/mp_11_0_offset.h"
31 #include "mp/mp_11_0_sh_mask.h"
32 #include "gc/gc_9_0_offset.h"
33 #include "sdma0/sdma0_4_0_offset.h"
34 #include "nbio/nbio_7_4_offset.h"
35 
36 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
37 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
38 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
39 
40 /* address block */
41 #define smnMP1_FIRMWARE_FLAGS		0x3010024
42 
43 static int psp_v11_0_init_microcode(struct psp_context *psp)
44 {
45 	struct amdgpu_device *adev = psp->adev;
46 	const char *chip_name;
47 	char fw_name[30];
48 	int err = 0;
49 	const struct psp_firmware_header_v1_0 *sos_hdr;
50 	const struct psp_firmware_header_v1_0 *asd_hdr;
51 	const struct ta_firmware_header_v1_0 *ta_hdr;
52 
53 	DRM_DEBUG("\n");
54 
55 	switch (adev->asic_type) {
56 	case CHIP_VEGA20:
57 		chip_name = "vega20";
58 		break;
59 	default:
60 		BUG();
61 	}
62 
63 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
64 	err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
65 	if (err)
66 		goto out;
67 
68 	err = amdgpu_ucode_validate(adev->psp.sos_fw);
69 	if (err)
70 		goto out;
71 
72 	sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
73 	adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
74 	adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
75 	adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
76 	adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->header.ucode_size_bytes) -
77 					le32_to_cpu(sos_hdr->sos_size_bytes);
78 	adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
79 				le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
80 	adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
81 				le32_to_cpu(sos_hdr->sos_offset_bytes);
82 
83 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
84 	err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
85 	if (err)
86 		goto out1;
87 
88 	err = amdgpu_ucode_validate(adev->psp.asd_fw);
89 	if (err)
90 		goto out1;
91 
92 	asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
93 	adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
94 	adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
95 	adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
96 	adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
97 				le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
98 
99 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
100 	err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
101 	if (err) {
102 		release_firmware(adev->psp.ta_fw);
103 		adev->psp.ta_fw = NULL;
104 		dev_info(adev->dev,
105 			 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
106 	} else {
107 		err = amdgpu_ucode_validate(adev->psp.ta_fw);
108 		if (err)
109 			goto out2;
110 
111 		ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data;
112 		adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version);
113 		adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
114 		adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
115 			le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
116 	}
117 
118 	return 0;
119 
120 out2:
121 	release_firmware(adev->psp.ta_fw);
122 	adev->psp.ta_fw = NULL;
123 out1:
124 	release_firmware(adev->psp.asd_fw);
125 	adev->psp.asd_fw = NULL;
126 out:
127 	dev_err(adev->dev,
128 		"psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
129 	release_firmware(adev->psp.sos_fw);
130 	adev->psp.sos_fw = NULL;
131 
132 	return err;
133 }
134 
135 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
136 {
137 	int ret;
138 	uint32_t psp_gfxdrv_command_reg = 0;
139 	struct amdgpu_device *adev = psp->adev;
140 	uint32_t sol_reg;
141 
142 	/* Check sOS sign of life register to confirm sys driver and sOS
143 	 * are already been loaded.
144 	 */
145 	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
146 	if (sol_reg) {
147 		psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
148 		printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
149 		return 0;
150 	}
151 
152 	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
153 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
154 			   0x80000000, 0x80000000, false);
155 	if (ret)
156 		return ret;
157 
158 	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
159 
160 	/* Copy PSP System Driver binary to memory */
161 	memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
162 
163 	/* Provide the sys driver to bootloader */
164 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
165 	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
166 	psp_gfxdrv_command_reg = 1 << 16;
167 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
168 	       psp_gfxdrv_command_reg);
169 
170 	/* there might be handshake issue with hardware which needs delay */
171 	mdelay(20);
172 
173 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
174 			   0x80000000, 0x80000000, false);
175 
176 	return ret;
177 }
178 
179 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
180 {
181 	int ret;
182 	unsigned int psp_gfxdrv_command_reg = 0;
183 	struct amdgpu_device *adev = psp->adev;
184 	uint32_t sol_reg;
185 
186 	/* Check sOS sign of life register to confirm sys driver and sOS
187 	 * are already been loaded.
188 	 */
189 	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
190 	if (sol_reg)
191 		return 0;
192 
193 	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
194 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
195 			   0x80000000, 0x80000000, false);
196 	if (ret)
197 		return ret;
198 
199 	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
200 
201 	/* Copy Secure OS binary to PSP memory */
202 	memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
203 
204 	/* Provide the PSP secure OS to bootloader */
205 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
206 	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
207 	psp_gfxdrv_command_reg = 2 << 16;
208 	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
209 	       psp_gfxdrv_command_reg);
210 
211 	/* there might be handshake issue with hardware which needs delay */
212 	mdelay(20);
213 	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
214 			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
215 			   0, true);
216 
217 	return ret;
218 }
219 
220 static int psp_v11_0_ring_init(struct psp_context *psp,
221 			      enum psp_ring_type ring_type)
222 {
223 	int ret = 0;
224 	struct psp_ring *ring;
225 	struct amdgpu_device *adev = psp->adev;
226 
227 	ring = &psp->km_ring;
228 
229 	ring->ring_type = ring_type;
230 
231 	/* allocate 4k Page of Local Frame Buffer memory for ring */
232 	ring->ring_size = 0x1000;
233 	ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
234 				      AMDGPU_GEM_DOMAIN_VRAM,
235 				      &adev->firmware.rbuf,
236 				      &ring->ring_mem_mc_addr,
237 				      (void **)&ring->ring_mem);
238 	if (ret) {
239 		ring->ring_size = 0;
240 		return ret;
241 	}
242 
243 	return 0;
244 }
245 
246 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
247 {
248 	if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
249 		return true;
250 	return false;
251 }
252 
253 static int psp_v11_0_ring_create(struct psp_context *psp,
254 				enum psp_ring_type ring_type)
255 {
256 	int ret = 0;
257 	unsigned int psp_ring_reg = 0;
258 	struct psp_ring *ring = &psp->km_ring;
259 	struct amdgpu_device *adev = psp->adev;
260 
261 	if (psp_v11_0_support_vmr_ring(psp)) {
262 		/* Write low address of the ring to C2PMSG_102 */
263 		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
264 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
265 		/* Write high address of the ring to C2PMSG_103 */
266 		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
267 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
268 
269 		/* Write the ring initialization command to C2PMSG_101 */
270 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
271 					     GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
272 
273 		/* there might be handshake issue with hardware which needs delay */
274 		mdelay(20);
275 
276 		/* Wait for response flag (bit 31) in C2PMSG_101 */
277 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
278 				   0x80000000, 0x8000FFFF, false);
279 
280 	} else {
281 		/* Write low address of the ring to C2PMSG_69 */
282 		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
283 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
284 		/* Write high address of the ring to C2PMSG_70 */
285 		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
286 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
287 		/* Write size of ring to C2PMSG_71 */
288 		psp_ring_reg = ring->ring_size;
289 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
290 		/* Write the ring initialization command to C2PMSG_64 */
291 		psp_ring_reg = ring_type;
292 		psp_ring_reg = psp_ring_reg << 16;
293 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
294 
295 		/* there might be handshake issue with hardware which needs delay */
296 		mdelay(20);
297 
298 		/* Wait for response flag (bit 31) in C2PMSG_64 */
299 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
300 				   0x80000000, 0x8000FFFF, false);
301 	}
302 
303 	return ret;
304 }
305 
306 static int psp_v11_0_ring_stop(struct psp_context *psp,
307 			      enum psp_ring_type ring_type)
308 {
309 	int ret = 0;
310 	struct amdgpu_device *adev = psp->adev;
311 
312 	/* Write the ring destroy command*/
313 	if (psp_v11_0_support_vmr_ring(psp))
314 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
315 				     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
316 	else
317 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
318 				     GFX_CTRL_CMD_ID_DESTROY_RINGS);
319 
320 	/* there might be handshake issue with hardware which needs delay */
321 	mdelay(20);
322 
323 	/* Wait for response flag (bit 31) */
324 	if (psp_v11_0_support_vmr_ring(psp))
325 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
326 				   0x80000000, 0x80000000, false);
327 	else
328 		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
329 				   0x80000000, 0x80000000, false);
330 
331 	return ret;
332 }
333 
334 static int psp_v11_0_ring_destroy(struct psp_context *psp,
335 				 enum psp_ring_type ring_type)
336 {
337 	int ret = 0;
338 	struct psp_ring *ring = &psp->km_ring;
339 	struct amdgpu_device *adev = psp->adev;
340 
341 	ret = psp_v11_0_ring_stop(psp, ring_type);
342 	if (ret)
343 		DRM_ERROR("Fail to stop psp ring\n");
344 
345 	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
346 			      &ring->ring_mem_mc_addr,
347 			      (void **)&ring->ring_mem);
348 
349 	return ret;
350 }
351 
352 static int psp_v11_0_cmd_submit(struct psp_context *psp,
353 			       struct amdgpu_firmware_info *ucode,
354 			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
355 			       int index)
356 {
357 	unsigned int psp_write_ptr_reg = 0;
358 	struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
359 	struct psp_ring *ring = &psp->km_ring;
360 	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
361 	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
362 		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
363 	struct amdgpu_device *adev = psp->adev;
364 	uint32_t ring_size_dw = ring->ring_size / 4;
365 	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
366 
367 	/* KM (GPCOM) prepare write pointer */
368 	if (psp_v11_0_support_vmr_ring(psp))
369 		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
370 	else
371 		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
372 
373 	/* Update KM RB frame pointer to new frame */
374 	/* write_frame ptr increments by size of rb_frame in bytes */
375 	/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
376 	if ((psp_write_ptr_reg % ring_size_dw) == 0)
377 		write_frame = ring_buffer_start;
378 	else
379 		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
380 	/* Check invalid write_frame ptr address */
381 	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
382 		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
383 			  ring_buffer_start, ring_buffer_end, write_frame);
384 		DRM_ERROR("write_frame is pointing to address out of bounds\n");
385 		return -EINVAL;
386 	}
387 
388 	/* Initialize KM RB frame */
389 	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
390 
391 	/* Update KM RB frame */
392 	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
393 	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
394 	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
395 	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
396 	write_frame->fence_value = index;
397 
398 	/* Update the write Pointer in DWORDs */
399 	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
400 	if (psp_v11_0_support_vmr_ring(psp)) {
401 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
402 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
403 	} else
404 		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
405 
406 	return 0;
407 }
408 
409 static int
410 psp_v11_0_sram_map(struct amdgpu_device *adev,
411 		  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
412 		  unsigned int *sram_data_reg_offset,
413 		  enum AMDGPU_UCODE_ID ucode_id)
414 {
415 	int ret = 0;
416 
417 	switch (ucode_id) {
418 /* TODO: needs to confirm */
419 #if 0
420 	case AMDGPU_UCODE_ID_SMC:
421 		*sram_offset = 0;
422 		*sram_addr_reg_offset = 0;
423 		*sram_data_reg_offset = 0;
424 		break;
425 #endif
426 
427 	case AMDGPU_UCODE_ID_CP_CE:
428 		*sram_offset = 0x0;
429 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
430 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
431 		break;
432 
433 	case AMDGPU_UCODE_ID_CP_PFP:
434 		*sram_offset = 0x0;
435 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
436 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
437 		break;
438 
439 	case AMDGPU_UCODE_ID_CP_ME:
440 		*sram_offset = 0x0;
441 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
442 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
443 		break;
444 
445 	case AMDGPU_UCODE_ID_CP_MEC1:
446 		*sram_offset = 0x10000;
447 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
448 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
449 		break;
450 
451 	case AMDGPU_UCODE_ID_CP_MEC2:
452 		*sram_offset = 0x10000;
453 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
454 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
455 		break;
456 
457 	case AMDGPU_UCODE_ID_RLC_G:
458 		*sram_offset = 0x2000;
459 		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
460 		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
461 		break;
462 
463 	case AMDGPU_UCODE_ID_SDMA0:
464 		*sram_offset = 0x0;
465 		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
466 		*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
467 		break;
468 
469 /* TODO: needs to confirm */
470 #if 0
471 	case AMDGPU_UCODE_ID_SDMA1:
472 		*sram_offset = ;
473 		*sram_addr_reg_offset = ;
474 		break;
475 
476 	case AMDGPU_UCODE_ID_UVD:
477 		*sram_offset = ;
478 		*sram_addr_reg_offset = ;
479 		break;
480 
481 	case AMDGPU_UCODE_ID_VCE:
482 		*sram_offset = ;
483 		*sram_addr_reg_offset = ;
484 		break;
485 #endif
486 
487 	case AMDGPU_UCODE_ID_MAXIMUM:
488 	default:
489 		ret = -EINVAL;
490 		break;
491 	}
492 
493 	return ret;
494 }
495 
496 static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
497 				       struct amdgpu_firmware_info *ucode,
498 				       enum AMDGPU_UCODE_ID ucode_type)
499 {
500 	int err = 0;
501 	unsigned int fw_sram_reg_val = 0;
502 	unsigned int fw_sram_addr_reg_offset = 0;
503 	unsigned int fw_sram_data_reg_offset = 0;
504 	unsigned int ucode_size;
505 	uint32_t *ucode_mem = NULL;
506 	struct amdgpu_device *adev = psp->adev;
507 
508 	err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
509 				&fw_sram_data_reg_offset, ucode_type);
510 	if (err)
511 		return false;
512 
513 	WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
514 
515 	ucode_size = ucode->ucode_size;
516 	ucode_mem = (uint32_t *)ucode->kaddr;
517 	while (ucode_size) {
518 		fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
519 
520 		if (*ucode_mem != fw_sram_reg_val)
521 			return false;
522 
523 		ucode_mem++;
524 		/* 4 bytes */
525 		ucode_size -= 4;
526 	}
527 
528 	return true;
529 }
530 
531 static int psp_v11_0_mode1_reset(struct psp_context *psp)
532 {
533 	int ret;
534 	uint32_t offset;
535 	struct amdgpu_device *adev = psp->adev;
536 
537 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
538 
539 	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
540 
541 	if (ret) {
542 		DRM_INFO("psp is not working correctly before mode1 reset!\n");
543 		return -EINVAL;
544 	}
545 
546 	/*send the mode 1 reset command*/
547 	WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
548 
549 	msleep(500);
550 
551 	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
552 
553 	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
554 
555 	if (ret) {
556 		DRM_INFO("psp mode 1 reset failed!\n");
557 		return -EINVAL;
558 	}
559 
560 	DRM_INFO("psp mode1 reset succeed \n");
561 
562 	return 0;
563 }
564 
565 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
566  * For now, return success and hack the hive_id so high level code can
567  * start testing
568  */
569 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp,
570 	int number_devices, struct psp_xgmi_topology_info *topology)
571 {
572 	struct ta_xgmi_shared_memory *xgmi_cmd;
573 	struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
574 	struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
575 	int i;
576 	int ret;
577 
578 	if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
579 		return -EINVAL;
580 
581 	xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
582 	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
583 
584 	/* Fill in the shared memory with topology information as input */
585 	topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
586 	xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
587 	topology_info_input->num_nodes = number_devices;
588 
589 	for (i = 0; i < topology_info_input->num_nodes; i++) {
590 		topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
591 		topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
592 		topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
593 		topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
594 	}
595 
596 	/* Invoke xgmi ta to get the topology information */
597 	ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
598 	if (ret)
599 		return ret;
600 
601 	/* Read the output topology information from the shared memory */
602 	topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
603 	topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
604 	for (i = 0; i < topology->num_nodes; i++) {
605 		topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
606 		topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
607 		topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
608 		topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
609 	}
610 
611 	return 0;
612 }
613 
614 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp,
615 	int number_devices, struct psp_xgmi_topology_info *topology)
616 {
617 	struct ta_xgmi_shared_memory *xgmi_cmd;
618 	struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
619 	int i;
620 
621 	if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
622 		return -EINVAL;
623 
624 	xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
625 	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
626 
627 	topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
628 	xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
629 	topology_info_input->num_nodes = number_devices;
630 
631 	for (i = 0; i < topology_info_input->num_nodes; i++) {
632 		topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
633 		topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
634 		topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
635 		topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
636 	}
637 
638 	/* Invoke xgmi ta to set topology information */
639 	return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
640 }
641 
642 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
643 {
644 	struct ta_xgmi_shared_memory *xgmi_cmd;
645 	int ret;
646 
647 	xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
648 	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
649 
650 	xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
651 
652 	/* Invoke xgmi ta to get hive id */
653 	ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
654 	if (ret)
655 		return ret;
656 
657 	*hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
658 
659 	return 0;
660 }
661 
662 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
663 {
664 	struct ta_xgmi_shared_memory *xgmi_cmd;
665 	int ret;
666 
667 	xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
668 	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
669 
670 	xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
671 
672 	/* Invoke xgmi ta to get the node id */
673 	ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
674 	if (ret)
675 		return ret;
676 
677 	*node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
678 
679 	return 0;
680 }
681 
682 static const struct psp_funcs psp_v11_0_funcs = {
683 	.init_microcode = psp_v11_0_init_microcode,
684 	.bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
685 	.bootloader_load_sos = psp_v11_0_bootloader_load_sos,
686 	.ring_init = psp_v11_0_ring_init,
687 	.ring_create = psp_v11_0_ring_create,
688 	.ring_stop = psp_v11_0_ring_stop,
689 	.ring_destroy = psp_v11_0_ring_destroy,
690 	.cmd_submit = psp_v11_0_cmd_submit,
691 	.compare_sram_data = psp_v11_0_compare_sram_data,
692 	.mode1_reset = psp_v11_0_mode1_reset,
693 	.xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
694 	.xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
695 	.xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
696 	.xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
697 	.support_vmr_ring = psp_v11_0_support_vmr_ring,
698 };
699 
700 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
701 {
702 	psp->funcs = &psp_v11_0_funcs;
703 }
704