1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_psp.h" 28 #include "amdgpu_ucode.h" 29 #include "soc15_common.h" 30 #include "psp_v11_0.h" 31 32 #include "mp/mp_11_0_offset.h" 33 #include "mp/mp_11_0_sh_mask.h" 34 #include "gc/gc_9_0_offset.h" 35 #include "sdma0/sdma0_4_0_offset.h" 36 #include "nbio/nbio_7_4_offset.h" 37 38 #include "oss/osssys_4_0_offset.h" 39 #include "oss/osssys_4_0_sh_mask.h" 40 41 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 42 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 43 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 46 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 48 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 49 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 50 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 51 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 52 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 53 54 /* address block */ 55 #define smnMP1_FIRMWARE_FLAGS 0x3010024 56 /* navi10 reg offset define */ 57 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 58 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 59 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 60 #define mmSDMA0_UCODE_DATA_NV10 0x5881 61 /* memory training timeout define */ 62 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 63 64 static int psp_v11_0_init_microcode(struct psp_context *psp) 65 { 66 struct amdgpu_device *adev = psp->adev; 67 const char *chip_name; 68 char fw_name[30]; 69 int err = 0; 70 const struct psp_firmware_header_v1_0 *sos_hdr; 71 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 72 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 73 const struct psp_firmware_header_v1_0 *asd_hdr; 74 const struct ta_firmware_header_v1_0 *ta_hdr; 75 76 DRM_DEBUG("\n"); 77 78 switch (adev->asic_type) { 79 case CHIP_VEGA20: 80 chip_name = "vega20"; 81 break; 82 case CHIP_NAVI10: 83 chip_name = "navi10"; 84 break; 85 case CHIP_NAVI14: 86 chip_name = "navi14"; 87 break; 88 case CHIP_NAVI12: 89 chip_name = "navi12"; 90 break; 91 case CHIP_ARCTURUS: 92 chip_name = "arcturus"; 93 break; 94 default: 95 BUG(); 96 } 97 98 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 99 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 100 if (err) 101 goto out; 102 103 err = amdgpu_ucode_validate(adev->psp.sos_fw); 104 if (err) 105 goto out; 106 107 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 108 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 109 110 switch (sos_hdr->header.header_version_major) { 111 case 1: 112 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 113 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 114 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 115 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 116 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 117 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 118 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 119 le32_to_cpu(sos_hdr->sos_offset_bytes); 120 if (sos_hdr->header.header_version_minor == 1) { 121 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 122 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 123 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 124 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 125 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 126 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 127 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 128 } 129 if (sos_hdr->header.header_version_minor == 2) { 130 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 131 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 132 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 133 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 134 } 135 break; 136 default: 137 dev_err(adev->dev, 138 "Unsupported psp sos firmware\n"); 139 err = -EINVAL; 140 goto out; 141 } 142 143 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 144 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 145 if (err) 146 goto out1; 147 148 err = amdgpu_ucode_validate(adev->psp.asd_fw); 149 if (err) 150 goto out1; 151 152 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 153 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 154 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 155 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 156 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 157 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 158 159 switch (adev->asic_type) { 160 case CHIP_VEGA20: 161 case CHIP_ARCTURUS: 162 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 163 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 164 if (err) { 165 release_firmware(adev->psp.ta_fw); 166 adev->psp.ta_fw = NULL; 167 dev_info(adev->dev, 168 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 169 } else { 170 err = amdgpu_ucode_validate(adev->psp.ta_fw); 171 if (err) 172 goto out2; 173 174 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 175 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 176 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 177 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 178 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 179 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 180 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); 181 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); 182 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + 183 le32_to_cpu(ta_hdr->ta_ras_offset_bytes); 184 } 185 break; 186 case CHIP_NAVI10: 187 case CHIP_NAVI14: 188 case CHIP_NAVI12: 189 break; 190 default: 191 BUG(); 192 } 193 194 return 0; 195 196 out2: 197 release_firmware(adev->psp.ta_fw); 198 adev->psp.ta_fw = NULL; 199 out1: 200 release_firmware(adev->psp.asd_fw); 201 adev->psp.asd_fw = NULL; 202 out: 203 dev_err(adev->dev, 204 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 205 release_firmware(adev->psp.sos_fw); 206 adev->psp.sos_fw = NULL; 207 208 return err; 209 } 210 211 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 212 { 213 struct amdgpu_device *adev = psp->adev; 214 uint32_t sol_reg; 215 216 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 217 218 return sol_reg != 0x0; 219 } 220 221 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 222 { 223 int ret; 224 uint32_t psp_gfxdrv_command_reg = 0; 225 struct amdgpu_device *adev = psp->adev; 226 227 /* Check tOS sign of life register to confirm sys driver and sOS 228 * are already been loaded. 229 */ 230 if (psp_v11_0_is_sos_alive(psp)) { 231 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 232 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version); 233 return 0; 234 } 235 236 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 237 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 238 0x80000000, 0x80000000, false); 239 if (ret) 240 return ret; 241 242 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 243 244 /* Copy PSP KDB binary to memory */ 245 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); 246 247 /* Provide the PSP KDB to bootloader */ 248 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 249 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 250 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; 251 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 252 psp_gfxdrv_command_reg); 253 254 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1*/ 255 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 256 0x80000000, 0x80000000, false); 257 258 return ret; 259 } 260 261 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 262 { 263 int ret; 264 uint32_t psp_gfxdrv_command_reg = 0; 265 struct amdgpu_device *adev = psp->adev; 266 267 /* Check sOS sign of life register to confirm sys driver and sOS 268 * are already been loaded. 269 */ 270 if (psp_v11_0_is_sos_alive(psp)) { 271 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 272 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version); 273 return 0; 274 } 275 276 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 277 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 278 0x80000000, 0x80000000, false); 279 if (ret) 280 return ret; 281 282 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 283 284 /* Copy PSP System Driver binary to memory */ 285 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 286 287 /* Provide the sys driver to bootloader */ 288 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 289 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 290 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 291 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 292 psp_gfxdrv_command_reg); 293 294 /* there might be handshake issue with hardware which needs delay */ 295 mdelay(20); 296 297 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 298 0x80000000, 0x80000000, false); 299 300 return ret; 301 } 302 303 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 304 { 305 int ret; 306 unsigned int psp_gfxdrv_command_reg = 0; 307 struct amdgpu_device *adev = psp->adev; 308 309 /* Check sOS sign of life register to confirm sys driver and sOS 310 * are already been loaded. 311 */ 312 if (psp_v11_0_is_sos_alive(psp)) 313 return 0; 314 315 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 316 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 317 0x80000000, 0x80000000, false); 318 if (ret) 319 return ret; 320 321 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 322 323 /* Copy Secure OS binary to PSP memory */ 324 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 325 326 /* Provide the PSP secure OS to bootloader */ 327 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 328 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 329 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 330 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 331 psp_gfxdrv_command_reg); 332 333 /* there might be handshake issue with hardware which needs delay */ 334 mdelay(20); 335 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 336 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 337 0, true); 338 339 return ret; 340 } 341 342 static void psp_v11_0_reroute_ih(struct psp_context *psp) 343 { 344 struct amdgpu_device *adev = psp->adev; 345 uint32_t tmp; 346 347 /* Change IH ring for VMC */ 348 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 349 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 350 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 351 352 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 353 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 354 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 355 356 mdelay(20); 357 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 358 0x80000000, 0x8000FFFF, false); 359 360 /* Change IH ring for UMC */ 361 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 362 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 363 364 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 365 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 366 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 367 368 mdelay(20); 369 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 370 0x80000000, 0x8000FFFF, false); 371 } 372 373 static int psp_v11_0_ring_init(struct psp_context *psp, 374 enum psp_ring_type ring_type) 375 { 376 int ret = 0; 377 struct psp_ring *ring; 378 struct amdgpu_device *adev = psp->adev; 379 380 psp_v11_0_reroute_ih(psp); 381 382 ring = &psp->km_ring; 383 384 ring->ring_type = ring_type; 385 386 /* allocate 4k Page of Local Frame Buffer memory for ring */ 387 ring->ring_size = 0x1000; 388 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 389 AMDGPU_GEM_DOMAIN_VRAM, 390 &adev->firmware.rbuf, 391 &ring->ring_mem_mc_addr, 392 (void **)&ring->ring_mem); 393 if (ret) { 394 ring->ring_size = 0; 395 return ret; 396 } 397 398 return 0; 399 } 400 401 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp) 402 { 403 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045) 404 return true; 405 return false; 406 } 407 408 static int psp_v11_0_ring_stop(struct psp_context *psp, 409 enum psp_ring_type ring_type) 410 { 411 int ret = 0; 412 struct amdgpu_device *adev = psp->adev; 413 414 /* Write the ring destroy command*/ 415 if (psp_v11_0_support_vmr_ring(psp)) 416 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 417 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 418 else 419 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 420 GFX_CTRL_CMD_ID_DESTROY_RINGS); 421 422 /* there might be handshake issue with hardware which needs delay */ 423 mdelay(20); 424 425 /* Wait for response flag (bit 31) */ 426 if (psp_v11_0_support_vmr_ring(psp)) 427 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 428 0x80000000, 0x80000000, false); 429 else 430 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 431 0x80000000, 0x80000000, false); 432 433 return ret; 434 } 435 436 static int psp_v11_0_ring_create(struct psp_context *psp, 437 enum psp_ring_type ring_type) 438 { 439 int ret = 0; 440 unsigned int psp_ring_reg = 0; 441 struct psp_ring *ring = &psp->km_ring; 442 struct amdgpu_device *adev = psp->adev; 443 444 if (psp_v11_0_support_vmr_ring(psp)) { 445 ret = psp_v11_0_ring_stop(psp, ring_type); 446 if (ret) { 447 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 448 return ret; 449 } 450 451 /* Write low address of the ring to C2PMSG_102 */ 452 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 453 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 454 /* Write high address of the ring to C2PMSG_103 */ 455 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 456 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 457 458 /* Write the ring initialization command to C2PMSG_101 */ 459 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 460 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 461 462 /* there might be handshake issue with hardware which needs delay */ 463 mdelay(20); 464 465 /* Wait for response flag (bit 31) in C2PMSG_101 */ 466 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 467 0x80000000, 0x8000FFFF, false); 468 469 } else { 470 /* Wait for sOS ready for ring creation */ 471 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 472 0x80000000, 0x80000000, false); 473 if (ret) { 474 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 475 return ret; 476 } 477 478 /* Write low address of the ring to C2PMSG_69 */ 479 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 480 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 481 /* Write high address of the ring to C2PMSG_70 */ 482 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 483 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 484 /* Write size of ring to C2PMSG_71 */ 485 psp_ring_reg = ring->ring_size; 486 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 487 /* Write the ring initialization command to C2PMSG_64 */ 488 psp_ring_reg = ring_type; 489 psp_ring_reg = psp_ring_reg << 16; 490 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 491 492 /* there might be handshake issue with hardware which needs delay */ 493 mdelay(20); 494 495 /* Wait for response flag (bit 31) in C2PMSG_64 */ 496 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 497 0x80000000, 0x8000FFFF, false); 498 } 499 500 return ret; 501 } 502 503 504 static int psp_v11_0_ring_destroy(struct psp_context *psp, 505 enum psp_ring_type ring_type) 506 { 507 int ret = 0; 508 struct psp_ring *ring = &psp->km_ring; 509 struct amdgpu_device *adev = psp->adev; 510 511 ret = psp_v11_0_ring_stop(psp, ring_type); 512 if (ret) 513 DRM_ERROR("Fail to stop psp ring\n"); 514 515 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 516 &ring->ring_mem_mc_addr, 517 (void **)&ring->ring_mem); 518 519 return ret; 520 } 521 522 static int 523 psp_v11_0_sram_map(struct amdgpu_device *adev, 524 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 525 unsigned int *sram_data_reg_offset, 526 enum AMDGPU_UCODE_ID ucode_id) 527 { 528 int ret = 0; 529 530 switch (ucode_id) { 531 /* TODO: needs to confirm */ 532 #if 0 533 case AMDGPU_UCODE_ID_SMC: 534 *sram_offset = 0; 535 *sram_addr_reg_offset = 0; 536 *sram_data_reg_offset = 0; 537 break; 538 #endif 539 540 case AMDGPU_UCODE_ID_CP_CE: 541 *sram_offset = 0x0; 542 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 543 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 544 break; 545 546 case AMDGPU_UCODE_ID_CP_PFP: 547 *sram_offset = 0x0; 548 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 549 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 550 break; 551 552 case AMDGPU_UCODE_ID_CP_ME: 553 *sram_offset = 0x0; 554 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 555 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 556 break; 557 558 case AMDGPU_UCODE_ID_CP_MEC1: 559 *sram_offset = 0x10000; 560 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 561 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 562 break; 563 564 case AMDGPU_UCODE_ID_CP_MEC2: 565 *sram_offset = 0x10000; 566 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 567 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 568 break; 569 570 case AMDGPU_UCODE_ID_RLC_G: 571 *sram_offset = 0x2000; 572 if (adev->asic_type < CHIP_NAVI10) { 573 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 574 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 575 } else { 576 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10; 577 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10; 578 } 579 break; 580 581 case AMDGPU_UCODE_ID_SDMA0: 582 *sram_offset = 0x0; 583 if (adev->asic_type < CHIP_NAVI10) { 584 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 585 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 586 } else { 587 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10; 588 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10; 589 } 590 break; 591 592 /* TODO: needs to confirm */ 593 #if 0 594 case AMDGPU_UCODE_ID_SDMA1: 595 *sram_offset = ; 596 *sram_addr_reg_offset = ; 597 break; 598 599 case AMDGPU_UCODE_ID_UVD: 600 *sram_offset = ; 601 *sram_addr_reg_offset = ; 602 break; 603 604 case AMDGPU_UCODE_ID_VCE: 605 *sram_offset = ; 606 *sram_addr_reg_offset = ; 607 break; 608 #endif 609 610 case AMDGPU_UCODE_ID_MAXIMUM: 611 default: 612 ret = -EINVAL; 613 break; 614 } 615 616 return ret; 617 } 618 619 static bool psp_v11_0_compare_sram_data(struct psp_context *psp, 620 struct amdgpu_firmware_info *ucode, 621 enum AMDGPU_UCODE_ID ucode_type) 622 { 623 int err = 0; 624 unsigned int fw_sram_reg_val = 0; 625 unsigned int fw_sram_addr_reg_offset = 0; 626 unsigned int fw_sram_data_reg_offset = 0; 627 unsigned int ucode_size; 628 uint32_t *ucode_mem = NULL; 629 struct amdgpu_device *adev = psp->adev; 630 631 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 632 &fw_sram_data_reg_offset, ucode_type); 633 if (err) 634 return false; 635 636 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 637 638 ucode_size = ucode->ucode_size; 639 ucode_mem = (uint32_t *)ucode->kaddr; 640 while (ucode_size) { 641 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 642 643 if (*ucode_mem != fw_sram_reg_val) 644 return false; 645 646 ucode_mem++; 647 /* 4 bytes */ 648 ucode_size -= 4; 649 } 650 651 return true; 652 } 653 654 static int psp_v11_0_mode1_reset(struct psp_context *psp) 655 { 656 int ret; 657 uint32_t offset; 658 struct amdgpu_device *adev = psp->adev; 659 660 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 661 662 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 663 664 if (ret) { 665 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 666 return -EINVAL; 667 } 668 669 /*send the mode 1 reset command*/ 670 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 671 672 msleep(500); 673 674 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 675 676 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 677 678 if (ret) { 679 DRM_INFO("psp mode 1 reset failed!\n"); 680 return -EINVAL; 681 } 682 683 DRM_INFO("psp mode1 reset succeed \n"); 684 685 return 0; 686 } 687 688 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready. 689 * For now, return success and hack the hive_id so high level code can 690 * start testing 691 */ 692 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp, 693 int number_devices, struct psp_xgmi_topology_info *topology) 694 { 695 struct ta_xgmi_shared_memory *xgmi_cmd; 696 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 697 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 698 int i; 699 int ret; 700 701 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 702 return -EINVAL; 703 704 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 705 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 706 707 /* Fill in the shared memory with topology information as input */ 708 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 709 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 710 topology_info_input->num_nodes = number_devices; 711 712 for (i = 0; i < topology_info_input->num_nodes; i++) { 713 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 714 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 715 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 716 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 717 } 718 719 /* Invoke xgmi ta to get the topology information */ 720 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 721 if (ret) 722 return ret; 723 724 /* Read the output topology information from the shared memory */ 725 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 726 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 727 for (i = 0; i < topology->num_nodes; i++) { 728 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 729 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 730 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 731 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 732 } 733 734 return 0; 735 } 736 737 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp, 738 int number_devices, struct psp_xgmi_topology_info *topology) 739 { 740 struct ta_xgmi_shared_memory *xgmi_cmd; 741 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 742 int i; 743 744 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 745 return -EINVAL; 746 747 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 748 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 749 750 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 751 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 752 topology_info_input->num_nodes = number_devices; 753 754 for (i = 0; i < topology_info_input->num_nodes; i++) { 755 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 756 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 757 topology_info_input->nodes[i].is_sharing_enabled = 1; 758 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 759 } 760 761 /* Invoke xgmi ta to set topology information */ 762 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 763 } 764 765 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 766 { 767 struct ta_xgmi_shared_memory *xgmi_cmd; 768 int ret; 769 770 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 771 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 772 773 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 774 775 /* Invoke xgmi ta to get hive id */ 776 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 777 if (ret) 778 return ret; 779 780 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 781 782 return 0; 783 } 784 785 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 786 { 787 struct ta_xgmi_shared_memory *xgmi_cmd; 788 int ret; 789 790 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 791 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 792 793 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 794 795 /* Invoke xgmi ta to get the node id */ 796 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 797 if (ret) 798 return ret; 799 800 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 801 802 return 0; 803 } 804 805 static int psp_v11_0_ras_trigger_error(struct psp_context *psp, 806 struct ta_ras_trigger_error_input *info) 807 { 808 struct ta_ras_shared_memory *ras_cmd; 809 int ret; 810 811 if (!psp->ras.ras_initialized) 812 return -EINVAL; 813 814 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 815 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 816 817 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 818 ras_cmd->ras_in_message.trigger_error = *info; 819 820 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 821 if (ret) 822 return -EINVAL; 823 824 return ras_cmd->ras_status; 825 } 826 827 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr) 828 { 829 #if 0 830 // not support yet. 831 struct ta_ras_shared_memory *ras_cmd; 832 int ret; 833 834 if (!psp->ras.ras_initialized) 835 return -EINVAL; 836 837 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 838 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 839 840 ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON; 841 ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr; 842 843 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 844 if (ret) 845 return -EINVAL; 846 847 return ras_cmd->ras_status; 848 #else 849 return -EINVAL; 850 #endif 851 } 852 853 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp) 854 { 855 return psp_rlc_autoload_start(psp); 856 } 857 858 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 859 { 860 int ret; 861 int i; 862 uint32_t data_32; 863 int max_wait; 864 struct amdgpu_device *adev = psp->adev; 865 866 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 867 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 868 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 869 870 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 871 for (i = 0; i < max_wait; i++) { 872 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 873 0x80000000, 0x80000000, false); 874 if (ret == 0) 875 break; 876 } 877 if (i < max_wait) 878 ret = 0; 879 else 880 ret = -ETIME; 881 882 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 883 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 884 (ret == 0) ? "succeed" : "failed", 885 i, adev->usec_timeout/1000); 886 return ret; 887 } 888 889 static void psp_v11_0_memory_training_fini(struct psp_context *psp) 890 { 891 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 892 893 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 894 kfree(ctx->sys_cache); 895 ctx->sys_cache = NULL; 896 } 897 898 static int psp_v11_0_memory_training_init(struct psp_context *psp) 899 { 900 int ret; 901 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 902 903 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 904 DRM_DEBUG("memory training is not supported!\n"); 905 return 0; 906 } 907 908 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 909 if (ctx->sys_cache == NULL) { 910 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 911 ret = -ENOMEM; 912 goto Err_out; 913 } 914 915 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 916 ctx->train_data_size, 917 ctx->p2c_train_data_offset, 918 ctx->c2p_train_data_offset); 919 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 920 return 0; 921 922 Err_out: 923 psp_v11_0_memory_training_fini(psp); 924 return ret; 925 } 926 927 /* 928 * save and restore proces 929 */ 930 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 931 { 932 int ret; 933 uint32_t p2c_header[4]; 934 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 935 uint32_t *pcache = (uint32_t*)ctx->sys_cache; 936 937 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 938 DRM_DEBUG("Memory training is not supported.\n"); 939 return 0; 940 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 941 DRM_ERROR("Memory training initialization failure.\n"); 942 return -EINVAL; 943 } 944 945 if (psp_v11_0_is_sos_alive(psp)) { 946 DRM_DEBUG("SOS is alive, skip memory training.\n"); 947 return 0; 948 } 949 950 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 951 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 952 pcache[0], pcache[1], pcache[2], pcache[3], 953 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 954 955 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 956 DRM_DEBUG("Short training depends on restore.\n"); 957 ops |= PSP_MEM_TRAIN_RESTORE; 958 } 959 960 if ((ops & PSP_MEM_TRAIN_RESTORE) && 961 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 962 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 963 ops |= PSP_MEM_TRAIN_SAVE; 964 } 965 966 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 967 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 968 pcache[3] == p2c_header[3])) { 969 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 970 ops |= PSP_MEM_TRAIN_SAVE; 971 } 972 973 if ((ops & PSP_MEM_TRAIN_SAVE) && 974 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 975 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 976 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 977 } 978 979 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 980 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 981 ops |= PSP_MEM_TRAIN_SAVE; 982 } 983 984 DRM_DEBUG("Memory training ops:%x.\n", ops); 985 986 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 987 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 988 if (ret) { 989 DRM_ERROR("Send long training msg failed.\n"); 990 return ret; 991 } 992 } 993 994 if (ops & PSP_MEM_TRAIN_SAVE) { 995 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 996 } 997 998 if (ops & PSP_MEM_TRAIN_RESTORE) { 999 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 1000 } 1001 1002 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 1003 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 1004 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 1005 if (ret) { 1006 DRM_ERROR("send training msg failed.\n"); 1007 return ret; 1008 } 1009 } 1010 ctx->training_cnt++; 1011 return 0; 1012 } 1013 1014 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 1015 { 1016 uint32_t data; 1017 struct amdgpu_device *adev = psp->adev; 1018 1019 if (psp_v11_0_support_vmr_ring(psp)) 1020 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 1021 else 1022 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 1023 1024 return data; 1025 } 1026 1027 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 1028 { 1029 struct amdgpu_device *adev = psp->adev; 1030 1031 if (psp_v11_0_support_vmr_ring(psp)) { 1032 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 1033 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 1034 } else 1035 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 1036 } 1037 1038 static const struct psp_funcs psp_v11_0_funcs = { 1039 .init_microcode = psp_v11_0_init_microcode, 1040 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 1041 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 1042 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 1043 .ring_init = psp_v11_0_ring_init, 1044 .ring_create = psp_v11_0_ring_create, 1045 .ring_stop = psp_v11_0_ring_stop, 1046 .ring_destroy = psp_v11_0_ring_destroy, 1047 .compare_sram_data = psp_v11_0_compare_sram_data, 1048 .mode1_reset = psp_v11_0_mode1_reset, 1049 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info, 1050 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info, 1051 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id, 1052 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id, 1053 .support_vmr_ring = psp_v11_0_support_vmr_ring, 1054 .ras_trigger_error = psp_v11_0_ras_trigger_error, 1055 .ras_cure_posion = psp_v11_0_ras_cure_posion, 1056 .rlc_autoload_start = psp_v11_0_rlc_autoload_start, 1057 .mem_training_init = psp_v11_0_memory_training_init, 1058 .mem_training_fini = psp_v11_0_memory_training_fini, 1059 .mem_training = psp_v11_0_memory_training, 1060 .ring_get_wptr = psp_v11_0_ring_get_wptr, 1061 .ring_set_wptr = psp_v11_0_ring_set_wptr, 1062 }; 1063 1064 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 1065 { 1066 psp->funcs = &psp_v11_0_funcs; 1067 } 1068