1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_psp.h" 28 #include "amdgpu_ucode.h" 29 #include "soc15_common.h" 30 #include "psp_v11_0.h" 31 32 #include "mp/mp_11_0_offset.h" 33 #include "mp/mp_11_0_sh_mask.h" 34 #include "gc/gc_9_0_offset.h" 35 #include "sdma0/sdma0_4_0_offset.h" 36 #include "nbio/nbio_7_4_offset.h" 37 38 #include "oss/osssys_4_0_offset.h" 39 #include "oss/osssys_4_0_sh_mask.h" 40 41 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 42 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 43 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 46 47 /* address block */ 48 #define smnMP1_FIRMWARE_FLAGS 0x3010024 49 /* navi10 reg offset define */ 50 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 51 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 52 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 53 #define mmSDMA0_UCODE_DATA_NV10 0x5881 54 55 static int psp_v11_0_init_microcode(struct psp_context *psp) 56 { 57 struct amdgpu_device *adev = psp->adev; 58 const char *chip_name; 59 char fw_name[30]; 60 int err = 0; 61 const struct psp_firmware_header_v1_0 *sos_hdr; 62 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 63 const struct psp_firmware_header_v1_0 *asd_hdr; 64 const struct ta_firmware_header_v1_0 *ta_hdr; 65 66 DRM_DEBUG("\n"); 67 68 switch (adev->asic_type) { 69 case CHIP_VEGA20: 70 chip_name = "vega20"; 71 break; 72 case CHIP_NAVI10: 73 chip_name = "navi10"; 74 break; 75 default: 76 BUG(); 77 } 78 79 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 80 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 81 if (err) 82 goto out; 83 84 err = amdgpu_ucode_validate(adev->psp.sos_fw); 85 if (err) 86 goto out; 87 88 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 89 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 90 91 switch (sos_hdr->header.header_version_major) { 92 case 1: 93 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 94 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 95 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 96 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 97 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 98 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 99 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 100 le32_to_cpu(sos_hdr->sos_offset_bytes); 101 if (sos_hdr->header.header_version_minor == 1) { 102 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 103 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 104 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 105 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 106 } 107 break; 108 default: 109 dev_err(adev->dev, 110 "Unsupported psp sos firmware\n"); 111 err = -EINVAL; 112 goto out; 113 } 114 115 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 116 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 117 if (err) 118 goto out1; 119 120 err = amdgpu_ucode_validate(adev->psp.asd_fw); 121 if (err) 122 goto out1; 123 124 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 125 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 126 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 127 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 128 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 129 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 130 131 switch (adev->asic_type) { 132 case CHIP_VEGA20: 133 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 134 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 135 if (err) { 136 release_firmware(adev->psp.ta_fw); 137 adev->psp.ta_fw = NULL; 138 dev_info(adev->dev, 139 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 140 } else { 141 err = amdgpu_ucode_validate(adev->psp.ta_fw); 142 if (err) 143 goto out2; 144 145 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 146 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 147 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 148 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 149 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 150 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 151 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); 152 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); 153 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + 154 le32_to_cpu(ta_hdr->ta_ras_offset_bytes); 155 } 156 break; 157 case CHIP_NAVI10: 158 break; 159 default: 160 BUG(); 161 } 162 163 return 0; 164 165 out2: 166 release_firmware(adev->psp.ta_fw); 167 adev->psp.ta_fw = NULL; 168 out1: 169 release_firmware(adev->psp.asd_fw); 170 adev->psp.asd_fw = NULL; 171 out: 172 dev_err(adev->dev, 173 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 174 release_firmware(adev->psp.sos_fw); 175 adev->psp.sos_fw = NULL; 176 177 return err; 178 } 179 180 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 181 { 182 int ret; 183 uint32_t psp_gfxdrv_command_reg = 0; 184 struct amdgpu_device *adev = psp->adev; 185 uint32_t sol_reg; 186 187 /* Check sOS sign of life register to confirm sys driver and sOS 188 * are already been loaded. 189 */ 190 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 191 if (sol_reg) { 192 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 193 printk("sos fw version = 0x%x.\n", psp->sos_fw_version); 194 return 0; 195 } 196 197 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 198 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 199 0x80000000, 0x80000000, false); 200 if (ret) 201 return ret; 202 203 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 204 205 /* Copy PSP System Driver binary to memory */ 206 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 207 208 /* Provide the sys driver to bootloader */ 209 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 210 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 211 psp_gfxdrv_command_reg = 1 << 16; 212 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 213 psp_gfxdrv_command_reg); 214 215 /* there might be handshake issue with hardware which needs delay */ 216 mdelay(20); 217 218 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 219 0x80000000, 0x80000000, false); 220 221 return ret; 222 } 223 224 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 225 { 226 int ret; 227 unsigned int psp_gfxdrv_command_reg = 0; 228 struct amdgpu_device *adev = psp->adev; 229 uint32_t sol_reg; 230 231 /* Check sOS sign of life register to confirm sys driver and sOS 232 * are already been loaded. 233 */ 234 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 235 if (sol_reg) 236 return 0; 237 238 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 239 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 240 0x80000000, 0x80000000, false); 241 if (ret) 242 return ret; 243 244 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 245 246 /* Copy Secure OS binary to PSP memory */ 247 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 248 249 /* Provide the PSP secure OS to bootloader */ 250 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 251 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 252 psp_gfxdrv_command_reg = 2 << 16; 253 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 254 psp_gfxdrv_command_reg); 255 256 /* there might be handshake issue with hardware which needs delay */ 257 mdelay(20); 258 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 259 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 260 0, true); 261 262 return ret; 263 } 264 265 static void psp_v11_0_reroute_ih(struct psp_context *psp) 266 { 267 struct amdgpu_device *adev = psp->adev; 268 uint32_t tmp; 269 270 /* Change IH ring for VMC */ 271 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 272 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 273 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 274 275 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 276 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 277 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 278 279 mdelay(20); 280 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 281 0x80000000, 0x8000FFFF, false); 282 283 /* Change IH ring for UMC */ 284 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 285 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 286 287 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 288 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 289 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 290 291 mdelay(20); 292 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 293 0x80000000, 0x8000FFFF, false); 294 } 295 296 static int psp_v11_0_ring_init(struct psp_context *psp, 297 enum psp_ring_type ring_type) 298 { 299 int ret = 0; 300 struct psp_ring *ring; 301 struct amdgpu_device *adev = psp->adev; 302 303 psp_v11_0_reroute_ih(psp); 304 305 ring = &psp->km_ring; 306 307 ring->ring_type = ring_type; 308 309 /* allocate 4k Page of Local Frame Buffer memory for ring */ 310 ring->ring_size = 0x1000; 311 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 312 AMDGPU_GEM_DOMAIN_VRAM, 313 &adev->firmware.rbuf, 314 &ring->ring_mem_mc_addr, 315 (void **)&ring->ring_mem); 316 if (ret) { 317 ring->ring_size = 0; 318 return ret; 319 } 320 321 return 0; 322 } 323 324 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp) 325 { 326 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045) 327 return true; 328 return false; 329 } 330 331 static int psp_v11_0_ring_create(struct psp_context *psp, 332 enum psp_ring_type ring_type) 333 { 334 int ret = 0; 335 unsigned int psp_ring_reg = 0; 336 struct psp_ring *ring = &psp->km_ring; 337 struct amdgpu_device *adev = psp->adev; 338 339 if (psp_v11_0_support_vmr_ring(psp)) { 340 /* Write low address of the ring to C2PMSG_102 */ 341 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 342 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 343 /* Write high address of the ring to C2PMSG_103 */ 344 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 345 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 346 347 /* Write the ring initialization command to C2PMSG_101 */ 348 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 349 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 350 351 /* there might be handshake issue with hardware which needs delay */ 352 mdelay(20); 353 354 /* Wait for response flag (bit 31) in C2PMSG_101 */ 355 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 356 0x80000000, 0x8000FFFF, false); 357 358 } else { 359 /* Write low address of the ring to C2PMSG_69 */ 360 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 361 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 362 /* Write high address of the ring to C2PMSG_70 */ 363 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 364 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 365 /* Write size of ring to C2PMSG_71 */ 366 psp_ring_reg = ring->ring_size; 367 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 368 /* Write the ring initialization command to C2PMSG_64 */ 369 psp_ring_reg = ring_type; 370 psp_ring_reg = psp_ring_reg << 16; 371 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 372 373 /* there might be handshake issue with hardware which needs delay */ 374 mdelay(20); 375 376 /* Wait for response flag (bit 31) in C2PMSG_64 */ 377 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 378 0x80000000, 0x8000FFFF, false); 379 } 380 381 return ret; 382 } 383 384 static int psp_v11_0_ring_stop(struct psp_context *psp, 385 enum psp_ring_type ring_type) 386 { 387 int ret = 0; 388 struct amdgpu_device *adev = psp->adev; 389 390 /* Write the ring destroy command*/ 391 if (psp_v11_0_support_vmr_ring(psp)) 392 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 393 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 394 else 395 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 396 GFX_CTRL_CMD_ID_DESTROY_RINGS); 397 398 /* there might be handshake issue with hardware which needs delay */ 399 mdelay(20); 400 401 /* Wait for response flag (bit 31) */ 402 if (psp_v11_0_support_vmr_ring(psp)) 403 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 404 0x80000000, 0x80000000, false); 405 else 406 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 407 0x80000000, 0x80000000, false); 408 409 return ret; 410 } 411 412 static int psp_v11_0_ring_destroy(struct psp_context *psp, 413 enum psp_ring_type ring_type) 414 { 415 int ret = 0; 416 struct psp_ring *ring = &psp->km_ring; 417 struct amdgpu_device *adev = psp->adev; 418 419 ret = psp_v11_0_ring_stop(psp, ring_type); 420 if (ret) 421 DRM_ERROR("Fail to stop psp ring\n"); 422 423 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 424 &ring->ring_mem_mc_addr, 425 (void **)&ring->ring_mem); 426 427 return ret; 428 } 429 430 static int psp_v11_0_cmd_submit(struct psp_context *psp, 431 struct amdgpu_firmware_info *ucode, 432 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 433 int index) 434 { 435 unsigned int psp_write_ptr_reg = 0; 436 struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem; 437 struct psp_ring *ring = &psp->km_ring; 438 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 439 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 440 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 441 struct amdgpu_device *adev = psp->adev; 442 uint32_t ring_size_dw = ring->ring_size / 4; 443 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 444 445 /* KM (GPCOM) prepare write pointer */ 446 if (psp_v11_0_support_vmr_ring(psp)) 447 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 448 else 449 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 450 451 /* Update KM RB frame pointer to new frame */ 452 /* write_frame ptr increments by size of rb_frame in bytes */ 453 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 454 if ((psp_write_ptr_reg % ring_size_dw) == 0) 455 write_frame = ring_buffer_start; 456 else 457 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 458 /* Check invalid write_frame ptr address */ 459 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 460 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 461 ring_buffer_start, ring_buffer_end, write_frame); 462 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 463 return -EINVAL; 464 } 465 466 /* Initialize KM RB frame */ 467 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 468 469 /* Update KM RB frame */ 470 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 471 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 472 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 473 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 474 write_frame->fence_value = index; 475 476 /* Update the write Pointer in DWORDs */ 477 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 478 if (psp_v11_0_support_vmr_ring(psp)) { 479 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg); 480 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 481 } else 482 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 483 484 return 0; 485 } 486 487 static int 488 psp_v11_0_sram_map(struct amdgpu_device *adev, 489 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 490 unsigned int *sram_data_reg_offset, 491 enum AMDGPU_UCODE_ID ucode_id) 492 { 493 int ret = 0; 494 495 switch (ucode_id) { 496 /* TODO: needs to confirm */ 497 #if 0 498 case AMDGPU_UCODE_ID_SMC: 499 *sram_offset = 0; 500 *sram_addr_reg_offset = 0; 501 *sram_data_reg_offset = 0; 502 break; 503 #endif 504 505 case AMDGPU_UCODE_ID_CP_CE: 506 *sram_offset = 0x0; 507 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 508 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 509 break; 510 511 case AMDGPU_UCODE_ID_CP_PFP: 512 *sram_offset = 0x0; 513 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 514 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 515 break; 516 517 case AMDGPU_UCODE_ID_CP_ME: 518 *sram_offset = 0x0; 519 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 520 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 521 break; 522 523 case AMDGPU_UCODE_ID_CP_MEC1: 524 *sram_offset = 0x10000; 525 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 526 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 527 break; 528 529 case AMDGPU_UCODE_ID_CP_MEC2: 530 *sram_offset = 0x10000; 531 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 532 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 533 break; 534 535 case AMDGPU_UCODE_ID_RLC_G: 536 *sram_offset = 0x2000; 537 if (adev->asic_type < CHIP_NAVI10) { 538 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 539 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 540 } else { 541 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10; 542 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10; 543 } 544 break; 545 546 case AMDGPU_UCODE_ID_SDMA0: 547 *sram_offset = 0x0; 548 if (adev->asic_type < CHIP_NAVI10) { 549 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 550 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 551 } else { 552 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10; 553 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10; 554 } 555 break; 556 557 /* TODO: needs to confirm */ 558 #if 0 559 case AMDGPU_UCODE_ID_SDMA1: 560 *sram_offset = ; 561 *sram_addr_reg_offset = ; 562 break; 563 564 case AMDGPU_UCODE_ID_UVD: 565 *sram_offset = ; 566 *sram_addr_reg_offset = ; 567 break; 568 569 case AMDGPU_UCODE_ID_VCE: 570 *sram_offset = ; 571 *sram_addr_reg_offset = ; 572 break; 573 #endif 574 575 case AMDGPU_UCODE_ID_MAXIMUM: 576 default: 577 ret = -EINVAL; 578 break; 579 } 580 581 return ret; 582 } 583 584 static bool psp_v11_0_compare_sram_data(struct psp_context *psp, 585 struct amdgpu_firmware_info *ucode, 586 enum AMDGPU_UCODE_ID ucode_type) 587 { 588 int err = 0; 589 unsigned int fw_sram_reg_val = 0; 590 unsigned int fw_sram_addr_reg_offset = 0; 591 unsigned int fw_sram_data_reg_offset = 0; 592 unsigned int ucode_size; 593 uint32_t *ucode_mem = NULL; 594 struct amdgpu_device *adev = psp->adev; 595 596 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 597 &fw_sram_data_reg_offset, ucode_type); 598 if (err) 599 return false; 600 601 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 602 603 ucode_size = ucode->ucode_size; 604 ucode_mem = (uint32_t *)ucode->kaddr; 605 while (ucode_size) { 606 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 607 608 if (*ucode_mem != fw_sram_reg_val) 609 return false; 610 611 ucode_mem++; 612 /* 4 bytes */ 613 ucode_size -= 4; 614 } 615 616 return true; 617 } 618 619 static int psp_v11_0_mode1_reset(struct psp_context *psp) 620 { 621 int ret; 622 uint32_t offset; 623 struct amdgpu_device *adev = psp->adev; 624 625 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 626 627 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 628 629 if (ret) { 630 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 631 return -EINVAL; 632 } 633 634 /*send the mode 1 reset command*/ 635 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 636 637 msleep(500); 638 639 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 640 641 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 642 643 if (ret) { 644 DRM_INFO("psp mode 1 reset failed!\n"); 645 return -EINVAL; 646 } 647 648 DRM_INFO("psp mode1 reset succeed \n"); 649 650 return 0; 651 } 652 653 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready. 654 * For now, return success and hack the hive_id so high level code can 655 * start testing 656 */ 657 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp, 658 int number_devices, struct psp_xgmi_topology_info *topology) 659 { 660 struct ta_xgmi_shared_memory *xgmi_cmd; 661 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 662 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 663 int i; 664 int ret; 665 666 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 667 return -EINVAL; 668 669 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 670 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 671 672 /* Fill in the shared memory with topology information as input */ 673 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 674 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 675 topology_info_input->num_nodes = number_devices; 676 677 for (i = 0; i < topology_info_input->num_nodes; i++) { 678 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 679 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 680 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 681 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 682 } 683 684 /* Invoke xgmi ta to get the topology information */ 685 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 686 if (ret) 687 return ret; 688 689 /* Read the output topology information from the shared memory */ 690 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 691 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 692 for (i = 0; i < topology->num_nodes; i++) { 693 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 694 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 695 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 696 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 697 } 698 699 return 0; 700 } 701 702 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp, 703 int number_devices, struct psp_xgmi_topology_info *topology) 704 { 705 struct ta_xgmi_shared_memory *xgmi_cmd; 706 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 707 int i; 708 709 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 710 return -EINVAL; 711 712 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 713 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 714 715 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 716 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 717 topology_info_input->num_nodes = number_devices; 718 719 for (i = 0; i < topology_info_input->num_nodes; i++) { 720 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 721 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 722 topology_info_input->nodes[i].is_sharing_enabled = 1; 723 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 724 } 725 726 /* Invoke xgmi ta to set topology information */ 727 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 728 } 729 730 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 731 { 732 struct ta_xgmi_shared_memory *xgmi_cmd; 733 int ret; 734 735 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 736 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 737 738 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 739 740 /* Invoke xgmi ta to get hive id */ 741 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 742 if (ret) 743 return ret; 744 745 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 746 747 return 0; 748 } 749 750 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 751 { 752 struct ta_xgmi_shared_memory *xgmi_cmd; 753 int ret; 754 755 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 756 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 757 758 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 759 760 /* Invoke xgmi ta to get the node id */ 761 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 762 if (ret) 763 return ret; 764 765 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 766 767 return 0; 768 } 769 770 static int psp_v11_0_ras_trigger_error(struct psp_context *psp, 771 struct ta_ras_trigger_error_input *info) 772 { 773 struct ta_ras_shared_memory *ras_cmd; 774 int ret; 775 776 if (!psp->ras.ras_initialized) 777 return -EINVAL; 778 779 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 780 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 781 782 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 783 ras_cmd->ras_in_message.trigger_error = *info; 784 785 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 786 if (ret) 787 return -EINVAL; 788 789 return ras_cmd->ras_status; 790 } 791 792 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr) 793 { 794 #if 0 795 // not support yet. 796 struct ta_ras_shared_memory *ras_cmd; 797 int ret; 798 799 if (!psp->ras.ras_initialized) 800 return -EINVAL; 801 802 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 803 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 804 805 ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON; 806 ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr; 807 808 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 809 if (ret) 810 return -EINVAL; 811 812 return ras_cmd->ras_status; 813 #else 814 return -EINVAL; 815 #endif 816 } 817 818 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp) 819 { 820 return psp_rlc_autoload_start(psp); 821 } 822 823 static const struct psp_funcs psp_v11_0_funcs = { 824 .init_microcode = psp_v11_0_init_microcode, 825 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 826 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 827 .ring_init = psp_v11_0_ring_init, 828 .ring_create = psp_v11_0_ring_create, 829 .ring_stop = psp_v11_0_ring_stop, 830 .ring_destroy = psp_v11_0_ring_destroy, 831 .cmd_submit = psp_v11_0_cmd_submit, 832 .compare_sram_data = psp_v11_0_compare_sram_data, 833 .mode1_reset = psp_v11_0_mode1_reset, 834 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info, 835 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info, 836 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id, 837 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id, 838 .support_vmr_ring = psp_v11_0_support_vmr_ring, 839 .ras_trigger_error = psp_v11_0_ras_trigger_error, 840 .ras_cure_posion = psp_v11_0_ras_cure_posion, 841 .rlc_autoload_start = psp_v11_0_rlc_autoload_start, 842 }; 843 844 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 845 { 846 psp->funcs = &psp_v11_0_funcs; 847 } 848