1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_psp.h" 28 #include "amdgpu_ucode.h" 29 #include "soc15_common.h" 30 #include "psp_v11_0.h" 31 32 #include "mp/mp_11_0_offset.h" 33 #include "mp/mp_11_0_sh_mask.h" 34 #include "gc/gc_9_0_offset.h" 35 #include "sdma0/sdma0_4_0_offset.h" 36 #include "nbio/nbio_7_4_offset.h" 37 38 #include "oss/osssys_4_0_offset.h" 39 #include "oss/osssys_4_0_sh_mask.h" 40 41 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 42 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 43 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 46 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 48 49 /* address block */ 50 #define smnMP1_FIRMWARE_FLAGS 0x3010024 51 /* navi10 reg offset define */ 52 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 53 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 54 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 55 #define mmSDMA0_UCODE_DATA_NV10 0x5881 56 57 static int psp_v11_0_init_microcode(struct psp_context *psp) 58 { 59 struct amdgpu_device *adev = psp->adev; 60 const char *chip_name; 61 char fw_name[30]; 62 int err = 0; 63 const struct psp_firmware_header_v1_0 *sos_hdr; 64 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 65 const struct psp_firmware_header_v1_0 *asd_hdr; 66 const struct ta_firmware_header_v1_0 *ta_hdr; 67 68 DRM_DEBUG("\n"); 69 70 switch (adev->asic_type) { 71 case CHIP_VEGA20: 72 chip_name = "vega20"; 73 break; 74 case CHIP_NAVI10: 75 chip_name = "navi10"; 76 break; 77 case CHIP_NAVI14: 78 chip_name = "navi14"; 79 break; 80 default: 81 BUG(); 82 } 83 84 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 85 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 86 if (err) 87 goto out; 88 89 err = amdgpu_ucode_validate(adev->psp.sos_fw); 90 if (err) 91 goto out; 92 93 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 94 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 95 96 switch (sos_hdr->header.header_version_major) { 97 case 1: 98 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 99 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 100 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 101 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 102 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 103 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 104 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 105 le32_to_cpu(sos_hdr->sos_offset_bytes); 106 if (sos_hdr->header.header_version_minor == 1) { 107 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 108 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 109 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 110 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 111 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 112 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 113 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 114 } 115 break; 116 default: 117 dev_err(adev->dev, 118 "Unsupported psp sos firmware\n"); 119 err = -EINVAL; 120 goto out; 121 } 122 123 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 124 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 125 if (err) 126 goto out1; 127 128 err = amdgpu_ucode_validate(adev->psp.asd_fw); 129 if (err) 130 goto out1; 131 132 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 133 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 134 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 135 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 136 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 137 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 138 139 switch (adev->asic_type) { 140 case CHIP_VEGA20: 141 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 142 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 143 if (err) { 144 release_firmware(adev->psp.ta_fw); 145 adev->psp.ta_fw = NULL; 146 dev_info(adev->dev, 147 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 148 } else { 149 err = amdgpu_ucode_validate(adev->psp.ta_fw); 150 if (err) 151 goto out2; 152 153 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 154 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 155 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 156 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 157 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 158 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 159 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); 160 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); 161 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + 162 le32_to_cpu(ta_hdr->ta_ras_offset_bytes); 163 } 164 break; 165 case CHIP_NAVI10: 166 case CHIP_NAVI14: 167 break; 168 default: 169 BUG(); 170 } 171 172 return 0; 173 174 out2: 175 release_firmware(adev->psp.ta_fw); 176 adev->psp.ta_fw = NULL; 177 out1: 178 release_firmware(adev->psp.asd_fw); 179 adev->psp.asd_fw = NULL; 180 out: 181 dev_err(adev->dev, 182 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 183 release_firmware(adev->psp.sos_fw); 184 adev->psp.sos_fw = NULL; 185 186 return err; 187 } 188 189 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 190 { 191 int ret; 192 uint32_t psp_gfxdrv_command_reg = 0; 193 struct amdgpu_device *adev = psp->adev; 194 uint32_t sol_reg; 195 196 /* Check tOS sign of life register to confirm sys driver and sOS 197 * are already been loaded. 198 */ 199 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 200 if (sol_reg) { 201 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 202 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version); 203 return 0; 204 } 205 206 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 207 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 208 0x80000000, 0x80000000, false); 209 if (ret) 210 return ret; 211 212 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 213 214 /* Copy PSP KDB binary to memory */ 215 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); 216 217 /* Provide the sys driver to bootloader */ 218 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 219 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 220 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; 221 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 222 psp_gfxdrv_command_reg); 223 224 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1*/ 225 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 226 0x80000000, 0x80000000, false); 227 228 return ret; 229 } 230 231 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 232 { 233 int ret; 234 uint32_t psp_gfxdrv_command_reg = 0; 235 struct amdgpu_device *adev = psp->adev; 236 uint32_t sol_reg; 237 238 /* Check sOS sign of life register to confirm sys driver and sOS 239 * are already been loaded. 240 */ 241 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 242 if (sol_reg) { 243 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 244 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version); 245 return 0; 246 } 247 248 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 249 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 250 0x80000000, 0x80000000, false); 251 if (ret) 252 return ret; 253 254 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 255 256 /* Copy PSP System Driver binary to memory */ 257 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 258 259 /* Provide the sys driver to bootloader */ 260 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 261 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 262 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 263 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 264 psp_gfxdrv_command_reg); 265 266 /* there might be handshake issue with hardware which needs delay */ 267 mdelay(20); 268 269 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 270 0x80000000, 0x80000000, false); 271 272 return ret; 273 } 274 275 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 276 { 277 int ret; 278 unsigned int psp_gfxdrv_command_reg = 0; 279 struct amdgpu_device *adev = psp->adev; 280 uint32_t sol_reg; 281 282 /* Check sOS sign of life register to confirm sys driver and sOS 283 * are already been loaded. 284 */ 285 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 286 if (sol_reg) 287 return 0; 288 289 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 290 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 291 0x80000000, 0x80000000, false); 292 if (ret) 293 return ret; 294 295 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 296 297 /* Copy Secure OS binary to PSP memory */ 298 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 299 300 /* Provide the PSP secure OS to bootloader */ 301 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 302 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 303 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 304 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 305 psp_gfxdrv_command_reg); 306 307 /* there might be handshake issue with hardware which needs delay */ 308 mdelay(20); 309 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 310 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 311 0, true); 312 313 return ret; 314 } 315 316 static void psp_v11_0_reroute_ih(struct psp_context *psp) 317 { 318 struct amdgpu_device *adev = psp->adev; 319 uint32_t tmp; 320 321 /* Change IH ring for VMC */ 322 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 323 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 324 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 325 326 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 327 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 328 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 329 330 mdelay(20); 331 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 332 0x80000000, 0x8000FFFF, false); 333 334 /* Change IH ring for UMC */ 335 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 336 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 337 338 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 339 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 340 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 341 342 mdelay(20); 343 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 344 0x80000000, 0x8000FFFF, false); 345 } 346 347 static int psp_v11_0_ring_init(struct psp_context *psp, 348 enum psp_ring_type ring_type) 349 { 350 int ret = 0; 351 struct psp_ring *ring; 352 struct amdgpu_device *adev = psp->adev; 353 354 psp_v11_0_reroute_ih(psp); 355 356 ring = &psp->km_ring; 357 358 ring->ring_type = ring_type; 359 360 /* allocate 4k Page of Local Frame Buffer memory for ring */ 361 ring->ring_size = 0x1000; 362 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 363 AMDGPU_GEM_DOMAIN_VRAM, 364 &adev->firmware.rbuf, 365 &ring->ring_mem_mc_addr, 366 (void **)&ring->ring_mem); 367 if (ret) { 368 ring->ring_size = 0; 369 return ret; 370 } 371 372 return 0; 373 } 374 375 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp) 376 { 377 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045) 378 return true; 379 return false; 380 } 381 382 static int psp_v11_0_ring_create(struct psp_context *psp, 383 enum psp_ring_type ring_type) 384 { 385 int ret = 0; 386 unsigned int psp_ring_reg = 0; 387 struct psp_ring *ring = &psp->km_ring; 388 struct amdgpu_device *adev = psp->adev; 389 390 if (psp_v11_0_support_vmr_ring(psp)) { 391 /* Write low address of the ring to C2PMSG_102 */ 392 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 393 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 394 /* Write high address of the ring to C2PMSG_103 */ 395 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 396 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 397 398 /* Write the ring initialization command to C2PMSG_101 */ 399 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 400 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 401 402 /* there might be handshake issue with hardware which needs delay */ 403 mdelay(20); 404 405 /* Wait for response flag (bit 31) in C2PMSG_101 */ 406 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 407 0x80000000, 0x8000FFFF, false); 408 409 } else { 410 /* Write low address of the ring to C2PMSG_69 */ 411 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 412 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 413 /* Write high address of the ring to C2PMSG_70 */ 414 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 415 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 416 /* Write size of ring to C2PMSG_71 */ 417 psp_ring_reg = ring->ring_size; 418 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 419 /* Write the ring initialization command to C2PMSG_64 */ 420 psp_ring_reg = ring_type; 421 psp_ring_reg = psp_ring_reg << 16; 422 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 423 424 /* there might be handshake issue with hardware which needs delay */ 425 mdelay(20); 426 427 /* Wait for response flag (bit 31) in C2PMSG_64 */ 428 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 429 0x80000000, 0x8000FFFF, false); 430 } 431 432 return ret; 433 } 434 435 static int psp_v11_0_ring_stop(struct psp_context *psp, 436 enum psp_ring_type ring_type) 437 { 438 int ret = 0; 439 struct amdgpu_device *adev = psp->adev; 440 441 /* Write the ring destroy command*/ 442 if (psp_v11_0_support_vmr_ring(psp)) 443 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 444 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 445 else 446 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 447 GFX_CTRL_CMD_ID_DESTROY_RINGS); 448 449 /* there might be handshake issue with hardware which needs delay */ 450 mdelay(20); 451 452 /* Wait for response flag (bit 31) */ 453 if (psp_v11_0_support_vmr_ring(psp)) 454 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 455 0x80000000, 0x80000000, false); 456 else 457 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 458 0x80000000, 0x80000000, false); 459 460 return ret; 461 } 462 463 static int psp_v11_0_ring_destroy(struct psp_context *psp, 464 enum psp_ring_type ring_type) 465 { 466 int ret = 0; 467 struct psp_ring *ring = &psp->km_ring; 468 struct amdgpu_device *adev = psp->adev; 469 470 ret = psp_v11_0_ring_stop(psp, ring_type); 471 if (ret) 472 DRM_ERROR("Fail to stop psp ring\n"); 473 474 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 475 &ring->ring_mem_mc_addr, 476 (void **)&ring->ring_mem); 477 478 return ret; 479 } 480 481 static int psp_v11_0_cmd_submit(struct psp_context *psp, 482 struct amdgpu_firmware_info *ucode, 483 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 484 int index) 485 { 486 unsigned int psp_write_ptr_reg = 0; 487 struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem; 488 struct psp_ring *ring = &psp->km_ring; 489 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 490 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 491 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 492 struct amdgpu_device *adev = psp->adev; 493 uint32_t ring_size_dw = ring->ring_size / 4; 494 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 495 496 /* KM (GPCOM) prepare write pointer */ 497 if (psp_v11_0_support_vmr_ring(psp)) 498 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 499 else 500 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 501 502 /* Update KM RB frame pointer to new frame */ 503 /* write_frame ptr increments by size of rb_frame in bytes */ 504 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 505 if ((psp_write_ptr_reg % ring_size_dw) == 0) 506 write_frame = ring_buffer_start; 507 else 508 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 509 /* Check invalid write_frame ptr address */ 510 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 511 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 512 ring_buffer_start, ring_buffer_end, write_frame); 513 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 514 return -EINVAL; 515 } 516 517 /* Initialize KM RB frame */ 518 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 519 520 /* Update KM RB frame */ 521 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 522 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 523 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 524 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 525 write_frame->fence_value = index; 526 527 /* Update the write Pointer in DWORDs */ 528 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 529 if (psp_v11_0_support_vmr_ring(psp)) { 530 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg); 531 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 532 } else 533 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 534 535 return 0; 536 } 537 538 static int 539 psp_v11_0_sram_map(struct amdgpu_device *adev, 540 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 541 unsigned int *sram_data_reg_offset, 542 enum AMDGPU_UCODE_ID ucode_id) 543 { 544 int ret = 0; 545 546 switch (ucode_id) { 547 /* TODO: needs to confirm */ 548 #if 0 549 case AMDGPU_UCODE_ID_SMC: 550 *sram_offset = 0; 551 *sram_addr_reg_offset = 0; 552 *sram_data_reg_offset = 0; 553 break; 554 #endif 555 556 case AMDGPU_UCODE_ID_CP_CE: 557 *sram_offset = 0x0; 558 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 559 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 560 break; 561 562 case AMDGPU_UCODE_ID_CP_PFP: 563 *sram_offset = 0x0; 564 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 565 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 566 break; 567 568 case AMDGPU_UCODE_ID_CP_ME: 569 *sram_offset = 0x0; 570 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 571 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 572 break; 573 574 case AMDGPU_UCODE_ID_CP_MEC1: 575 *sram_offset = 0x10000; 576 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 577 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 578 break; 579 580 case AMDGPU_UCODE_ID_CP_MEC2: 581 *sram_offset = 0x10000; 582 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 583 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 584 break; 585 586 case AMDGPU_UCODE_ID_RLC_G: 587 *sram_offset = 0x2000; 588 if (adev->asic_type < CHIP_NAVI10) { 589 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 590 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 591 } else { 592 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10; 593 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10; 594 } 595 break; 596 597 case AMDGPU_UCODE_ID_SDMA0: 598 *sram_offset = 0x0; 599 if (adev->asic_type < CHIP_NAVI10) { 600 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 601 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 602 } else { 603 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10; 604 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10; 605 } 606 break; 607 608 /* TODO: needs to confirm */ 609 #if 0 610 case AMDGPU_UCODE_ID_SDMA1: 611 *sram_offset = ; 612 *sram_addr_reg_offset = ; 613 break; 614 615 case AMDGPU_UCODE_ID_UVD: 616 *sram_offset = ; 617 *sram_addr_reg_offset = ; 618 break; 619 620 case AMDGPU_UCODE_ID_VCE: 621 *sram_offset = ; 622 *sram_addr_reg_offset = ; 623 break; 624 #endif 625 626 case AMDGPU_UCODE_ID_MAXIMUM: 627 default: 628 ret = -EINVAL; 629 break; 630 } 631 632 return ret; 633 } 634 635 static bool psp_v11_0_compare_sram_data(struct psp_context *psp, 636 struct amdgpu_firmware_info *ucode, 637 enum AMDGPU_UCODE_ID ucode_type) 638 { 639 int err = 0; 640 unsigned int fw_sram_reg_val = 0; 641 unsigned int fw_sram_addr_reg_offset = 0; 642 unsigned int fw_sram_data_reg_offset = 0; 643 unsigned int ucode_size; 644 uint32_t *ucode_mem = NULL; 645 struct amdgpu_device *adev = psp->adev; 646 647 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 648 &fw_sram_data_reg_offset, ucode_type); 649 if (err) 650 return false; 651 652 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 653 654 ucode_size = ucode->ucode_size; 655 ucode_mem = (uint32_t *)ucode->kaddr; 656 while (ucode_size) { 657 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 658 659 if (*ucode_mem != fw_sram_reg_val) 660 return false; 661 662 ucode_mem++; 663 /* 4 bytes */ 664 ucode_size -= 4; 665 } 666 667 return true; 668 } 669 670 static int psp_v11_0_mode1_reset(struct psp_context *psp) 671 { 672 int ret; 673 uint32_t offset; 674 struct amdgpu_device *adev = psp->adev; 675 676 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 677 678 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 679 680 if (ret) { 681 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 682 return -EINVAL; 683 } 684 685 /*send the mode 1 reset command*/ 686 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 687 688 msleep(500); 689 690 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 691 692 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 693 694 if (ret) { 695 DRM_INFO("psp mode 1 reset failed!\n"); 696 return -EINVAL; 697 } 698 699 DRM_INFO("psp mode1 reset succeed \n"); 700 701 return 0; 702 } 703 704 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready. 705 * For now, return success and hack the hive_id so high level code can 706 * start testing 707 */ 708 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp, 709 int number_devices, struct psp_xgmi_topology_info *topology) 710 { 711 struct ta_xgmi_shared_memory *xgmi_cmd; 712 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 713 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 714 int i; 715 int ret; 716 717 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 718 return -EINVAL; 719 720 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 721 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 722 723 /* Fill in the shared memory with topology information as input */ 724 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 725 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 726 topology_info_input->num_nodes = number_devices; 727 728 for (i = 0; i < topology_info_input->num_nodes; i++) { 729 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 730 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 731 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 732 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 733 } 734 735 /* Invoke xgmi ta to get the topology information */ 736 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 737 if (ret) 738 return ret; 739 740 /* Read the output topology information from the shared memory */ 741 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 742 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 743 for (i = 0; i < topology->num_nodes; i++) { 744 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 745 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 746 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 747 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 748 } 749 750 return 0; 751 } 752 753 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp, 754 int number_devices, struct psp_xgmi_topology_info *topology) 755 { 756 struct ta_xgmi_shared_memory *xgmi_cmd; 757 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 758 int i; 759 760 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 761 return -EINVAL; 762 763 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 764 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 765 766 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 767 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 768 topology_info_input->num_nodes = number_devices; 769 770 for (i = 0; i < topology_info_input->num_nodes; i++) { 771 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 772 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 773 topology_info_input->nodes[i].is_sharing_enabled = 1; 774 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 775 } 776 777 /* Invoke xgmi ta to set topology information */ 778 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 779 } 780 781 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 782 { 783 struct ta_xgmi_shared_memory *xgmi_cmd; 784 int ret; 785 786 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 787 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 788 789 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 790 791 /* Invoke xgmi ta to get hive id */ 792 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 793 if (ret) 794 return ret; 795 796 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 797 798 return 0; 799 } 800 801 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 802 { 803 struct ta_xgmi_shared_memory *xgmi_cmd; 804 int ret; 805 806 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 807 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 808 809 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 810 811 /* Invoke xgmi ta to get the node id */ 812 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 813 if (ret) 814 return ret; 815 816 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 817 818 return 0; 819 } 820 821 static int psp_v11_0_ras_trigger_error(struct psp_context *psp, 822 struct ta_ras_trigger_error_input *info) 823 { 824 struct ta_ras_shared_memory *ras_cmd; 825 int ret; 826 827 if (!psp->ras.ras_initialized) 828 return -EINVAL; 829 830 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 831 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 832 833 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 834 ras_cmd->ras_in_message.trigger_error = *info; 835 836 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 837 if (ret) 838 return -EINVAL; 839 840 return ras_cmd->ras_status; 841 } 842 843 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr) 844 { 845 #if 0 846 // not support yet. 847 struct ta_ras_shared_memory *ras_cmd; 848 int ret; 849 850 if (!psp->ras.ras_initialized) 851 return -EINVAL; 852 853 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 854 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 855 856 ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON; 857 ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr; 858 859 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 860 if (ret) 861 return -EINVAL; 862 863 return ras_cmd->ras_status; 864 #else 865 return -EINVAL; 866 #endif 867 } 868 869 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp) 870 { 871 return psp_rlc_autoload_start(psp); 872 } 873 874 static const struct psp_funcs psp_v11_0_funcs = { 875 .init_microcode = psp_v11_0_init_microcode, 876 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 877 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 878 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 879 .ring_init = psp_v11_0_ring_init, 880 .ring_create = psp_v11_0_ring_create, 881 .ring_stop = psp_v11_0_ring_stop, 882 .ring_destroy = psp_v11_0_ring_destroy, 883 .cmd_submit = psp_v11_0_cmd_submit, 884 .compare_sram_data = psp_v11_0_compare_sram_data, 885 .mode1_reset = psp_v11_0_mode1_reset, 886 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info, 887 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info, 888 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id, 889 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id, 890 .support_vmr_ring = psp_v11_0_support_vmr_ring, 891 .ras_trigger_error = psp_v11_0_ras_trigger_error, 892 .ras_cure_posion = psp_v11_0_ras_cure_posion, 893 .rlc_autoload_start = psp_v11_0_rlc_autoload_start, 894 }; 895 896 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 897 { 898 psp->funcs = &psp_v11_0_funcs; 899 } 900