1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/vmalloc.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_psp.h" 29 #include "amdgpu_ras.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v11_0.h" 33 34 #include "mp/mp_11_0_offset.h" 35 #include "mp/mp_11_0_sh_mask.h" 36 #include "gc/gc_9_0_offset.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "nbio/nbio_7_4_offset.h" 39 40 #include "oss/osssys_4_0_offset.h" 41 #include "oss/osssys_4_0_sh_mask.h" 42 43 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 45 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 48 MODULE_FIRMWARE("amdgpu/navi10_ta.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 50 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 51 MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 53 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 54 MODULE_FIRMWARE("amdgpu/navi12_ta.bin"); 55 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 56 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 57 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 58 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin"); 59 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin"); 61 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin"); 62 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin"); 63 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin"); 64 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin"); 65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_asd.bin"); 66 67 /* address block */ 68 #define smnMP1_FIRMWARE_FLAGS 0x3010024 69 /* navi10 reg offset define */ 70 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 71 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 72 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 73 #define mmSDMA0_UCODE_DATA_NV10 0x5881 74 /* memory training timeout define */ 75 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 76 77 /* For large FW files the time to complete can be very long */ 78 #define USBC_PD_POLLING_LIMIT_S 240 79 80 static int psp_v11_0_init_microcode(struct psp_context *psp) 81 { 82 struct amdgpu_device *adev = psp->adev; 83 const char *chip_name; 84 char fw_name[PSP_FW_NAME_LEN]; 85 int err = 0; 86 const struct ta_firmware_header_v1_0 *ta_hdr; 87 88 DRM_DEBUG("\n"); 89 90 switch (adev->asic_type) { 91 case CHIP_VEGA20: 92 chip_name = "vega20"; 93 break; 94 case CHIP_NAVI10: 95 chip_name = "navi10"; 96 break; 97 case CHIP_NAVI14: 98 chip_name = "navi14"; 99 break; 100 case CHIP_NAVI12: 101 chip_name = "navi12"; 102 break; 103 case CHIP_ARCTURUS: 104 chip_name = "arcturus"; 105 break; 106 case CHIP_SIENNA_CICHLID: 107 chip_name = "sienna_cichlid"; 108 break; 109 case CHIP_NAVY_FLOUNDER: 110 chip_name = "navy_flounder"; 111 break; 112 case CHIP_VANGOGH: 113 chip_name = "vangogh"; 114 break; 115 case CHIP_DIMGREY_CAVEFISH: 116 chip_name = "dimgrey_cavefish"; 117 break; 118 default: 119 BUG(); 120 } 121 122 123 switch (adev->asic_type) { 124 case CHIP_VEGA20: 125 case CHIP_ARCTURUS: 126 err = psp_init_sos_microcode(psp, chip_name); 127 if (err) 128 return err; 129 err = psp_init_asd_microcode(psp, chip_name); 130 if (err) 131 return err; 132 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 133 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 134 if (err) { 135 release_firmware(adev->psp.ta_fw); 136 adev->psp.ta_fw = NULL; 137 dev_info(adev->dev, 138 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 139 } else { 140 err = amdgpu_ucode_validate(adev->psp.ta_fw); 141 if (err) 142 goto out2; 143 144 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 145 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 146 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 147 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 148 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 149 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 150 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); 151 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); 152 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + 153 le32_to_cpu(ta_hdr->ta_ras_offset_bytes); 154 } 155 break; 156 case CHIP_NAVI10: 157 case CHIP_NAVI14: 158 case CHIP_NAVI12: 159 err = psp_init_sos_microcode(psp, chip_name); 160 if (err) 161 return err; 162 err = psp_init_asd_microcode(psp, chip_name); 163 if (err) 164 return err; 165 if (amdgpu_sriov_vf(adev)) 166 break; 167 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 168 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 169 if (err) { 170 release_firmware(adev->psp.ta_fw); 171 adev->psp.ta_fw = NULL; 172 dev_info(adev->dev, 173 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 174 } else { 175 err = amdgpu_ucode_validate(adev->psp.ta_fw); 176 if (err) 177 goto out2; 178 179 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 180 adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 181 adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 182 adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr + 183 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 184 185 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 186 187 adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 188 adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 189 adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr + 190 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 191 } 192 break; 193 case CHIP_SIENNA_CICHLID: 194 case CHIP_NAVY_FLOUNDER: 195 err = psp_init_sos_microcode(psp, chip_name); 196 if (err) 197 return err; 198 err = psp_init_ta_microcode(&adev->psp, chip_name); 199 if (err) 200 return err; 201 break; 202 case CHIP_DIMGREY_CAVEFISH: 203 err = psp_init_sos_microcode(psp, chip_name); 204 if (err) 205 return err; 206 break; 207 case CHIP_VANGOGH: 208 err = psp_init_asd_microcode(psp, chip_name); 209 if (err) 210 return err; 211 err = psp_init_toc_microcode(psp, chip_name); 212 if (err) 213 return err; 214 break; 215 default: 216 BUG(); 217 } 218 219 return 0; 220 221 out2: 222 release_firmware(adev->psp.ta_fw); 223 adev->psp.ta_fw = NULL; 224 return err; 225 } 226 227 int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 228 { 229 struct amdgpu_device *adev = psp->adev; 230 231 int ret; 232 int retry_loop; 233 234 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 235 /* Wait for bootloader to signify that is 236 ready having bit 31 of C2PMSG_35 set to 1 */ 237 ret = psp_wait_for(psp, 238 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 239 0x80000000, 240 0x80000000, 241 false); 242 243 if (ret == 0) 244 return 0; 245 } 246 247 return ret; 248 } 249 250 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 251 { 252 struct amdgpu_device *adev = psp->adev; 253 uint32_t sol_reg; 254 255 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 256 257 return sol_reg != 0x0; 258 } 259 260 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 261 { 262 int ret; 263 uint32_t psp_gfxdrv_command_reg = 0; 264 struct amdgpu_device *adev = psp->adev; 265 266 /* Check tOS sign of life register to confirm sys driver and sOS 267 * are already been loaded. 268 */ 269 if (psp_v11_0_is_sos_alive(psp)) 270 return 0; 271 272 ret = psp_v11_0_wait_for_bootloader(psp); 273 if (ret) 274 return ret; 275 276 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 277 278 /* Copy PSP KDB binary to memory */ 279 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); 280 281 /* Provide the PSP KDB to bootloader */ 282 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 283 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 284 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; 285 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 286 psp_gfxdrv_command_reg); 287 288 ret = psp_v11_0_wait_for_bootloader(psp); 289 290 return ret; 291 } 292 293 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp) 294 { 295 int ret; 296 uint32_t psp_gfxdrv_command_reg = 0; 297 struct amdgpu_device *adev = psp->adev; 298 299 /* Check tOS sign of life register to confirm sys driver and sOS 300 * are already been loaded. 301 */ 302 if (psp_v11_0_is_sos_alive(psp)) 303 return 0; 304 305 ret = psp_v11_0_wait_for_bootloader(psp); 306 if (ret) 307 return ret; 308 309 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 310 311 /* Copy PSP SPL binary to memory */ 312 memcpy(psp->fw_pri_buf, psp->spl_start_addr, psp->spl_bin_size); 313 314 /* Provide the PSP SPL to bootloader */ 315 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 316 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 317 psp_gfxdrv_command_reg = PSP_BL__LOAD_TOS_SPL_TABLE; 318 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 319 psp_gfxdrv_command_reg); 320 321 ret = psp_v11_0_wait_for_bootloader(psp); 322 323 return ret; 324 } 325 326 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 327 { 328 int ret; 329 uint32_t psp_gfxdrv_command_reg = 0; 330 struct amdgpu_device *adev = psp->adev; 331 332 /* Check sOS sign of life register to confirm sys driver and sOS 333 * are already been loaded. 334 */ 335 if (psp_v11_0_is_sos_alive(psp)) 336 return 0; 337 338 ret = psp_v11_0_wait_for_bootloader(psp); 339 if (ret) 340 return ret; 341 342 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 343 344 /* Copy PSP System Driver binary to memory */ 345 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 346 347 /* Provide the sys driver to bootloader */ 348 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 349 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 350 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 351 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 352 psp_gfxdrv_command_reg); 353 354 /* there might be handshake issue with hardware which needs delay */ 355 mdelay(20); 356 357 ret = psp_v11_0_wait_for_bootloader(psp); 358 359 return ret; 360 } 361 362 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 363 { 364 int ret; 365 unsigned int psp_gfxdrv_command_reg = 0; 366 struct amdgpu_device *adev = psp->adev; 367 368 /* Check sOS sign of life register to confirm sys driver and sOS 369 * are already been loaded. 370 */ 371 if (psp_v11_0_is_sos_alive(psp)) 372 return 0; 373 374 ret = psp_v11_0_wait_for_bootloader(psp); 375 if (ret) 376 return ret; 377 378 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 379 380 /* Copy Secure OS binary to PSP memory */ 381 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 382 383 /* Provide the PSP secure OS to bootloader */ 384 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 385 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 386 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 387 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 388 psp_gfxdrv_command_reg); 389 390 /* there might be handshake issue with hardware which needs delay */ 391 mdelay(20); 392 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 393 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 394 0, true); 395 396 return ret; 397 } 398 399 static void psp_v11_0_reroute_ih(struct psp_context *psp) 400 { 401 struct amdgpu_device *adev = psp->adev; 402 uint32_t tmp; 403 404 /* Change IH ring for VMC */ 405 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 406 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 407 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 408 409 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 410 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 411 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 412 413 mdelay(20); 414 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 415 0x80000000, 0x8000FFFF, false); 416 417 /* Change IH ring for UMC */ 418 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 419 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 420 421 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 422 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 423 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 424 425 mdelay(20); 426 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 427 0x80000000, 0x8000FFFF, false); 428 } 429 430 static int psp_v11_0_ring_init(struct psp_context *psp, 431 enum psp_ring_type ring_type) 432 { 433 int ret = 0; 434 struct psp_ring *ring; 435 struct amdgpu_device *adev = psp->adev; 436 437 if ((!amdgpu_sriov_vf(adev)) && 438 !(adev->asic_type >= CHIP_SIENNA_CICHLID && 439 adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 440 psp_v11_0_reroute_ih(psp); 441 442 ring = &psp->km_ring; 443 444 ring->ring_type = ring_type; 445 446 /* allocate 4k Page of Local Frame Buffer memory for ring */ 447 ring->ring_size = 0x1000; 448 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 449 AMDGPU_GEM_DOMAIN_VRAM, 450 &adev->firmware.rbuf, 451 &ring->ring_mem_mc_addr, 452 (void **)&ring->ring_mem); 453 if (ret) { 454 ring->ring_size = 0; 455 return ret; 456 } 457 458 return 0; 459 } 460 461 static int psp_v11_0_ring_stop(struct psp_context *psp, 462 enum psp_ring_type ring_type) 463 { 464 int ret = 0; 465 struct amdgpu_device *adev = psp->adev; 466 467 /* Write the ring destroy command*/ 468 if (amdgpu_sriov_vf(adev)) 469 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 470 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 471 else 472 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 473 GFX_CTRL_CMD_ID_DESTROY_RINGS); 474 475 /* there might be handshake issue with hardware which needs delay */ 476 mdelay(20); 477 478 /* Wait for response flag (bit 31) */ 479 if (amdgpu_sriov_vf(adev)) 480 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 481 0x80000000, 0x80000000, false); 482 else 483 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 484 0x80000000, 0x80000000, false); 485 486 return ret; 487 } 488 489 static int psp_v11_0_ring_create(struct psp_context *psp, 490 enum psp_ring_type ring_type) 491 { 492 int ret = 0; 493 unsigned int psp_ring_reg = 0; 494 struct psp_ring *ring = &psp->km_ring; 495 struct amdgpu_device *adev = psp->adev; 496 497 if (amdgpu_sriov_vf(adev)) { 498 ret = psp_v11_0_ring_stop(psp, ring_type); 499 if (ret) { 500 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 501 return ret; 502 } 503 504 /* Write low address of the ring to C2PMSG_102 */ 505 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 506 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 507 /* Write high address of the ring to C2PMSG_103 */ 508 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 509 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 510 511 /* Write the ring initialization command to C2PMSG_101 */ 512 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 513 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 514 515 /* there might be handshake issue with hardware which needs delay */ 516 mdelay(20); 517 518 /* Wait for response flag (bit 31) in C2PMSG_101 */ 519 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 520 0x80000000, 0x8000FFFF, false); 521 522 } else { 523 /* Wait for sOS ready for ring creation */ 524 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 525 0x80000000, 0x80000000, false); 526 if (ret) { 527 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 528 return ret; 529 } 530 531 /* Write low address of the ring to C2PMSG_69 */ 532 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 533 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 534 /* Write high address of the ring to C2PMSG_70 */ 535 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 536 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 537 /* Write size of ring to C2PMSG_71 */ 538 psp_ring_reg = ring->ring_size; 539 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 540 /* Write the ring initialization command to C2PMSG_64 */ 541 psp_ring_reg = ring_type; 542 psp_ring_reg = psp_ring_reg << 16; 543 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 544 545 /* there might be handshake issue with hardware which needs delay */ 546 mdelay(20); 547 548 /* Wait for response flag (bit 31) in C2PMSG_64 */ 549 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 550 0x80000000, 0x8000FFFF, false); 551 } 552 553 return ret; 554 } 555 556 557 static int psp_v11_0_ring_destroy(struct psp_context *psp, 558 enum psp_ring_type ring_type) 559 { 560 int ret = 0; 561 struct psp_ring *ring = &psp->km_ring; 562 struct amdgpu_device *adev = psp->adev; 563 564 ret = psp_v11_0_ring_stop(psp, ring_type); 565 if (ret) 566 DRM_ERROR("Fail to stop psp ring\n"); 567 568 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 569 &ring->ring_mem_mc_addr, 570 (void **)&ring->ring_mem); 571 572 return ret; 573 } 574 575 static int psp_v11_0_mode1_reset(struct psp_context *psp) 576 { 577 int ret; 578 uint32_t offset; 579 struct amdgpu_device *adev = psp->adev; 580 581 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 582 583 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 584 585 if (ret) { 586 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 587 return -EINVAL; 588 } 589 590 /*send the mode 1 reset command*/ 591 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 592 593 msleep(500); 594 595 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 596 597 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 598 599 if (ret) { 600 DRM_INFO("psp mode 1 reset failed!\n"); 601 return -EINVAL; 602 } 603 604 DRM_INFO("psp mode1 reset succeed \n"); 605 606 return 0; 607 } 608 609 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 610 { 611 int ret; 612 int i; 613 uint32_t data_32; 614 int max_wait; 615 struct amdgpu_device *adev = psp->adev; 616 617 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 618 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 619 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 620 621 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 622 for (i = 0; i < max_wait; i++) { 623 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 624 0x80000000, 0x80000000, false); 625 if (ret == 0) 626 break; 627 } 628 if (i < max_wait) 629 ret = 0; 630 else 631 ret = -ETIME; 632 633 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 634 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 635 (ret == 0) ? "succeed" : "failed", 636 i, adev->usec_timeout/1000); 637 return ret; 638 } 639 640 /* 641 * save and restore proces 642 */ 643 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 644 { 645 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 646 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 647 struct amdgpu_device *adev = psp->adev; 648 uint32_t p2c_header[4]; 649 uint32_t sz; 650 void *buf; 651 int ret; 652 653 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 654 DRM_DEBUG("Memory training is not supported.\n"); 655 return 0; 656 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 657 DRM_ERROR("Memory training initialization failure.\n"); 658 return -EINVAL; 659 } 660 661 if (psp_v11_0_is_sos_alive(psp)) { 662 DRM_DEBUG("SOS is alive, skip memory training.\n"); 663 return 0; 664 } 665 666 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 667 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 668 pcache[0], pcache[1], pcache[2], pcache[3], 669 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 670 671 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 672 DRM_DEBUG("Short training depends on restore.\n"); 673 ops |= PSP_MEM_TRAIN_RESTORE; 674 } 675 676 if ((ops & PSP_MEM_TRAIN_RESTORE) && 677 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 678 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 679 ops |= PSP_MEM_TRAIN_SAVE; 680 } 681 682 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 683 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 684 pcache[3] == p2c_header[3])) { 685 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 686 ops |= PSP_MEM_TRAIN_SAVE; 687 } 688 689 if ((ops & PSP_MEM_TRAIN_SAVE) && 690 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 691 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 692 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 693 } 694 695 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 696 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 697 ops |= PSP_MEM_TRAIN_SAVE; 698 } 699 700 DRM_DEBUG("Memory training ops:%x.\n", ops); 701 702 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 703 /* 704 * Long traing will encroach certain mount of bottom VRAM, 705 * saving the content of this bottom VRAM to system memory 706 * before training, and restoring it after training to avoid 707 * VRAM corruption. 708 */ 709 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 710 711 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 712 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 713 adev->gmc.visible_vram_size, 714 adev->mman.aper_base_kaddr); 715 return -EINVAL; 716 } 717 718 buf = vmalloc(sz); 719 if (!buf) { 720 DRM_ERROR("failed to allocate system memory.\n"); 721 return -ENOMEM; 722 } 723 724 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 725 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 726 if (ret) { 727 DRM_ERROR("Send long training msg failed.\n"); 728 vfree(buf); 729 return ret; 730 } 731 732 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 733 adev->nbio.funcs->hdp_flush(adev, NULL); 734 vfree(buf); 735 } 736 737 if (ops & PSP_MEM_TRAIN_SAVE) { 738 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 739 } 740 741 if (ops & PSP_MEM_TRAIN_RESTORE) { 742 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 743 } 744 745 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 746 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 747 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 748 if (ret) { 749 DRM_ERROR("send training msg failed.\n"); 750 return ret; 751 } 752 } 753 ctx->training_cnt++; 754 return 0; 755 } 756 757 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 758 { 759 uint32_t data; 760 struct amdgpu_device *adev = psp->adev; 761 762 if (amdgpu_sriov_vf(adev)) 763 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 764 else 765 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 766 767 return data; 768 } 769 770 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 771 { 772 struct amdgpu_device *adev = psp->adev; 773 774 if (amdgpu_sriov_vf(adev)) { 775 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 776 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 777 } else 778 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 779 } 780 781 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, dma_addr_t dma_addr) 782 { 783 struct amdgpu_device *adev = psp->adev; 784 uint32_t reg_status; 785 int ret, i = 0; 786 787 /* Write lower 32-bit address of the PD Controller FW */ 788 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, lower_32_bits(dma_addr)); 789 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 790 0x80000000, 0x80000000, false); 791 if (ret) 792 return ret; 793 794 /* Fireup interrupt so PSP can pick up the lower address */ 795 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x800000); 796 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 797 0x80000000, 0x80000000, false); 798 if (ret) 799 return ret; 800 801 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 802 803 if ((reg_status & 0xFFFF) != 0) { 804 DRM_ERROR("Lower address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %02x...\n", 805 reg_status & 0xFFFF); 806 return -EIO; 807 } 808 809 /* Write upper 32-bit address of the PD Controller FW */ 810 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, upper_32_bits(dma_addr)); 811 812 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 813 0x80000000, 0x80000000, false); 814 if (ret) 815 return ret; 816 817 /* Fireup interrupt so PSP can pick up the upper address */ 818 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x4000000); 819 820 /* FW load takes very long time */ 821 do { 822 msleep(1000); 823 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 824 825 if (reg_status & 0x80000000) 826 goto done; 827 828 } while (++i < USBC_PD_POLLING_LIMIT_S); 829 830 return -ETIME; 831 done: 832 833 if ((reg_status & 0xFFFF) != 0) { 834 DRM_ERROR("Upper address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = x%04x\n", 835 reg_status & 0xFFFF); 836 return -EIO; 837 } 838 839 return 0; 840 } 841 842 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 843 { 844 struct amdgpu_device *adev = psp->adev; 845 int ret; 846 847 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 848 849 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 850 0x80000000, 0x80000000, false); 851 if (!ret) 852 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36); 853 854 return ret; 855 } 856 857 static const struct psp_funcs psp_v11_0_funcs = { 858 .init_microcode = psp_v11_0_init_microcode, 859 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 860 .bootloader_load_spl = psp_v11_0_bootloader_load_spl, 861 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 862 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 863 .ring_init = psp_v11_0_ring_init, 864 .ring_create = psp_v11_0_ring_create, 865 .ring_stop = psp_v11_0_ring_stop, 866 .ring_destroy = psp_v11_0_ring_destroy, 867 .mode1_reset = psp_v11_0_mode1_reset, 868 .mem_training = psp_v11_0_memory_training, 869 .ring_get_wptr = psp_v11_0_ring_get_wptr, 870 .ring_set_wptr = psp_v11_0_ring_set_wptr, 871 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, 872 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw 873 }; 874 875 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 876 { 877 psp->funcs = &psp_v11_0_funcs; 878 } 879