1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/vmalloc.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_psp.h" 29 #include "amdgpu_ras.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v11_0.h" 33 34 #include "mp/mp_11_0_offset.h" 35 #include "mp/mp_11_0_sh_mask.h" 36 #include "gc/gc_9_0_offset.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "nbio/nbio_7_4_offset.h" 39 40 #include "oss/osssys_4_0_offset.h" 41 #include "oss/osssys_4_0_sh_mask.h" 42 43 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 45 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 48 MODULE_FIRMWARE("amdgpu/navi10_ta.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 50 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 51 MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 53 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 54 MODULE_FIRMWARE("amdgpu/navi12_ta.bin"); 55 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 56 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 57 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 58 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin"); 59 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin"); 61 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin"); 62 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin"); 63 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin"); 64 65 /* address block */ 66 #define smnMP1_FIRMWARE_FLAGS 0x3010024 67 /* navi10 reg offset define */ 68 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 69 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 70 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 71 #define mmSDMA0_UCODE_DATA_NV10 0x5881 72 /* memory training timeout define */ 73 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 74 75 /* For large FW files the time to complete can be very long */ 76 #define USBC_PD_POLLING_LIMIT_S 240 77 78 static int psp_v11_0_init_microcode(struct psp_context *psp) 79 { 80 struct amdgpu_device *adev = psp->adev; 81 const char *chip_name; 82 char fw_name[30]; 83 int err = 0; 84 const struct ta_firmware_header_v1_0 *ta_hdr; 85 86 DRM_DEBUG("\n"); 87 88 switch (adev->asic_type) { 89 case CHIP_VEGA20: 90 chip_name = "vega20"; 91 break; 92 case CHIP_NAVI10: 93 chip_name = "navi10"; 94 break; 95 case CHIP_NAVI14: 96 chip_name = "navi14"; 97 break; 98 case CHIP_NAVI12: 99 chip_name = "navi12"; 100 break; 101 case CHIP_ARCTURUS: 102 chip_name = "arcturus"; 103 break; 104 case CHIP_SIENNA_CICHLID: 105 chip_name = "sienna_cichlid"; 106 break; 107 case CHIP_NAVY_FLOUNDER: 108 chip_name = "navy_flounder"; 109 break; 110 case CHIP_VANGOGH: 111 chip_name = "vangogh"; 112 break; 113 default: 114 BUG(); 115 } 116 117 118 switch (adev->asic_type) { 119 case CHIP_VEGA20: 120 case CHIP_ARCTURUS: 121 err = psp_init_sos_microcode(psp, chip_name); 122 if (err) 123 return err; 124 err = psp_init_asd_microcode(psp, chip_name); 125 if (err) 126 return err; 127 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 128 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 129 if (err) { 130 release_firmware(adev->psp.ta_fw); 131 adev->psp.ta_fw = NULL; 132 dev_info(adev->dev, 133 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 134 } else { 135 err = amdgpu_ucode_validate(adev->psp.ta_fw); 136 if (err) 137 goto out2; 138 139 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 140 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 141 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 142 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 143 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 144 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 145 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); 146 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); 147 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + 148 le32_to_cpu(ta_hdr->ta_ras_offset_bytes); 149 } 150 break; 151 case CHIP_NAVI10: 152 case CHIP_NAVI14: 153 case CHIP_NAVI12: 154 err = psp_init_sos_microcode(psp, chip_name); 155 if (err) 156 return err; 157 err = psp_init_asd_microcode(psp, chip_name); 158 if (err) 159 return err; 160 if (amdgpu_sriov_vf(adev)) 161 break; 162 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 163 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 164 if (err) { 165 release_firmware(adev->psp.ta_fw); 166 adev->psp.ta_fw = NULL; 167 dev_info(adev->dev, 168 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 169 } else { 170 err = amdgpu_ucode_validate(adev->psp.ta_fw); 171 if (err) 172 goto out2; 173 174 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 175 adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 176 adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 177 adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr + 178 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 179 180 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 181 182 adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 183 adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 184 adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr + 185 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 186 } 187 break; 188 case CHIP_SIENNA_CICHLID: 189 case CHIP_NAVY_FLOUNDER: 190 err = psp_init_sos_microcode(psp, chip_name); 191 if (err) 192 return err; 193 err = psp_init_ta_microcode(&adev->psp, chip_name); 194 if (err) 195 return err; 196 break; 197 case CHIP_VANGOGH: 198 err = psp_init_asd_microcode(psp, chip_name); 199 if (err) 200 return err; 201 err = psp_init_toc_microcode(psp, chip_name); 202 if (err) 203 return err; 204 break; 205 default: 206 BUG(); 207 } 208 209 return 0; 210 211 out2: 212 release_firmware(adev->psp.ta_fw); 213 adev->psp.ta_fw = NULL; 214 return err; 215 } 216 217 int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 218 { 219 struct amdgpu_device *adev = psp->adev; 220 221 int ret; 222 int retry_loop; 223 224 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 225 /* Wait for bootloader to signify that is 226 ready having bit 31 of C2PMSG_35 set to 1 */ 227 ret = psp_wait_for(psp, 228 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 229 0x80000000, 230 0x80000000, 231 false); 232 233 if (ret == 0) 234 return 0; 235 } 236 237 return ret; 238 } 239 240 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 241 { 242 struct amdgpu_device *adev = psp->adev; 243 uint32_t sol_reg; 244 245 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 246 247 return sol_reg != 0x0; 248 } 249 250 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 251 { 252 int ret; 253 uint32_t psp_gfxdrv_command_reg = 0; 254 struct amdgpu_device *adev = psp->adev; 255 256 /* Check tOS sign of life register to confirm sys driver and sOS 257 * are already been loaded. 258 */ 259 if (psp_v11_0_is_sos_alive(psp)) 260 return 0; 261 262 ret = psp_v11_0_wait_for_bootloader(psp); 263 if (ret) 264 return ret; 265 266 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 267 268 /* Copy PSP KDB binary to memory */ 269 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); 270 271 /* Provide the PSP KDB to bootloader */ 272 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 273 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 274 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; 275 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 276 psp_gfxdrv_command_reg); 277 278 ret = psp_v11_0_wait_for_bootloader(psp); 279 280 return ret; 281 } 282 283 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp) 284 { 285 int ret; 286 uint32_t psp_gfxdrv_command_reg = 0; 287 struct amdgpu_device *adev = psp->adev; 288 289 /* Check tOS sign of life register to confirm sys driver and sOS 290 * are already been loaded. 291 */ 292 if (psp_v11_0_is_sos_alive(psp)) 293 return 0; 294 295 ret = psp_v11_0_wait_for_bootloader(psp); 296 if (ret) 297 return ret; 298 299 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 300 301 /* Copy PSP SPL binary to memory */ 302 memcpy(psp->fw_pri_buf, psp->spl_start_addr, psp->spl_bin_size); 303 304 /* Provide the PSP SPL to bootloader */ 305 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 306 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 307 psp_gfxdrv_command_reg = PSP_BL__LOAD_TOS_SPL_TABLE; 308 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 309 psp_gfxdrv_command_reg); 310 311 ret = psp_v11_0_wait_for_bootloader(psp); 312 313 return ret; 314 } 315 316 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 317 { 318 int ret; 319 uint32_t psp_gfxdrv_command_reg = 0; 320 struct amdgpu_device *adev = psp->adev; 321 322 /* Check sOS sign of life register to confirm sys driver and sOS 323 * are already been loaded. 324 */ 325 if (psp_v11_0_is_sos_alive(psp)) 326 return 0; 327 328 ret = psp_v11_0_wait_for_bootloader(psp); 329 if (ret) 330 return ret; 331 332 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 333 334 /* Copy PSP System Driver binary to memory */ 335 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 336 337 /* Provide the sys driver to bootloader */ 338 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 339 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 340 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 341 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 342 psp_gfxdrv_command_reg); 343 344 /* there might be handshake issue with hardware which needs delay */ 345 mdelay(20); 346 347 ret = psp_v11_0_wait_for_bootloader(psp); 348 349 return ret; 350 } 351 352 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 353 { 354 int ret; 355 unsigned int psp_gfxdrv_command_reg = 0; 356 struct amdgpu_device *adev = psp->adev; 357 358 /* Check sOS sign of life register to confirm sys driver and sOS 359 * are already been loaded. 360 */ 361 if (psp_v11_0_is_sos_alive(psp)) 362 return 0; 363 364 ret = psp_v11_0_wait_for_bootloader(psp); 365 if (ret) 366 return ret; 367 368 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 369 370 /* Copy Secure OS binary to PSP memory */ 371 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 372 373 /* Provide the PSP secure OS to bootloader */ 374 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 375 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 376 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 377 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 378 psp_gfxdrv_command_reg); 379 380 /* there might be handshake issue with hardware which needs delay */ 381 mdelay(20); 382 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 383 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 384 0, true); 385 386 return ret; 387 } 388 389 static void psp_v11_0_reroute_ih(struct psp_context *psp) 390 { 391 struct amdgpu_device *adev = psp->adev; 392 uint32_t tmp; 393 394 /* Change IH ring for VMC */ 395 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 396 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 397 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 398 399 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 400 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 401 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 402 403 mdelay(20); 404 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 405 0x80000000, 0x8000FFFF, false); 406 407 /* Change IH ring for UMC */ 408 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 409 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 410 411 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 412 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 413 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 414 415 mdelay(20); 416 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 417 0x80000000, 0x8000FFFF, false); 418 } 419 420 static int psp_v11_0_ring_init(struct psp_context *psp, 421 enum psp_ring_type ring_type) 422 { 423 int ret = 0; 424 struct psp_ring *ring; 425 struct amdgpu_device *adev = psp->adev; 426 427 if ((!amdgpu_sriov_vf(adev)) && 428 (adev->asic_type != CHIP_SIENNA_CICHLID) && 429 (adev->asic_type != CHIP_NAVY_FLOUNDER)) 430 psp_v11_0_reroute_ih(psp); 431 432 ring = &psp->km_ring; 433 434 ring->ring_type = ring_type; 435 436 /* allocate 4k Page of Local Frame Buffer memory for ring */ 437 ring->ring_size = 0x1000; 438 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 439 AMDGPU_GEM_DOMAIN_VRAM, 440 &adev->firmware.rbuf, 441 &ring->ring_mem_mc_addr, 442 (void **)&ring->ring_mem); 443 if (ret) { 444 ring->ring_size = 0; 445 return ret; 446 } 447 448 return 0; 449 } 450 451 static int psp_v11_0_ring_stop(struct psp_context *psp, 452 enum psp_ring_type ring_type) 453 { 454 int ret = 0; 455 struct amdgpu_device *adev = psp->adev; 456 457 /* Write the ring destroy command*/ 458 if (amdgpu_sriov_vf(adev)) 459 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 460 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 461 else 462 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 463 GFX_CTRL_CMD_ID_DESTROY_RINGS); 464 465 /* there might be handshake issue with hardware which needs delay */ 466 mdelay(20); 467 468 /* Wait for response flag (bit 31) */ 469 if (amdgpu_sriov_vf(adev)) 470 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 471 0x80000000, 0x80000000, false); 472 else 473 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 474 0x80000000, 0x80000000, false); 475 476 return ret; 477 } 478 479 static int psp_v11_0_ring_create(struct psp_context *psp, 480 enum psp_ring_type ring_type) 481 { 482 int ret = 0; 483 unsigned int psp_ring_reg = 0; 484 struct psp_ring *ring = &psp->km_ring; 485 struct amdgpu_device *adev = psp->adev; 486 487 if (amdgpu_sriov_vf(adev)) { 488 ret = psp_v11_0_ring_stop(psp, ring_type); 489 if (ret) { 490 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 491 return ret; 492 } 493 494 /* Write low address of the ring to C2PMSG_102 */ 495 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 496 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 497 /* Write high address of the ring to C2PMSG_103 */ 498 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 499 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 500 501 /* Write the ring initialization command to C2PMSG_101 */ 502 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 503 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 504 505 /* there might be handshake issue with hardware which needs delay */ 506 mdelay(20); 507 508 /* Wait for response flag (bit 31) in C2PMSG_101 */ 509 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 510 0x80000000, 0x8000FFFF, false); 511 512 } else { 513 /* Wait for sOS ready for ring creation */ 514 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 515 0x80000000, 0x80000000, false); 516 if (ret) { 517 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 518 return ret; 519 } 520 521 /* Write low address of the ring to C2PMSG_69 */ 522 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 523 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 524 /* Write high address of the ring to C2PMSG_70 */ 525 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 526 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 527 /* Write size of ring to C2PMSG_71 */ 528 psp_ring_reg = ring->ring_size; 529 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 530 /* Write the ring initialization command to C2PMSG_64 */ 531 psp_ring_reg = ring_type; 532 psp_ring_reg = psp_ring_reg << 16; 533 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 534 535 /* there might be handshake issue with hardware which needs delay */ 536 mdelay(20); 537 538 /* Wait for response flag (bit 31) in C2PMSG_64 */ 539 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 540 0x80000000, 0x8000FFFF, false); 541 } 542 543 return ret; 544 } 545 546 547 static int psp_v11_0_ring_destroy(struct psp_context *psp, 548 enum psp_ring_type ring_type) 549 { 550 int ret = 0; 551 struct psp_ring *ring = &psp->km_ring; 552 struct amdgpu_device *adev = psp->adev; 553 554 ret = psp_v11_0_ring_stop(psp, ring_type); 555 if (ret) 556 DRM_ERROR("Fail to stop psp ring\n"); 557 558 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 559 &ring->ring_mem_mc_addr, 560 (void **)&ring->ring_mem); 561 562 return ret; 563 } 564 565 static int psp_v11_0_mode1_reset(struct psp_context *psp) 566 { 567 int ret; 568 uint32_t offset; 569 struct amdgpu_device *adev = psp->adev; 570 571 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 572 573 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 574 575 if (ret) { 576 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 577 return -EINVAL; 578 } 579 580 /*send the mode 1 reset command*/ 581 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 582 583 msleep(500); 584 585 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 586 587 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 588 589 if (ret) { 590 DRM_INFO("psp mode 1 reset failed!\n"); 591 return -EINVAL; 592 } 593 594 DRM_INFO("psp mode1 reset succeed \n"); 595 596 return 0; 597 } 598 599 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 600 { 601 int ret; 602 int i; 603 uint32_t data_32; 604 int max_wait; 605 struct amdgpu_device *adev = psp->adev; 606 607 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 608 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 609 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 610 611 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 612 for (i = 0; i < max_wait; i++) { 613 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 614 0x80000000, 0x80000000, false); 615 if (ret == 0) 616 break; 617 } 618 if (i < max_wait) 619 ret = 0; 620 else 621 ret = -ETIME; 622 623 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 624 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 625 (ret == 0) ? "succeed" : "failed", 626 i, adev->usec_timeout/1000); 627 return ret; 628 } 629 630 /* 631 * save and restore proces 632 */ 633 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 634 { 635 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 636 uint32_t *pcache = (uint32_t*)ctx->sys_cache; 637 struct amdgpu_device *adev = psp->adev; 638 uint32_t p2c_header[4]; 639 uint32_t sz; 640 void *buf; 641 int ret; 642 643 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 644 DRM_DEBUG("Memory training is not supported.\n"); 645 return 0; 646 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 647 DRM_ERROR("Memory training initialization failure.\n"); 648 return -EINVAL; 649 } 650 651 if (psp_v11_0_is_sos_alive(psp)) { 652 DRM_DEBUG("SOS is alive, skip memory training.\n"); 653 return 0; 654 } 655 656 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 657 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 658 pcache[0], pcache[1], pcache[2], pcache[3], 659 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 660 661 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 662 DRM_DEBUG("Short training depends on restore.\n"); 663 ops |= PSP_MEM_TRAIN_RESTORE; 664 } 665 666 if ((ops & PSP_MEM_TRAIN_RESTORE) && 667 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 668 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 669 ops |= PSP_MEM_TRAIN_SAVE; 670 } 671 672 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 673 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 674 pcache[3] == p2c_header[3])) { 675 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 676 ops |= PSP_MEM_TRAIN_SAVE; 677 } 678 679 if ((ops & PSP_MEM_TRAIN_SAVE) && 680 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 681 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 682 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 683 } 684 685 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 686 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 687 ops |= PSP_MEM_TRAIN_SAVE; 688 } 689 690 DRM_DEBUG("Memory training ops:%x.\n", ops); 691 692 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 693 /* 694 * Long traing will encroach certain mount of bottom VRAM, 695 * saving the content of this bottom VRAM to system memory 696 * before training, and restoring it after training to avoid 697 * VRAM corruption. 698 */ 699 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 700 701 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 702 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 703 adev->gmc.visible_vram_size, 704 adev->mman.aper_base_kaddr); 705 return -EINVAL; 706 } 707 708 buf = vmalloc(sz); 709 if (!buf) { 710 DRM_ERROR("failed to allocate system memory.\n"); 711 return -ENOMEM; 712 } 713 714 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 715 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 716 if (ret) { 717 DRM_ERROR("Send long training msg failed.\n"); 718 vfree(buf); 719 return ret; 720 } 721 722 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 723 adev->nbio.funcs->hdp_flush(adev, NULL); 724 vfree(buf); 725 } 726 727 if (ops & PSP_MEM_TRAIN_SAVE) { 728 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 729 } 730 731 if (ops & PSP_MEM_TRAIN_RESTORE) { 732 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 733 } 734 735 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 736 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 737 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 738 if (ret) { 739 DRM_ERROR("send training msg failed.\n"); 740 return ret; 741 } 742 } 743 ctx->training_cnt++; 744 return 0; 745 } 746 747 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 748 { 749 uint32_t data; 750 struct amdgpu_device *adev = psp->adev; 751 752 if (amdgpu_sriov_vf(adev)) 753 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 754 else 755 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 756 757 return data; 758 } 759 760 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 761 { 762 struct amdgpu_device *adev = psp->adev; 763 764 if (amdgpu_sriov_vf(adev)) { 765 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 766 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 767 } else 768 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 769 } 770 771 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, dma_addr_t dma_addr) 772 { 773 struct amdgpu_device *adev = psp->adev; 774 uint32_t reg_status; 775 int ret, i = 0; 776 777 /* Write lower 32-bit address of the PD Controller FW */ 778 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, lower_32_bits(dma_addr)); 779 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 780 0x80000000, 0x80000000, false); 781 if (ret) 782 return ret; 783 784 /* Fireup interrupt so PSP can pick up the lower address */ 785 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x800000); 786 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 787 0x80000000, 0x80000000, false); 788 if (ret) 789 return ret; 790 791 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 792 793 if ((reg_status & 0xFFFF) != 0) { 794 DRM_ERROR("Lower address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %02x...\n", 795 reg_status & 0xFFFF); 796 return -EIO; 797 } 798 799 /* Write upper 32-bit address of the PD Controller FW */ 800 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, upper_32_bits(dma_addr)); 801 802 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 803 0x80000000, 0x80000000, false); 804 if (ret) 805 return ret; 806 807 /* Fireup interrupt so PSP can pick up the upper address */ 808 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x4000000); 809 810 /* FW load takes very long time */ 811 do { 812 msleep(1000); 813 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 814 815 if (reg_status & 0x80000000) 816 goto done; 817 818 } while (++i < USBC_PD_POLLING_LIMIT_S); 819 820 return -ETIME; 821 done: 822 823 if ((reg_status & 0xFFFF) != 0) { 824 DRM_ERROR("Upper address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = x%04x\n", 825 reg_status & 0xFFFF); 826 return -EIO; 827 } 828 829 return 0; 830 } 831 832 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 833 { 834 struct amdgpu_device *adev = psp->adev; 835 int ret; 836 837 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 838 839 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 840 0x80000000, 0x80000000, false); 841 if (!ret) 842 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36); 843 844 return ret; 845 } 846 847 static const struct psp_funcs psp_v11_0_funcs = { 848 .init_microcode = psp_v11_0_init_microcode, 849 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 850 .bootloader_load_spl = psp_v11_0_bootloader_load_spl, 851 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 852 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 853 .ring_init = psp_v11_0_ring_init, 854 .ring_create = psp_v11_0_ring_create, 855 .ring_stop = psp_v11_0_ring_stop, 856 .ring_destroy = psp_v11_0_ring_destroy, 857 .mode1_reset = psp_v11_0_mode1_reset, 858 .mem_training = psp_v11_0_memory_training, 859 .ring_get_wptr = psp_v11_0_ring_get_wptr, 860 .ring_set_wptr = psp_v11_0_ring_set_wptr, 861 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, 862 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw 863 }; 864 865 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 866 { 867 psp->funcs = &psp_v11_0_funcs; 868 } 869