1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_psp.h" 28 #include "amdgpu_ucode.h" 29 #include "soc15_common.h" 30 #include "psp_v11_0.h" 31 32 #include "mp/mp_11_0_offset.h" 33 #include "mp/mp_11_0_sh_mask.h" 34 #include "gc/gc_9_0_offset.h" 35 #include "sdma0/sdma0_4_0_offset.h" 36 #include "nbio/nbio_7_4_offset.h" 37 38 #include "oss/osssys_4_0_offset.h" 39 #include "oss/osssys_4_0_sh_mask.h" 40 41 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 42 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 43 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 46 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 48 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 49 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 50 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 51 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 52 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 53 54 /* address block */ 55 #define smnMP1_FIRMWARE_FLAGS 0x3010024 56 /* navi10 reg offset define */ 57 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 58 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 59 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 60 #define mmSDMA0_UCODE_DATA_NV10 0x5881 61 /* memory training timeout define */ 62 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 63 64 static int psp_v11_0_init_microcode(struct psp_context *psp) 65 { 66 struct amdgpu_device *adev = psp->adev; 67 const char *chip_name; 68 char fw_name[30]; 69 int err = 0; 70 const struct psp_firmware_header_v1_0 *sos_hdr; 71 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 72 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 73 const struct psp_firmware_header_v1_0 *asd_hdr; 74 const struct ta_firmware_header_v1_0 *ta_hdr; 75 76 DRM_DEBUG("\n"); 77 78 switch (adev->asic_type) { 79 case CHIP_VEGA20: 80 chip_name = "vega20"; 81 break; 82 case CHIP_NAVI10: 83 chip_name = "navi10"; 84 break; 85 case CHIP_NAVI14: 86 chip_name = "navi14"; 87 break; 88 case CHIP_NAVI12: 89 chip_name = "navi12"; 90 break; 91 case CHIP_ARCTURUS: 92 chip_name = "arcturus"; 93 break; 94 default: 95 BUG(); 96 } 97 98 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 99 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 100 if (err) 101 goto out; 102 103 err = amdgpu_ucode_validate(adev->psp.sos_fw); 104 if (err) 105 goto out; 106 107 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 108 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 109 110 switch (sos_hdr->header.header_version_major) { 111 case 1: 112 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 113 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 114 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 115 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 116 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 117 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 118 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 119 le32_to_cpu(sos_hdr->sos_offset_bytes); 120 if (sos_hdr->header.header_version_minor == 1) { 121 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 122 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 123 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 124 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 125 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 126 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 127 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 128 } 129 if (sos_hdr->header.header_version_minor == 2) { 130 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 131 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 132 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 133 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 134 } 135 break; 136 default: 137 dev_err(adev->dev, 138 "Unsupported psp sos firmware\n"); 139 err = -EINVAL; 140 goto out; 141 } 142 143 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 144 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 145 if (err) 146 goto out1; 147 148 err = amdgpu_ucode_validate(adev->psp.asd_fw); 149 if (err) 150 goto out1; 151 152 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 153 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 154 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 155 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 156 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 157 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 158 159 switch (adev->asic_type) { 160 case CHIP_VEGA20: 161 case CHIP_ARCTURUS: 162 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 163 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 164 if (err) { 165 release_firmware(adev->psp.ta_fw); 166 adev->psp.ta_fw = NULL; 167 dev_info(adev->dev, 168 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 169 } else { 170 err = amdgpu_ucode_validate(adev->psp.ta_fw); 171 if (err) 172 goto out2; 173 174 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 175 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 176 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 177 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 178 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 179 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 180 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); 181 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); 182 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + 183 le32_to_cpu(ta_hdr->ta_ras_offset_bytes); 184 } 185 break; 186 case CHIP_NAVI10: 187 case CHIP_NAVI14: 188 case CHIP_NAVI12: 189 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 190 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 191 if (err) { 192 release_firmware(adev->psp.ta_fw); 193 adev->psp.ta_fw = NULL; 194 dev_info(adev->dev, 195 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 196 } else { 197 err = amdgpu_ucode_validate(adev->psp.ta_fw); 198 if (err) 199 goto out2; 200 201 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 202 adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 203 adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 204 adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr + 205 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 206 207 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 208 209 adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 210 adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 211 adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr + 212 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 213 } 214 break; 215 default: 216 BUG(); 217 } 218 219 return 0; 220 221 out2: 222 release_firmware(adev->psp.ta_fw); 223 adev->psp.ta_fw = NULL; 224 out1: 225 release_firmware(adev->psp.asd_fw); 226 adev->psp.asd_fw = NULL; 227 out: 228 dev_err(adev->dev, 229 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 230 release_firmware(adev->psp.sos_fw); 231 adev->psp.sos_fw = NULL; 232 233 return err; 234 } 235 236 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 237 { 238 struct amdgpu_device *adev = psp->adev; 239 uint32_t sol_reg; 240 241 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 242 243 return sol_reg != 0x0; 244 } 245 246 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 247 { 248 int ret; 249 uint32_t psp_gfxdrv_command_reg = 0; 250 struct amdgpu_device *adev = psp->adev; 251 252 /* Check tOS sign of life register to confirm sys driver and sOS 253 * are already been loaded. 254 */ 255 if (psp_v11_0_is_sos_alive(psp)) { 256 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 257 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version); 258 return 0; 259 } 260 261 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 262 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 263 0x80000000, 0x80000000, false); 264 if (ret) 265 return ret; 266 267 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 268 269 /* Copy PSP KDB binary to memory */ 270 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); 271 272 /* Provide the PSP KDB to bootloader */ 273 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 274 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 275 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; 276 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 277 psp_gfxdrv_command_reg); 278 279 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1*/ 280 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 281 0x80000000, 0x80000000, false); 282 283 return ret; 284 } 285 286 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 287 { 288 int ret; 289 uint32_t psp_gfxdrv_command_reg = 0; 290 struct amdgpu_device *adev = psp->adev; 291 292 /* Check sOS sign of life register to confirm sys driver and sOS 293 * are already been loaded. 294 */ 295 if (psp_v11_0_is_sos_alive(psp)) { 296 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 297 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version); 298 return 0; 299 } 300 301 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 302 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 303 0x80000000, 0x80000000, false); 304 if (ret) 305 return ret; 306 307 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 308 309 /* Copy PSP System Driver binary to memory */ 310 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 311 312 /* Provide the sys driver to bootloader */ 313 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 314 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 315 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 316 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 317 psp_gfxdrv_command_reg); 318 319 /* there might be handshake issue with hardware which needs delay */ 320 mdelay(20); 321 322 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 323 0x80000000, 0x80000000, false); 324 325 return ret; 326 } 327 328 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 329 { 330 int ret; 331 unsigned int psp_gfxdrv_command_reg = 0; 332 struct amdgpu_device *adev = psp->adev; 333 334 /* Check sOS sign of life register to confirm sys driver and sOS 335 * are already been loaded. 336 */ 337 if (psp_v11_0_is_sos_alive(psp)) 338 return 0; 339 340 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 341 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 342 0x80000000, 0x80000000, false); 343 if (ret) 344 return ret; 345 346 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 347 348 /* Copy Secure OS binary to PSP memory */ 349 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 350 351 /* Provide the PSP secure OS to bootloader */ 352 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 353 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 354 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 355 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 356 psp_gfxdrv_command_reg); 357 358 /* there might be handshake issue with hardware which needs delay */ 359 mdelay(20); 360 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 361 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 362 0, true); 363 364 return ret; 365 } 366 367 static void psp_v11_0_reroute_ih(struct psp_context *psp) 368 { 369 struct amdgpu_device *adev = psp->adev; 370 uint32_t tmp; 371 372 /* Change IH ring for VMC */ 373 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 374 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 375 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 376 377 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 378 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 379 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 380 381 mdelay(20); 382 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 383 0x80000000, 0x8000FFFF, false); 384 385 /* Change IH ring for UMC */ 386 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 387 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 388 389 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 390 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 391 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 392 393 mdelay(20); 394 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 395 0x80000000, 0x8000FFFF, false); 396 } 397 398 static int psp_v11_0_ring_init(struct psp_context *psp, 399 enum psp_ring_type ring_type) 400 { 401 int ret = 0; 402 struct psp_ring *ring; 403 struct amdgpu_device *adev = psp->adev; 404 405 psp_v11_0_reroute_ih(psp); 406 407 ring = &psp->km_ring; 408 409 ring->ring_type = ring_type; 410 411 /* allocate 4k Page of Local Frame Buffer memory for ring */ 412 ring->ring_size = 0x1000; 413 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 414 AMDGPU_GEM_DOMAIN_VRAM, 415 &adev->firmware.rbuf, 416 &ring->ring_mem_mc_addr, 417 (void **)&ring->ring_mem); 418 if (ret) { 419 ring->ring_size = 0; 420 return ret; 421 } 422 423 return 0; 424 } 425 426 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp) 427 { 428 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045) 429 return true; 430 return false; 431 } 432 433 static int psp_v11_0_ring_stop(struct psp_context *psp, 434 enum psp_ring_type ring_type) 435 { 436 int ret = 0; 437 struct amdgpu_device *adev = psp->adev; 438 439 /* Write the ring destroy command*/ 440 if (psp_v11_0_support_vmr_ring(psp)) 441 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 442 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 443 else 444 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 445 GFX_CTRL_CMD_ID_DESTROY_RINGS); 446 447 /* there might be handshake issue with hardware which needs delay */ 448 mdelay(20); 449 450 /* Wait for response flag (bit 31) */ 451 if (psp_v11_0_support_vmr_ring(psp)) 452 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 453 0x80000000, 0x80000000, false); 454 else 455 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 456 0x80000000, 0x80000000, false); 457 458 return ret; 459 } 460 461 static int psp_v11_0_ring_create(struct psp_context *psp, 462 enum psp_ring_type ring_type) 463 { 464 int ret = 0; 465 unsigned int psp_ring_reg = 0; 466 struct psp_ring *ring = &psp->km_ring; 467 struct amdgpu_device *adev = psp->adev; 468 469 if (psp_v11_0_support_vmr_ring(psp)) { 470 ret = psp_v11_0_ring_stop(psp, ring_type); 471 if (ret) { 472 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 473 return ret; 474 } 475 476 /* Write low address of the ring to C2PMSG_102 */ 477 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 478 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 479 /* Write high address of the ring to C2PMSG_103 */ 480 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 481 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 482 483 /* Write the ring initialization command to C2PMSG_101 */ 484 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 485 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 486 487 /* there might be handshake issue with hardware which needs delay */ 488 mdelay(20); 489 490 /* Wait for response flag (bit 31) in C2PMSG_101 */ 491 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 492 0x80000000, 0x8000FFFF, false); 493 494 } else { 495 /* Wait for sOS ready for ring creation */ 496 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 497 0x80000000, 0x80000000, false); 498 if (ret) { 499 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 500 return ret; 501 } 502 503 /* Write low address of the ring to C2PMSG_69 */ 504 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 505 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 506 /* Write high address of the ring to C2PMSG_70 */ 507 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 508 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 509 /* Write size of ring to C2PMSG_71 */ 510 psp_ring_reg = ring->ring_size; 511 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 512 /* Write the ring initialization command to C2PMSG_64 */ 513 psp_ring_reg = ring_type; 514 psp_ring_reg = psp_ring_reg << 16; 515 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 516 517 /* there might be handshake issue with hardware which needs delay */ 518 mdelay(20); 519 520 /* Wait for response flag (bit 31) in C2PMSG_64 */ 521 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 522 0x80000000, 0x8000FFFF, false); 523 } 524 525 return ret; 526 } 527 528 529 static int psp_v11_0_ring_destroy(struct psp_context *psp, 530 enum psp_ring_type ring_type) 531 { 532 int ret = 0; 533 struct psp_ring *ring = &psp->km_ring; 534 struct amdgpu_device *adev = psp->adev; 535 536 ret = psp_v11_0_ring_stop(psp, ring_type); 537 if (ret) 538 DRM_ERROR("Fail to stop psp ring\n"); 539 540 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 541 &ring->ring_mem_mc_addr, 542 (void **)&ring->ring_mem); 543 544 return ret; 545 } 546 547 static int 548 psp_v11_0_sram_map(struct amdgpu_device *adev, 549 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 550 unsigned int *sram_data_reg_offset, 551 enum AMDGPU_UCODE_ID ucode_id) 552 { 553 int ret = 0; 554 555 switch (ucode_id) { 556 /* TODO: needs to confirm */ 557 #if 0 558 case AMDGPU_UCODE_ID_SMC: 559 *sram_offset = 0; 560 *sram_addr_reg_offset = 0; 561 *sram_data_reg_offset = 0; 562 break; 563 #endif 564 565 case AMDGPU_UCODE_ID_CP_CE: 566 *sram_offset = 0x0; 567 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 568 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 569 break; 570 571 case AMDGPU_UCODE_ID_CP_PFP: 572 *sram_offset = 0x0; 573 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 574 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 575 break; 576 577 case AMDGPU_UCODE_ID_CP_ME: 578 *sram_offset = 0x0; 579 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 580 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 581 break; 582 583 case AMDGPU_UCODE_ID_CP_MEC1: 584 *sram_offset = 0x10000; 585 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 586 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 587 break; 588 589 case AMDGPU_UCODE_ID_CP_MEC2: 590 *sram_offset = 0x10000; 591 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 592 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 593 break; 594 595 case AMDGPU_UCODE_ID_RLC_G: 596 *sram_offset = 0x2000; 597 if (adev->asic_type < CHIP_NAVI10) { 598 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 599 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 600 } else { 601 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10; 602 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10; 603 } 604 break; 605 606 case AMDGPU_UCODE_ID_SDMA0: 607 *sram_offset = 0x0; 608 if (adev->asic_type < CHIP_NAVI10) { 609 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 610 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 611 } else { 612 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10; 613 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10; 614 } 615 break; 616 617 /* TODO: needs to confirm */ 618 #if 0 619 case AMDGPU_UCODE_ID_SDMA1: 620 *sram_offset = ; 621 *sram_addr_reg_offset = ; 622 break; 623 624 case AMDGPU_UCODE_ID_UVD: 625 *sram_offset = ; 626 *sram_addr_reg_offset = ; 627 break; 628 629 case AMDGPU_UCODE_ID_VCE: 630 *sram_offset = ; 631 *sram_addr_reg_offset = ; 632 break; 633 #endif 634 635 case AMDGPU_UCODE_ID_MAXIMUM: 636 default: 637 ret = -EINVAL; 638 break; 639 } 640 641 return ret; 642 } 643 644 static bool psp_v11_0_compare_sram_data(struct psp_context *psp, 645 struct amdgpu_firmware_info *ucode, 646 enum AMDGPU_UCODE_ID ucode_type) 647 { 648 int err = 0; 649 unsigned int fw_sram_reg_val = 0; 650 unsigned int fw_sram_addr_reg_offset = 0; 651 unsigned int fw_sram_data_reg_offset = 0; 652 unsigned int ucode_size; 653 uint32_t *ucode_mem = NULL; 654 struct amdgpu_device *adev = psp->adev; 655 656 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 657 &fw_sram_data_reg_offset, ucode_type); 658 if (err) 659 return false; 660 661 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 662 663 ucode_size = ucode->ucode_size; 664 ucode_mem = (uint32_t *)ucode->kaddr; 665 while (ucode_size) { 666 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 667 668 if (*ucode_mem != fw_sram_reg_val) 669 return false; 670 671 ucode_mem++; 672 /* 4 bytes */ 673 ucode_size -= 4; 674 } 675 676 return true; 677 } 678 679 static int psp_v11_0_mode1_reset(struct psp_context *psp) 680 { 681 int ret; 682 uint32_t offset; 683 struct amdgpu_device *adev = psp->adev; 684 685 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 686 687 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 688 689 if (ret) { 690 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 691 return -EINVAL; 692 } 693 694 /*send the mode 1 reset command*/ 695 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 696 697 msleep(500); 698 699 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 700 701 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 702 703 if (ret) { 704 DRM_INFO("psp mode 1 reset failed!\n"); 705 return -EINVAL; 706 } 707 708 DRM_INFO("psp mode1 reset succeed \n"); 709 710 return 0; 711 } 712 713 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready. 714 * For now, return success and hack the hive_id so high level code can 715 * start testing 716 */ 717 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp, 718 int number_devices, struct psp_xgmi_topology_info *topology) 719 { 720 struct ta_xgmi_shared_memory *xgmi_cmd; 721 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 722 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 723 int i; 724 int ret; 725 726 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 727 return -EINVAL; 728 729 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 730 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 731 732 /* Fill in the shared memory with topology information as input */ 733 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 734 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 735 topology_info_input->num_nodes = number_devices; 736 737 for (i = 0; i < topology_info_input->num_nodes; i++) { 738 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 739 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 740 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 741 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 742 } 743 744 /* Invoke xgmi ta to get the topology information */ 745 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 746 if (ret) 747 return ret; 748 749 /* Read the output topology information from the shared memory */ 750 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 751 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 752 for (i = 0; i < topology->num_nodes; i++) { 753 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 754 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 755 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 756 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 757 } 758 759 return 0; 760 } 761 762 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp, 763 int number_devices, struct psp_xgmi_topology_info *topology) 764 { 765 struct ta_xgmi_shared_memory *xgmi_cmd; 766 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 767 int i; 768 769 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 770 return -EINVAL; 771 772 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 773 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 774 775 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 776 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 777 topology_info_input->num_nodes = number_devices; 778 779 for (i = 0; i < topology_info_input->num_nodes; i++) { 780 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 781 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 782 topology_info_input->nodes[i].is_sharing_enabled = 1; 783 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 784 } 785 786 /* Invoke xgmi ta to set topology information */ 787 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 788 } 789 790 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 791 { 792 struct ta_xgmi_shared_memory *xgmi_cmd; 793 int ret; 794 795 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 796 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 797 798 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 799 800 /* Invoke xgmi ta to get hive id */ 801 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 802 if (ret) 803 return ret; 804 805 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 806 807 return 0; 808 } 809 810 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 811 { 812 struct ta_xgmi_shared_memory *xgmi_cmd; 813 int ret; 814 815 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 816 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 817 818 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 819 820 /* Invoke xgmi ta to get the node id */ 821 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 822 if (ret) 823 return ret; 824 825 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 826 827 return 0; 828 } 829 830 static int psp_v11_0_ras_trigger_error(struct psp_context *psp, 831 struct ta_ras_trigger_error_input *info) 832 { 833 struct ta_ras_shared_memory *ras_cmd; 834 int ret; 835 836 if (!psp->ras.ras_initialized) 837 return -EINVAL; 838 839 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 840 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 841 842 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 843 ras_cmd->ras_in_message.trigger_error = *info; 844 845 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 846 if (ret) 847 return -EINVAL; 848 849 return ras_cmd->ras_status; 850 } 851 852 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr) 853 { 854 #if 0 855 // not support yet. 856 struct ta_ras_shared_memory *ras_cmd; 857 int ret; 858 859 if (!psp->ras.ras_initialized) 860 return -EINVAL; 861 862 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 863 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 864 865 ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON; 866 ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr; 867 868 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 869 if (ret) 870 return -EINVAL; 871 872 return ras_cmd->ras_status; 873 #else 874 return -EINVAL; 875 #endif 876 } 877 878 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp) 879 { 880 return psp_rlc_autoload_start(psp); 881 } 882 883 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 884 { 885 int ret; 886 int i; 887 uint32_t data_32; 888 int max_wait; 889 struct amdgpu_device *adev = psp->adev; 890 891 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 892 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 893 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 894 895 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 896 for (i = 0; i < max_wait; i++) { 897 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 898 0x80000000, 0x80000000, false); 899 if (ret == 0) 900 break; 901 } 902 if (i < max_wait) 903 ret = 0; 904 else 905 ret = -ETIME; 906 907 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 908 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 909 (ret == 0) ? "succeed" : "failed", 910 i, adev->usec_timeout/1000); 911 return ret; 912 } 913 914 static void psp_v11_0_memory_training_fini(struct psp_context *psp) 915 { 916 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 917 918 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 919 kfree(ctx->sys_cache); 920 ctx->sys_cache = NULL; 921 } 922 923 static int psp_v11_0_memory_training_init(struct psp_context *psp) 924 { 925 int ret; 926 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 927 928 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 929 DRM_DEBUG("memory training is not supported!\n"); 930 return 0; 931 } 932 933 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 934 if (ctx->sys_cache == NULL) { 935 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 936 ret = -ENOMEM; 937 goto Err_out; 938 } 939 940 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 941 ctx->train_data_size, 942 ctx->p2c_train_data_offset, 943 ctx->c2p_train_data_offset); 944 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 945 return 0; 946 947 Err_out: 948 psp_v11_0_memory_training_fini(psp); 949 return ret; 950 } 951 952 /* 953 * save and restore proces 954 */ 955 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 956 { 957 int ret; 958 uint32_t p2c_header[4]; 959 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 960 uint32_t *pcache = (uint32_t*)ctx->sys_cache; 961 962 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 963 DRM_DEBUG("Memory training is not supported.\n"); 964 return 0; 965 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 966 DRM_ERROR("Memory training initialization failure.\n"); 967 return -EINVAL; 968 } 969 970 if (psp_v11_0_is_sos_alive(psp)) { 971 DRM_DEBUG("SOS is alive, skip memory training.\n"); 972 return 0; 973 } 974 975 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 976 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 977 pcache[0], pcache[1], pcache[2], pcache[3], 978 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 979 980 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 981 DRM_DEBUG("Short training depends on restore.\n"); 982 ops |= PSP_MEM_TRAIN_RESTORE; 983 } 984 985 if ((ops & PSP_MEM_TRAIN_RESTORE) && 986 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 987 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 988 ops |= PSP_MEM_TRAIN_SAVE; 989 } 990 991 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 992 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 993 pcache[3] == p2c_header[3])) { 994 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 995 ops |= PSP_MEM_TRAIN_SAVE; 996 } 997 998 if ((ops & PSP_MEM_TRAIN_SAVE) && 999 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 1000 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 1001 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 1002 } 1003 1004 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 1005 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 1006 ops |= PSP_MEM_TRAIN_SAVE; 1007 } 1008 1009 DRM_DEBUG("Memory training ops:%x.\n", ops); 1010 1011 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 1012 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 1013 if (ret) { 1014 DRM_ERROR("Send long training msg failed.\n"); 1015 return ret; 1016 } 1017 } 1018 1019 if (ops & PSP_MEM_TRAIN_SAVE) { 1020 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 1021 } 1022 1023 if (ops & PSP_MEM_TRAIN_RESTORE) { 1024 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 1025 } 1026 1027 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 1028 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 1029 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 1030 if (ret) { 1031 DRM_ERROR("send training msg failed.\n"); 1032 return ret; 1033 } 1034 } 1035 ctx->training_cnt++; 1036 return 0; 1037 } 1038 1039 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 1040 { 1041 uint32_t data; 1042 struct amdgpu_device *adev = psp->adev; 1043 1044 if (psp_v11_0_support_vmr_ring(psp)) 1045 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 1046 else 1047 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 1048 1049 return data; 1050 } 1051 1052 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 1053 { 1054 struct amdgpu_device *adev = psp->adev; 1055 1056 if (psp_v11_0_support_vmr_ring(psp)) { 1057 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 1058 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 1059 } else 1060 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 1061 } 1062 1063 static const struct psp_funcs psp_v11_0_funcs = { 1064 .init_microcode = psp_v11_0_init_microcode, 1065 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 1066 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 1067 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 1068 .ring_init = psp_v11_0_ring_init, 1069 .ring_create = psp_v11_0_ring_create, 1070 .ring_stop = psp_v11_0_ring_stop, 1071 .ring_destroy = psp_v11_0_ring_destroy, 1072 .compare_sram_data = psp_v11_0_compare_sram_data, 1073 .mode1_reset = psp_v11_0_mode1_reset, 1074 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info, 1075 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info, 1076 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id, 1077 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id, 1078 .support_vmr_ring = psp_v11_0_support_vmr_ring, 1079 .ras_trigger_error = psp_v11_0_ras_trigger_error, 1080 .ras_cure_posion = psp_v11_0_ras_cure_posion, 1081 .rlc_autoload_start = psp_v11_0_rlc_autoload_start, 1082 .mem_training_init = psp_v11_0_memory_training_init, 1083 .mem_training_fini = psp_v11_0_memory_training_fini, 1084 .mem_training = psp_v11_0_memory_training, 1085 .ring_get_wptr = psp_v11_0_ring_get_wptr, 1086 .ring_set_wptr = psp_v11_0_ring_set_wptr, 1087 }; 1088 1089 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 1090 { 1091 psp->funcs = &psp_v11_0_funcs; 1092 } 1093