1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "amdgpu_psp.h" 26 #include "amdgpu_ucode.h" 27 #include "soc15_common.h" 28 #include "psp_v11_0.h" 29 30 #include "mp/mp_11_0_offset.h" 31 #include "mp/mp_11_0_sh_mask.h" 32 #include "gc/gc_9_0_offset.h" 33 #include "sdma0/sdma0_4_0_offset.h" 34 #include "nbio/nbio_7_4_offset.h" 35 36 #include "oss/osssys_4_0_offset.h" 37 #include "oss/osssys_4_0_sh_mask.h" 38 39 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 40 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 41 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 42 43 /* address block */ 44 #define smnMP1_FIRMWARE_FLAGS 0x3010024 45 46 static int psp_v11_0_init_microcode(struct psp_context *psp) 47 { 48 struct amdgpu_device *adev = psp->adev; 49 const char *chip_name; 50 char fw_name[30]; 51 int err = 0; 52 const struct psp_firmware_header_v1_0 *sos_hdr; 53 const struct psp_firmware_header_v1_0 *asd_hdr; 54 const struct ta_firmware_header_v1_0 *ta_hdr; 55 56 DRM_DEBUG("\n"); 57 58 switch (adev->asic_type) { 59 case CHIP_VEGA20: 60 chip_name = "vega20"; 61 break; 62 default: 63 BUG(); 64 } 65 66 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 67 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 68 if (err) 69 goto out; 70 71 err = amdgpu_ucode_validate(adev->psp.sos_fw); 72 if (err) 73 goto out; 74 75 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 76 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 77 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 78 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 79 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->header.ucode_size_bytes) - 80 le32_to_cpu(sos_hdr->sos_size_bytes); 81 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 82 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 83 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 84 le32_to_cpu(sos_hdr->sos_offset_bytes); 85 86 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 87 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 88 if (err) 89 goto out1; 90 91 err = amdgpu_ucode_validate(adev->psp.asd_fw); 92 if (err) 93 goto out1; 94 95 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 96 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 97 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 98 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 99 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 100 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 101 102 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 103 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 104 if (err) { 105 release_firmware(adev->psp.ta_fw); 106 adev->psp.ta_fw = NULL; 107 dev_info(adev->dev, 108 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 109 } else { 110 err = amdgpu_ucode_validate(adev->psp.ta_fw); 111 if (err) 112 goto out2; 113 114 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 115 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 116 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 117 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 118 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 119 120 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 121 122 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); 123 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); 124 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + 125 le32_to_cpu(ta_hdr->ta_ras_offset_bytes); 126 } 127 128 return 0; 129 130 out2: 131 release_firmware(adev->psp.ta_fw); 132 adev->psp.ta_fw = NULL; 133 out1: 134 release_firmware(adev->psp.asd_fw); 135 adev->psp.asd_fw = NULL; 136 out: 137 dev_err(adev->dev, 138 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 139 release_firmware(adev->psp.sos_fw); 140 adev->psp.sos_fw = NULL; 141 142 return err; 143 } 144 145 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 146 { 147 int ret; 148 uint32_t psp_gfxdrv_command_reg = 0; 149 struct amdgpu_device *adev = psp->adev; 150 uint32_t sol_reg; 151 152 /* Check sOS sign of life register to confirm sys driver and sOS 153 * are already been loaded. 154 */ 155 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 156 if (sol_reg) { 157 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 158 printk("sos fw version = 0x%x.\n", psp->sos_fw_version); 159 return 0; 160 } 161 162 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 163 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 164 0x80000000, 0x80000000, false); 165 if (ret) 166 return ret; 167 168 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 169 170 /* Copy PSP System Driver binary to memory */ 171 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 172 173 /* Provide the sys driver to bootloader */ 174 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 175 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 176 psp_gfxdrv_command_reg = 1 << 16; 177 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 178 psp_gfxdrv_command_reg); 179 180 /* there might be handshake issue with hardware which needs delay */ 181 mdelay(20); 182 183 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 184 0x80000000, 0x80000000, false); 185 186 return ret; 187 } 188 189 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 190 { 191 int ret; 192 unsigned int psp_gfxdrv_command_reg = 0; 193 struct amdgpu_device *adev = psp->adev; 194 uint32_t sol_reg; 195 196 /* Check sOS sign of life register to confirm sys driver and sOS 197 * are already been loaded. 198 */ 199 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 200 if (sol_reg) 201 return 0; 202 203 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 204 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 205 0x80000000, 0x80000000, false); 206 if (ret) 207 return ret; 208 209 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 210 211 /* Copy Secure OS binary to PSP memory */ 212 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 213 214 /* Provide the PSP secure OS to bootloader */ 215 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 216 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 217 psp_gfxdrv_command_reg = 2 << 16; 218 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 219 psp_gfxdrv_command_reg); 220 221 /* there might be handshake issue with hardware which needs delay */ 222 mdelay(20); 223 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 224 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 225 0, true); 226 227 return ret; 228 } 229 230 static void psp_v11_0_reroute_ih(struct psp_context *psp) 231 { 232 struct amdgpu_device *adev = psp->adev; 233 uint32_t tmp; 234 235 /* Change IH ring for VMC */ 236 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 237 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 238 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 239 240 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 241 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 242 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 243 244 mdelay(20); 245 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 246 0x80000000, 0x8000FFFF, false); 247 248 /* Change IH ring for UMC */ 249 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 250 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 251 252 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 253 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 254 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 255 256 mdelay(20); 257 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 258 0x80000000, 0x8000FFFF, false); 259 } 260 261 static int psp_v11_0_ring_init(struct psp_context *psp, 262 enum psp_ring_type ring_type) 263 { 264 int ret = 0; 265 struct psp_ring *ring; 266 struct amdgpu_device *adev = psp->adev; 267 268 psp_v11_0_reroute_ih(psp); 269 270 ring = &psp->km_ring; 271 272 ring->ring_type = ring_type; 273 274 /* allocate 4k Page of Local Frame Buffer memory for ring */ 275 ring->ring_size = 0x1000; 276 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 277 AMDGPU_GEM_DOMAIN_VRAM, 278 &adev->firmware.rbuf, 279 &ring->ring_mem_mc_addr, 280 (void **)&ring->ring_mem); 281 if (ret) { 282 ring->ring_size = 0; 283 return ret; 284 } 285 286 return 0; 287 } 288 289 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp) 290 { 291 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045) 292 return true; 293 return false; 294 } 295 296 static int psp_v11_0_ring_create(struct psp_context *psp, 297 enum psp_ring_type ring_type) 298 { 299 int ret = 0; 300 unsigned int psp_ring_reg = 0; 301 struct psp_ring *ring = &psp->km_ring; 302 struct amdgpu_device *adev = psp->adev; 303 304 if (psp_v11_0_support_vmr_ring(psp)) { 305 /* Write low address of the ring to C2PMSG_102 */ 306 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 307 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 308 /* Write high address of the ring to C2PMSG_103 */ 309 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 310 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 311 312 /* Write the ring initialization command to C2PMSG_101 */ 313 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 314 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 315 316 /* there might be handshake issue with hardware which needs delay */ 317 mdelay(20); 318 319 /* Wait for response flag (bit 31) in C2PMSG_101 */ 320 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 321 0x80000000, 0x8000FFFF, false); 322 323 } else { 324 /* Write low address of the ring to C2PMSG_69 */ 325 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 326 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 327 /* Write high address of the ring to C2PMSG_70 */ 328 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 329 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 330 /* Write size of ring to C2PMSG_71 */ 331 psp_ring_reg = ring->ring_size; 332 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 333 /* Write the ring initialization command to C2PMSG_64 */ 334 psp_ring_reg = ring_type; 335 psp_ring_reg = psp_ring_reg << 16; 336 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 337 338 /* there might be handshake issue with hardware which needs delay */ 339 mdelay(20); 340 341 /* Wait for response flag (bit 31) in C2PMSG_64 */ 342 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 343 0x80000000, 0x8000FFFF, false); 344 } 345 346 return ret; 347 } 348 349 static int psp_v11_0_ring_stop(struct psp_context *psp, 350 enum psp_ring_type ring_type) 351 { 352 int ret = 0; 353 struct amdgpu_device *adev = psp->adev; 354 355 /* Write the ring destroy command*/ 356 if (psp_v11_0_support_vmr_ring(psp)) 357 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 358 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 359 else 360 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 361 GFX_CTRL_CMD_ID_DESTROY_RINGS); 362 363 /* there might be handshake issue with hardware which needs delay */ 364 mdelay(20); 365 366 /* Wait for response flag (bit 31) */ 367 if (psp_v11_0_support_vmr_ring(psp)) 368 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 369 0x80000000, 0x80000000, false); 370 else 371 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 372 0x80000000, 0x80000000, false); 373 374 return ret; 375 } 376 377 static int psp_v11_0_ring_destroy(struct psp_context *psp, 378 enum psp_ring_type ring_type) 379 { 380 int ret = 0; 381 struct psp_ring *ring = &psp->km_ring; 382 struct amdgpu_device *adev = psp->adev; 383 384 ret = psp_v11_0_ring_stop(psp, ring_type); 385 if (ret) 386 DRM_ERROR("Fail to stop psp ring\n"); 387 388 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 389 &ring->ring_mem_mc_addr, 390 (void **)&ring->ring_mem); 391 392 return ret; 393 } 394 395 static int psp_v11_0_cmd_submit(struct psp_context *psp, 396 struct amdgpu_firmware_info *ucode, 397 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 398 int index) 399 { 400 unsigned int psp_write_ptr_reg = 0; 401 struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem; 402 struct psp_ring *ring = &psp->km_ring; 403 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 404 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 405 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 406 struct amdgpu_device *adev = psp->adev; 407 uint32_t ring_size_dw = ring->ring_size / 4; 408 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 409 410 /* KM (GPCOM) prepare write pointer */ 411 if (psp_v11_0_support_vmr_ring(psp)) 412 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 413 else 414 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 415 416 /* Update KM RB frame pointer to new frame */ 417 /* write_frame ptr increments by size of rb_frame in bytes */ 418 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 419 if ((psp_write_ptr_reg % ring_size_dw) == 0) 420 write_frame = ring_buffer_start; 421 else 422 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 423 /* Check invalid write_frame ptr address */ 424 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 425 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 426 ring_buffer_start, ring_buffer_end, write_frame); 427 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 428 return -EINVAL; 429 } 430 431 /* Initialize KM RB frame */ 432 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 433 434 /* Update KM RB frame */ 435 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 436 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 437 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 438 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 439 write_frame->fence_value = index; 440 441 /* Update the write Pointer in DWORDs */ 442 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 443 if (psp_v11_0_support_vmr_ring(psp)) { 444 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg); 445 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 446 } else 447 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 448 449 return 0; 450 } 451 452 static int 453 psp_v11_0_sram_map(struct amdgpu_device *adev, 454 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 455 unsigned int *sram_data_reg_offset, 456 enum AMDGPU_UCODE_ID ucode_id) 457 { 458 int ret = 0; 459 460 switch (ucode_id) { 461 /* TODO: needs to confirm */ 462 #if 0 463 case AMDGPU_UCODE_ID_SMC: 464 *sram_offset = 0; 465 *sram_addr_reg_offset = 0; 466 *sram_data_reg_offset = 0; 467 break; 468 #endif 469 470 case AMDGPU_UCODE_ID_CP_CE: 471 *sram_offset = 0x0; 472 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 473 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 474 break; 475 476 case AMDGPU_UCODE_ID_CP_PFP: 477 *sram_offset = 0x0; 478 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 479 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 480 break; 481 482 case AMDGPU_UCODE_ID_CP_ME: 483 *sram_offset = 0x0; 484 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 485 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 486 break; 487 488 case AMDGPU_UCODE_ID_CP_MEC1: 489 *sram_offset = 0x10000; 490 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 491 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 492 break; 493 494 case AMDGPU_UCODE_ID_CP_MEC2: 495 *sram_offset = 0x10000; 496 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 497 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 498 break; 499 500 case AMDGPU_UCODE_ID_RLC_G: 501 *sram_offset = 0x2000; 502 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 503 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 504 break; 505 506 case AMDGPU_UCODE_ID_SDMA0: 507 *sram_offset = 0x0; 508 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 509 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 510 break; 511 512 /* TODO: needs to confirm */ 513 #if 0 514 case AMDGPU_UCODE_ID_SDMA1: 515 *sram_offset = ; 516 *sram_addr_reg_offset = ; 517 break; 518 519 case AMDGPU_UCODE_ID_UVD: 520 *sram_offset = ; 521 *sram_addr_reg_offset = ; 522 break; 523 524 case AMDGPU_UCODE_ID_VCE: 525 *sram_offset = ; 526 *sram_addr_reg_offset = ; 527 break; 528 #endif 529 530 case AMDGPU_UCODE_ID_MAXIMUM: 531 default: 532 ret = -EINVAL; 533 break; 534 } 535 536 return ret; 537 } 538 539 static bool psp_v11_0_compare_sram_data(struct psp_context *psp, 540 struct amdgpu_firmware_info *ucode, 541 enum AMDGPU_UCODE_ID ucode_type) 542 { 543 int err = 0; 544 unsigned int fw_sram_reg_val = 0; 545 unsigned int fw_sram_addr_reg_offset = 0; 546 unsigned int fw_sram_data_reg_offset = 0; 547 unsigned int ucode_size; 548 uint32_t *ucode_mem = NULL; 549 struct amdgpu_device *adev = psp->adev; 550 551 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 552 &fw_sram_data_reg_offset, ucode_type); 553 if (err) 554 return false; 555 556 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 557 558 ucode_size = ucode->ucode_size; 559 ucode_mem = (uint32_t *)ucode->kaddr; 560 while (ucode_size) { 561 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 562 563 if (*ucode_mem != fw_sram_reg_val) 564 return false; 565 566 ucode_mem++; 567 /* 4 bytes */ 568 ucode_size -= 4; 569 } 570 571 return true; 572 } 573 574 static int psp_v11_0_mode1_reset(struct psp_context *psp) 575 { 576 int ret; 577 uint32_t offset; 578 struct amdgpu_device *adev = psp->adev; 579 580 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 581 582 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 583 584 if (ret) { 585 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 586 return -EINVAL; 587 } 588 589 /*send the mode 1 reset command*/ 590 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 591 592 msleep(500); 593 594 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 595 596 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 597 598 if (ret) { 599 DRM_INFO("psp mode 1 reset failed!\n"); 600 return -EINVAL; 601 } 602 603 DRM_INFO("psp mode1 reset succeed \n"); 604 605 return 0; 606 } 607 608 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready. 609 * For now, return success and hack the hive_id so high level code can 610 * start testing 611 */ 612 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp, 613 int number_devices, struct psp_xgmi_topology_info *topology) 614 { 615 struct ta_xgmi_shared_memory *xgmi_cmd; 616 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 617 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 618 int i; 619 int ret; 620 621 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 622 return -EINVAL; 623 624 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 625 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 626 627 /* Fill in the shared memory with topology information as input */ 628 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 629 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 630 topology_info_input->num_nodes = number_devices; 631 632 for (i = 0; i < topology_info_input->num_nodes; i++) { 633 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 634 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 635 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 636 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 637 } 638 639 /* Invoke xgmi ta to get the topology information */ 640 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 641 if (ret) 642 return ret; 643 644 /* Read the output topology information from the shared memory */ 645 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 646 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 647 for (i = 0; i < topology->num_nodes; i++) { 648 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 649 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 650 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 651 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 652 } 653 654 return 0; 655 } 656 657 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp, 658 int number_devices, struct psp_xgmi_topology_info *topology) 659 { 660 struct ta_xgmi_shared_memory *xgmi_cmd; 661 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 662 int i; 663 664 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 665 return -EINVAL; 666 667 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 668 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 669 670 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 671 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 672 topology_info_input->num_nodes = number_devices; 673 674 for (i = 0; i < topology_info_input->num_nodes; i++) { 675 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 676 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 677 topology_info_input->nodes[i].is_sharing_enabled = 1; 678 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 679 } 680 681 /* Invoke xgmi ta to set topology information */ 682 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 683 } 684 685 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 686 { 687 struct ta_xgmi_shared_memory *xgmi_cmd; 688 int ret; 689 690 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 691 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 692 693 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 694 695 /* Invoke xgmi ta to get hive id */ 696 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 697 if (ret) 698 return ret; 699 700 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 701 702 return 0; 703 } 704 705 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 706 { 707 struct ta_xgmi_shared_memory *xgmi_cmd; 708 int ret; 709 710 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 711 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 712 713 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 714 715 /* Invoke xgmi ta to get the node id */ 716 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 717 if (ret) 718 return ret; 719 720 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 721 722 return 0; 723 } 724 725 static int psp_v11_0_ras_trigger_error(struct psp_context *psp, 726 struct ta_ras_trigger_error_input *info) 727 { 728 struct ta_ras_shared_memory *ras_cmd; 729 int ret; 730 731 if (!psp->ras.ras_initialized) 732 return -EINVAL; 733 734 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 735 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 736 737 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 738 ras_cmd->ras_in_message.trigger_error = *info; 739 740 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 741 if (ret) 742 return -EINVAL; 743 744 return ras_cmd->ras_status; 745 } 746 747 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr) 748 { 749 #if 0 750 // not support yet. 751 struct ta_ras_shared_memory *ras_cmd; 752 int ret; 753 754 if (!psp->ras.ras_initialized) 755 return -EINVAL; 756 757 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 758 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 759 760 ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON; 761 ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr; 762 763 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 764 if (ret) 765 return -EINVAL; 766 767 return ras_cmd->ras_status; 768 #else 769 return -EINVAL; 770 #endif 771 } 772 773 static const struct psp_funcs psp_v11_0_funcs = { 774 .init_microcode = psp_v11_0_init_microcode, 775 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 776 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 777 .ring_init = psp_v11_0_ring_init, 778 .ring_create = psp_v11_0_ring_create, 779 .ring_stop = psp_v11_0_ring_stop, 780 .ring_destroy = psp_v11_0_ring_destroy, 781 .cmd_submit = psp_v11_0_cmd_submit, 782 .compare_sram_data = psp_v11_0_compare_sram_data, 783 .mode1_reset = psp_v11_0_mode1_reset, 784 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info, 785 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info, 786 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id, 787 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id, 788 .support_vmr_ring = psp_v11_0_support_vmr_ring, 789 .ras_trigger_error = psp_v11_0_ras_trigger_error, 790 .ras_cure_posion = psp_v11_0_ras_cure_posion, 791 }; 792 793 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 794 { 795 psp->funcs = &psp_v11_0_funcs; 796 } 797