1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/vmalloc.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_psp.h" 29 #include "amdgpu_ucode.h" 30 #include "soc15_common.h" 31 #include "psp_v11_0.h" 32 33 #include "mp/mp_11_0_offset.h" 34 #include "mp/mp_11_0_sh_mask.h" 35 #include "gc/gc_9_0_offset.h" 36 #include "sdma0/sdma0_4_0_offset.h" 37 #include "nbio/nbio_7_4_offset.h" 38 39 #include "oss/osssys_4_0_offset.h" 40 #include "oss/osssys_4_0_sh_mask.h" 41 42 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 43 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 44 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 45 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 47 MODULE_FIRMWARE("amdgpu/navi10_ta.bin"); 48 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 50 MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); 51 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 53 MODULE_FIRMWARE("amdgpu/navi12_ta.bin"); 54 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 55 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 56 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 57 58 /* address block */ 59 #define smnMP1_FIRMWARE_FLAGS 0x3010024 60 /* navi10 reg offset define */ 61 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 62 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 63 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 64 #define mmSDMA0_UCODE_DATA_NV10 0x5881 65 /* memory training timeout define */ 66 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 67 68 /* For large FW files the time to complete can be very long */ 69 #define USBC_PD_POLLING_LIMIT_S 240 70 71 static int psp_v11_0_init_microcode(struct psp_context *psp) 72 { 73 struct amdgpu_device *adev = psp->adev; 74 const char *chip_name; 75 char fw_name[30]; 76 int err = 0; 77 const struct psp_firmware_header_v1_0 *sos_hdr; 78 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 79 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 80 const struct psp_firmware_header_v1_0 *asd_hdr; 81 const struct ta_firmware_header_v1_0 *ta_hdr; 82 83 DRM_DEBUG("\n"); 84 85 switch (adev->asic_type) { 86 case CHIP_VEGA20: 87 chip_name = "vega20"; 88 break; 89 case CHIP_NAVI10: 90 chip_name = "navi10"; 91 break; 92 case CHIP_NAVI14: 93 chip_name = "navi14"; 94 break; 95 case CHIP_NAVI12: 96 chip_name = "navi12"; 97 break; 98 case CHIP_ARCTURUS: 99 chip_name = "arcturus"; 100 break; 101 default: 102 BUG(); 103 } 104 105 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 106 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 107 if (err) 108 goto out; 109 110 err = amdgpu_ucode_validate(adev->psp.sos_fw); 111 if (err) 112 goto out; 113 114 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 115 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 116 117 switch (sos_hdr->header.header_version_major) { 118 case 1: 119 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 120 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version); 121 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes); 122 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes); 123 adev->psp.sys_start_addr = (uint8_t *)sos_hdr + 124 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 125 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 126 le32_to_cpu(sos_hdr->sos_offset_bytes); 127 if (sos_hdr->header.header_version_minor == 1) { 128 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 129 adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes); 130 adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr + 131 le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes); 132 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes); 133 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 134 le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes); 135 } 136 if (sos_hdr->header.header_version_minor == 2) { 137 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 138 adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes); 139 adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr + 140 le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes); 141 } 142 break; 143 default: 144 dev_err(adev->dev, 145 "Unsupported psp sos firmware\n"); 146 err = -EINVAL; 147 goto out; 148 } 149 150 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 151 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 152 if (err) 153 goto out1; 154 155 err = amdgpu_ucode_validate(adev->psp.asd_fw); 156 if (err) 157 goto out1; 158 159 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 160 adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 161 adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version); 162 adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 163 adev->psp.asd_start_addr = (uint8_t *)asd_hdr + 164 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 165 166 switch (adev->asic_type) { 167 case CHIP_VEGA20: 168 case CHIP_ARCTURUS: 169 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 170 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 171 if (err) { 172 release_firmware(adev->psp.ta_fw); 173 adev->psp.ta_fw = NULL; 174 dev_info(adev->dev, 175 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 176 } else { 177 err = amdgpu_ucode_validate(adev->psp.ta_fw); 178 if (err) 179 goto out2; 180 181 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 182 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 183 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 184 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 185 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 186 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 187 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); 188 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); 189 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + 190 le32_to_cpu(ta_hdr->ta_ras_offset_bytes); 191 } 192 break; 193 case CHIP_NAVI10: 194 case CHIP_NAVI14: 195 case CHIP_NAVI12: 196 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 197 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 198 if (err) { 199 release_firmware(adev->psp.ta_fw); 200 adev->psp.ta_fw = NULL; 201 dev_info(adev->dev, 202 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 203 } else { 204 err = amdgpu_ucode_validate(adev->psp.ta_fw); 205 if (err) 206 goto out2; 207 208 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 209 adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 210 adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 211 adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr + 212 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 213 214 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 215 216 adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 217 adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 218 adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr + 219 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 220 } 221 break; 222 default: 223 BUG(); 224 } 225 226 return 0; 227 228 out2: 229 release_firmware(adev->psp.ta_fw); 230 adev->psp.ta_fw = NULL; 231 out1: 232 release_firmware(adev->psp.asd_fw); 233 adev->psp.asd_fw = NULL; 234 out: 235 dev_err(adev->dev, 236 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 237 release_firmware(adev->psp.sos_fw); 238 adev->psp.sos_fw = NULL; 239 240 return err; 241 } 242 243 int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 244 { 245 struct amdgpu_device *adev = psp->adev; 246 247 int ret; 248 int retry_loop; 249 250 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 251 /* Wait for bootloader to signify that is 252 ready having bit 31 of C2PMSG_35 set to 1 */ 253 ret = psp_wait_for(psp, 254 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 255 0x80000000, 256 0x80000000, 257 false); 258 259 if (ret == 0) 260 return 0; 261 } 262 263 return ret; 264 } 265 266 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 267 { 268 struct amdgpu_device *adev = psp->adev; 269 uint32_t sol_reg; 270 271 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 272 273 return sol_reg != 0x0; 274 } 275 276 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 277 { 278 int ret; 279 uint32_t psp_gfxdrv_command_reg = 0; 280 struct amdgpu_device *adev = psp->adev; 281 282 /* Check tOS sign of life register to confirm sys driver and sOS 283 * are already been loaded. 284 */ 285 if (psp_v11_0_is_sos_alive(psp)) { 286 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 287 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version); 288 return 0; 289 } 290 291 ret = psp_v11_0_wait_for_bootloader(psp); 292 if (ret) 293 return ret; 294 295 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 296 297 /* Copy PSP KDB binary to memory */ 298 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); 299 300 /* Provide the PSP KDB to bootloader */ 301 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 302 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 303 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; 304 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 305 psp_gfxdrv_command_reg); 306 307 ret = psp_v11_0_wait_for_bootloader(psp); 308 309 return ret; 310 } 311 312 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 313 { 314 int ret; 315 uint32_t psp_gfxdrv_command_reg = 0; 316 struct amdgpu_device *adev = psp->adev; 317 318 /* Check sOS sign of life register to confirm sys driver and sOS 319 * are already been loaded. 320 */ 321 if (psp_v11_0_is_sos_alive(psp)) { 322 psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 323 dev_info(adev->dev, "sos fw version = 0x%x.\n", psp->sos_fw_version); 324 return 0; 325 } 326 327 ret = psp_v11_0_wait_for_bootloader(psp); 328 if (ret) 329 return ret; 330 331 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 332 333 /* Copy PSP System Driver binary to memory */ 334 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 335 336 /* Provide the sys driver to bootloader */ 337 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 338 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 339 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 340 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 341 psp_gfxdrv_command_reg); 342 343 /* there might be handshake issue with hardware which needs delay */ 344 mdelay(20); 345 346 ret = psp_v11_0_wait_for_bootloader(psp); 347 348 return ret; 349 } 350 351 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 352 { 353 int ret; 354 unsigned int psp_gfxdrv_command_reg = 0; 355 struct amdgpu_device *adev = psp->adev; 356 357 /* Check sOS sign of life register to confirm sys driver and sOS 358 * are already been loaded. 359 */ 360 if (psp_v11_0_is_sos_alive(psp)) 361 return 0; 362 363 ret = psp_v11_0_wait_for_bootloader(psp); 364 if (ret) 365 return ret; 366 367 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 368 369 /* Copy Secure OS binary to PSP memory */ 370 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 371 372 /* Provide the PSP secure OS to bootloader */ 373 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 374 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 375 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 376 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 377 psp_gfxdrv_command_reg); 378 379 /* there might be handshake issue with hardware which needs delay */ 380 mdelay(20); 381 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 382 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 383 0, true); 384 385 return ret; 386 } 387 388 static void psp_v11_0_reroute_ih(struct psp_context *psp) 389 { 390 struct amdgpu_device *adev = psp->adev; 391 uint32_t tmp; 392 393 /* Change IH ring for VMC */ 394 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 395 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 396 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 397 398 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 399 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 400 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 401 402 mdelay(20); 403 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 404 0x80000000, 0x8000FFFF, false); 405 406 /* Change IH ring for UMC */ 407 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 408 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 409 410 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 411 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 412 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 413 414 mdelay(20); 415 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 416 0x80000000, 0x8000FFFF, false); 417 } 418 419 static int psp_v11_0_ring_init(struct psp_context *psp, 420 enum psp_ring_type ring_type) 421 { 422 int ret = 0; 423 struct psp_ring *ring; 424 struct amdgpu_device *adev = psp->adev; 425 426 if (!amdgpu_sriov_vf(adev)) 427 psp_v11_0_reroute_ih(psp); 428 429 ring = &psp->km_ring; 430 431 ring->ring_type = ring_type; 432 433 /* allocate 4k Page of Local Frame Buffer memory for ring */ 434 ring->ring_size = 0x1000; 435 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 436 AMDGPU_GEM_DOMAIN_VRAM, 437 &adev->firmware.rbuf, 438 &ring->ring_mem_mc_addr, 439 (void **)&ring->ring_mem); 440 if (ret) { 441 ring->ring_size = 0; 442 return ret; 443 } 444 445 return 0; 446 } 447 448 static bool psp_v11_0_support_vmr_ring(struct psp_context *psp) 449 { 450 if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045) 451 return true; 452 return false; 453 } 454 455 static int psp_v11_0_ring_stop(struct psp_context *psp, 456 enum psp_ring_type ring_type) 457 { 458 int ret = 0; 459 struct amdgpu_device *adev = psp->adev; 460 461 /* Write the ring destroy command*/ 462 if (psp_v11_0_support_vmr_ring(psp)) 463 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 464 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 465 else 466 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 467 GFX_CTRL_CMD_ID_DESTROY_RINGS); 468 469 /* there might be handshake issue with hardware which needs delay */ 470 mdelay(20); 471 472 /* Wait for response flag (bit 31) */ 473 if (psp_v11_0_support_vmr_ring(psp)) 474 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 475 0x80000000, 0x80000000, false); 476 else 477 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 478 0x80000000, 0x80000000, false); 479 480 return ret; 481 } 482 483 static int psp_v11_0_ring_create(struct psp_context *psp, 484 enum psp_ring_type ring_type) 485 { 486 int ret = 0; 487 unsigned int psp_ring_reg = 0; 488 struct psp_ring *ring = &psp->km_ring; 489 struct amdgpu_device *adev = psp->adev; 490 491 if (psp_v11_0_support_vmr_ring(psp)) { 492 ret = psp_v11_0_ring_stop(psp, ring_type); 493 if (ret) { 494 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 495 return ret; 496 } 497 498 /* Write low address of the ring to C2PMSG_102 */ 499 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 500 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 501 /* Write high address of the ring to C2PMSG_103 */ 502 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 503 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 504 505 /* Write the ring initialization command to C2PMSG_101 */ 506 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 507 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 508 509 /* there might be handshake issue with hardware which needs delay */ 510 mdelay(20); 511 512 /* Wait for response flag (bit 31) in C2PMSG_101 */ 513 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 514 0x80000000, 0x8000FFFF, false); 515 516 } else { 517 /* Wait for sOS ready for ring creation */ 518 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 519 0x80000000, 0x80000000, false); 520 if (ret) { 521 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 522 return ret; 523 } 524 525 /* Write low address of the ring to C2PMSG_69 */ 526 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 527 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 528 /* Write high address of the ring to C2PMSG_70 */ 529 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 530 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 531 /* Write size of ring to C2PMSG_71 */ 532 psp_ring_reg = ring->ring_size; 533 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 534 /* Write the ring initialization command to C2PMSG_64 */ 535 psp_ring_reg = ring_type; 536 psp_ring_reg = psp_ring_reg << 16; 537 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 538 539 /* there might be handshake issue with hardware which needs delay */ 540 mdelay(20); 541 542 /* Wait for response flag (bit 31) in C2PMSG_64 */ 543 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 544 0x80000000, 0x8000FFFF, false); 545 } 546 547 return ret; 548 } 549 550 551 static int psp_v11_0_ring_destroy(struct psp_context *psp, 552 enum psp_ring_type ring_type) 553 { 554 int ret = 0; 555 struct psp_ring *ring = &psp->km_ring; 556 struct amdgpu_device *adev = psp->adev; 557 558 ret = psp_v11_0_ring_stop(psp, ring_type); 559 if (ret) 560 DRM_ERROR("Fail to stop psp ring\n"); 561 562 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 563 &ring->ring_mem_mc_addr, 564 (void **)&ring->ring_mem); 565 566 return ret; 567 } 568 569 static int 570 psp_v11_0_sram_map(struct amdgpu_device *adev, 571 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 572 unsigned int *sram_data_reg_offset, 573 enum AMDGPU_UCODE_ID ucode_id) 574 { 575 int ret = 0; 576 577 switch (ucode_id) { 578 /* TODO: needs to confirm */ 579 #if 0 580 case AMDGPU_UCODE_ID_SMC: 581 *sram_offset = 0; 582 *sram_addr_reg_offset = 0; 583 *sram_data_reg_offset = 0; 584 break; 585 #endif 586 587 case AMDGPU_UCODE_ID_CP_CE: 588 *sram_offset = 0x0; 589 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 590 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 591 break; 592 593 case AMDGPU_UCODE_ID_CP_PFP: 594 *sram_offset = 0x0; 595 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 596 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 597 break; 598 599 case AMDGPU_UCODE_ID_CP_ME: 600 *sram_offset = 0x0; 601 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 602 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 603 break; 604 605 case AMDGPU_UCODE_ID_CP_MEC1: 606 *sram_offset = 0x10000; 607 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 608 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 609 break; 610 611 case AMDGPU_UCODE_ID_CP_MEC2: 612 *sram_offset = 0x10000; 613 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 614 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 615 break; 616 617 case AMDGPU_UCODE_ID_RLC_G: 618 *sram_offset = 0x2000; 619 if (adev->asic_type < CHIP_NAVI10) { 620 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 621 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 622 } else { 623 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10; 624 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10; 625 } 626 break; 627 628 case AMDGPU_UCODE_ID_SDMA0: 629 *sram_offset = 0x0; 630 if (adev->asic_type < CHIP_NAVI10) { 631 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 632 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 633 } else { 634 *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10; 635 *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10; 636 } 637 break; 638 639 /* TODO: needs to confirm */ 640 #if 0 641 case AMDGPU_UCODE_ID_SDMA1: 642 *sram_offset = ; 643 *sram_addr_reg_offset = ; 644 break; 645 646 case AMDGPU_UCODE_ID_UVD: 647 *sram_offset = ; 648 *sram_addr_reg_offset = ; 649 break; 650 651 case AMDGPU_UCODE_ID_VCE: 652 *sram_offset = ; 653 *sram_addr_reg_offset = ; 654 break; 655 #endif 656 657 case AMDGPU_UCODE_ID_MAXIMUM: 658 default: 659 ret = -EINVAL; 660 break; 661 } 662 663 return ret; 664 } 665 666 static bool psp_v11_0_compare_sram_data(struct psp_context *psp, 667 struct amdgpu_firmware_info *ucode, 668 enum AMDGPU_UCODE_ID ucode_type) 669 { 670 int err = 0; 671 unsigned int fw_sram_reg_val = 0; 672 unsigned int fw_sram_addr_reg_offset = 0; 673 unsigned int fw_sram_data_reg_offset = 0; 674 unsigned int ucode_size; 675 uint32_t *ucode_mem = NULL; 676 struct amdgpu_device *adev = psp->adev; 677 678 err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 679 &fw_sram_data_reg_offset, ucode_type); 680 if (err) 681 return false; 682 683 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 684 685 ucode_size = ucode->ucode_size; 686 ucode_mem = (uint32_t *)ucode->kaddr; 687 while (ucode_size) { 688 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 689 690 if (*ucode_mem != fw_sram_reg_val) 691 return false; 692 693 ucode_mem++; 694 /* 4 bytes */ 695 ucode_size -= 4; 696 } 697 698 return true; 699 } 700 701 static int psp_v11_0_mode1_reset(struct psp_context *psp) 702 { 703 int ret; 704 uint32_t offset; 705 struct amdgpu_device *adev = psp->adev; 706 707 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 708 709 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 710 711 if (ret) { 712 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 713 return -EINVAL; 714 } 715 716 /*send the mode 1 reset command*/ 717 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 718 719 msleep(500); 720 721 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 722 723 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 724 725 if (ret) { 726 DRM_INFO("psp mode 1 reset failed!\n"); 727 return -EINVAL; 728 } 729 730 DRM_INFO("psp mode1 reset succeed \n"); 731 732 return 0; 733 } 734 735 /* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready. 736 * For now, return success and hack the hive_id so high level code can 737 * start testing 738 */ 739 static int psp_v11_0_xgmi_get_topology_info(struct psp_context *psp, 740 int number_devices, struct psp_xgmi_topology_info *topology) 741 { 742 struct ta_xgmi_shared_memory *xgmi_cmd; 743 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 744 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 745 int i; 746 int ret; 747 748 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 749 return -EINVAL; 750 751 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 752 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 753 754 /* Fill in the shared memory with topology information as input */ 755 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 756 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 757 topology_info_input->num_nodes = number_devices; 758 759 for (i = 0; i < topology_info_input->num_nodes; i++) { 760 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 761 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 762 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 763 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 764 } 765 766 /* Invoke xgmi ta to get the topology information */ 767 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 768 if (ret) 769 return ret; 770 771 /* Read the output topology information from the shared memory */ 772 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 773 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 774 for (i = 0; i < topology->num_nodes; i++) { 775 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 776 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 777 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled; 778 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine; 779 } 780 781 return 0; 782 } 783 784 static int psp_v11_0_xgmi_set_topology_info(struct psp_context *psp, 785 int number_devices, struct psp_xgmi_topology_info *topology) 786 { 787 struct ta_xgmi_shared_memory *xgmi_cmd; 788 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 789 int i; 790 791 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 792 return -EINVAL; 793 794 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 795 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 796 797 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 798 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 799 topology_info_input->num_nodes = number_devices; 800 801 for (i = 0; i < topology_info_input->num_nodes; i++) { 802 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 803 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 804 topology_info_input->nodes[i].is_sharing_enabled = 1; 805 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 806 } 807 808 /* Invoke xgmi ta to set topology information */ 809 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 810 } 811 812 static int psp_v11_0_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 813 { 814 struct ta_xgmi_shared_memory *xgmi_cmd; 815 int ret; 816 817 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 818 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 819 820 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 821 822 /* Invoke xgmi ta to get hive id */ 823 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 824 if (ret) 825 return ret; 826 827 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 828 829 return 0; 830 } 831 832 static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 833 { 834 struct ta_xgmi_shared_memory *xgmi_cmd; 835 int ret; 836 837 xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf; 838 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 839 840 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 841 842 /* Invoke xgmi ta to get the node id */ 843 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 844 if (ret) 845 return ret; 846 847 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 848 849 return 0; 850 } 851 852 static int psp_v11_0_ras_trigger_error(struct psp_context *psp, 853 struct ta_ras_trigger_error_input *info) 854 { 855 struct ta_ras_shared_memory *ras_cmd; 856 int ret; 857 858 if (!psp->ras.ras_initialized) 859 return -EINVAL; 860 861 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 862 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 863 864 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 865 ras_cmd->ras_in_message.trigger_error = *info; 866 867 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 868 if (ret) 869 return -EINVAL; 870 871 return ras_cmd->ras_status; 872 } 873 874 static int psp_v11_0_ras_cure_posion(struct psp_context *psp, uint64_t *mode_ptr) 875 { 876 #if 0 877 // not support yet. 878 struct ta_ras_shared_memory *ras_cmd; 879 int ret; 880 881 if (!psp->ras.ras_initialized) 882 return -EINVAL; 883 884 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf; 885 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 886 887 ras_cmd->cmd_id = TA_RAS_COMMAND__CURE_POISON; 888 ras_cmd->ras_in_message.cure_poison.mode_ptr = mode_ptr; 889 890 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 891 if (ret) 892 return -EINVAL; 893 894 return ras_cmd->ras_status; 895 #else 896 return -EINVAL; 897 #endif 898 } 899 900 static int psp_v11_0_rlc_autoload_start(struct psp_context *psp) 901 { 902 return psp_rlc_autoload_start(psp); 903 } 904 905 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 906 { 907 int ret; 908 int i; 909 uint32_t data_32; 910 int max_wait; 911 struct amdgpu_device *adev = psp->adev; 912 913 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 914 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 915 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 916 917 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 918 for (i = 0; i < max_wait; i++) { 919 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 920 0x80000000, 0x80000000, false); 921 if (ret == 0) 922 break; 923 } 924 if (i < max_wait) 925 ret = 0; 926 else 927 ret = -ETIME; 928 929 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 930 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 931 (ret == 0) ? "succeed" : "failed", 932 i, adev->usec_timeout/1000); 933 return ret; 934 } 935 936 static void psp_v11_0_memory_training_fini(struct psp_context *psp) 937 { 938 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 939 940 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 941 kfree(ctx->sys_cache); 942 ctx->sys_cache = NULL; 943 } 944 945 static int psp_v11_0_memory_training_init(struct psp_context *psp) 946 { 947 int ret; 948 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 949 950 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 951 DRM_DEBUG("memory training is not supported!\n"); 952 return 0; 953 } 954 955 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 956 if (ctx->sys_cache == NULL) { 957 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 958 ret = -ENOMEM; 959 goto Err_out; 960 } 961 962 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 963 ctx->train_data_size, 964 ctx->p2c_train_data_offset, 965 ctx->c2p_train_data_offset); 966 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 967 return 0; 968 969 Err_out: 970 psp_v11_0_memory_training_fini(psp); 971 return ret; 972 } 973 974 /* 975 * save and restore proces 976 */ 977 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 978 { 979 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 980 uint32_t *pcache = (uint32_t*)ctx->sys_cache; 981 struct amdgpu_device *adev = psp->adev; 982 uint32_t p2c_header[4]; 983 uint32_t sz; 984 void *buf; 985 int ret; 986 987 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 988 DRM_DEBUG("Memory training is not supported.\n"); 989 return 0; 990 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 991 DRM_ERROR("Memory training initialization failure.\n"); 992 return -EINVAL; 993 } 994 995 if (psp_v11_0_is_sos_alive(psp)) { 996 DRM_DEBUG("SOS is alive, skip memory training.\n"); 997 return 0; 998 } 999 1000 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 1001 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 1002 pcache[0], pcache[1], pcache[2], pcache[3], 1003 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 1004 1005 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 1006 DRM_DEBUG("Short training depends on restore.\n"); 1007 ops |= PSP_MEM_TRAIN_RESTORE; 1008 } 1009 1010 if ((ops & PSP_MEM_TRAIN_RESTORE) && 1011 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 1012 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 1013 ops |= PSP_MEM_TRAIN_SAVE; 1014 } 1015 1016 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 1017 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 1018 pcache[3] == p2c_header[3])) { 1019 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 1020 ops |= PSP_MEM_TRAIN_SAVE; 1021 } 1022 1023 if ((ops & PSP_MEM_TRAIN_SAVE) && 1024 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 1025 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 1026 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 1027 } 1028 1029 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 1030 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 1031 ops |= PSP_MEM_TRAIN_SAVE; 1032 } 1033 1034 DRM_DEBUG("Memory training ops:%x.\n", ops); 1035 1036 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 1037 /* 1038 * Long traing will encroach certain mount of bottom VRAM, 1039 * saving the content of this bottom VRAM to system memory 1040 * before training, and restoring it after training to avoid 1041 * VRAM corruption. 1042 */ 1043 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 1044 1045 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 1046 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 1047 adev->gmc.visible_vram_size, 1048 adev->mman.aper_base_kaddr); 1049 return -EINVAL; 1050 } 1051 1052 buf = vmalloc(sz); 1053 if (!buf) { 1054 DRM_ERROR("failed to allocate system memory.\n"); 1055 return -ENOMEM; 1056 } 1057 1058 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 1059 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 1060 if (ret) { 1061 DRM_ERROR("Send long training msg failed.\n"); 1062 vfree(buf); 1063 return ret; 1064 } 1065 1066 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 1067 adev->nbio.funcs->hdp_flush(adev, NULL); 1068 vfree(buf); 1069 } 1070 1071 if (ops & PSP_MEM_TRAIN_SAVE) { 1072 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 1073 } 1074 1075 if (ops & PSP_MEM_TRAIN_RESTORE) { 1076 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 1077 } 1078 1079 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 1080 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 1081 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 1082 if (ret) { 1083 DRM_ERROR("send training msg failed.\n"); 1084 return ret; 1085 } 1086 } 1087 ctx->training_cnt++; 1088 return 0; 1089 } 1090 1091 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 1092 { 1093 uint32_t data; 1094 struct amdgpu_device *adev = psp->adev; 1095 1096 if (psp_v11_0_support_vmr_ring(psp)) 1097 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 1098 else 1099 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 1100 1101 return data; 1102 } 1103 1104 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 1105 { 1106 struct amdgpu_device *adev = psp->adev; 1107 1108 if (psp_v11_0_support_vmr_ring(psp)) { 1109 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 1110 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 1111 } else 1112 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 1113 } 1114 1115 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, dma_addr_t dma_addr) 1116 { 1117 struct amdgpu_device *adev = psp->adev; 1118 uint32_t reg_status; 1119 int ret, i = 0; 1120 1121 /* Write lower 32-bit address of the PD Controller FW */ 1122 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, lower_32_bits(dma_addr)); 1123 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 1124 0x80000000, 0x80000000, false); 1125 if (ret) 1126 return ret; 1127 1128 /* Fireup interrupt so PSP can pick up the lower address */ 1129 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x800000); 1130 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 1131 0x80000000, 0x80000000, false); 1132 if (ret) 1133 return ret; 1134 1135 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 1136 1137 if ((reg_status & 0xFFFF) != 0) { 1138 DRM_ERROR("Lower address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %02x...\n", 1139 reg_status & 0xFFFF); 1140 return -EIO; 1141 } 1142 1143 /* Write upper 32-bit address of the PD Controller FW */ 1144 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, upper_32_bits(dma_addr)); 1145 1146 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 1147 0x80000000, 0x80000000, false); 1148 if (ret) 1149 return ret; 1150 1151 /* Fireup interrupt so PSP can pick up the upper address */ 1152 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x4000000); 1153 1154 /* FW load takes very long time */ 1155 do { 1156 msleep(1000); 1157 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 1158 1159 if (reg_status & 0x80000000) 1160 goto done; 1161 1162 } while (++i < USBC_PD_POLLING_LIMIT_S); 1163 1164 return -ETIME; 1165 done: 1166 1167 if ((reg_status & 0xFFFF) != 0) { 1168 DRM_ERROR("Upper address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = x%04x\n", 1169 reg_status & 0xFFFF); 1170 return -EIO; 1171 } 1172 1173 return 0; 1174 } 1175 1176 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 1177 { 1178 struct amdgpu_device *adev = psp->adev; 1179 int ret; 1180 1181 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 1182 1183 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 1184 0x80000000, 0x80000000, false); 1185 if (!ret) 1186 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36); 1187 1188 return ret; 1189 } 1190 1191 static const struct psp_funcs psp_v11_0_funcs = { 1192 .init_microcode = psp_v11_0_init_microcode, 1193 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 1194 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 1195 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 1196 .ring_init = psp_v11_0_ring_init, 1197 .ring_create = psp_v11_0_ring_create, 1198 .ring_stop = psp_v11_0_ring_stop, 1199 .ring_destroy = psp_v11_0_ring_destroy, 1200 .compare_sram_data = psp_v11_0_compare_sram_data, 1201 .mode1_reset = psp_v11_0_mode1_reset, 1202 .xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info, 1203 .xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info, 1204 .xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id, 1205 .xgmi_get_node_id = psp_v11_0_xgmi_get_node_id, 1206 .support_vmr_ring = psp_v11_0_support_vmr_ring, 1207 .ras_trigger_error = psp_v11_0_ras_trigger_error, 1208 .ras_cure_posion = psp_v11_0_ras_cure_posion, 1209 .rlc_autoload_start = psp_v11_0_rlc_autoload_start, 1210 .mem_training_init = psp_v11_0_memory_training_init, 1211 .mem_training_fini = psp_v11_0_memory_training_fini, 1212 .mem_training = psp_v11_0_memory_training, 1213 .ring_get_wptr = psp_v11_0_ring_get_wptr, 1214 .ring_set_wptr = psp_v11_0_ring_set_wptr, 1215 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, 1216 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw 1217 }; 1218 1219 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 1220 { 1221 psp->funcs = &psp_v11_0_funcs; 1222 } 1223