1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/vmalloc.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_psp.h" 29 #include "amdgpu_ras.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v11_0.h" 33 34 #include "mp/mp_11_0_offset.h" 35 #include "mp/mp_11_0_sh_mask.h" 36 #include "gc/gc_9_0_offset.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "nbio/nbio_7_4_offset.h" 39 40 #include "oss/osssys_4_0_offset.h" 41 #include "oss/osssys_4_0_sh_mask.h" 42 43 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 45 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 48 MODULE_FIRMWARE("amdgpu/navi10_ta.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 50 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 51 MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 53 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 54 MODULE_FIRMWARE("amdgpu/navi12_ta.bin"); 55 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 56 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 57 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 58 59 /* address block */ 60 #define smnMP1_FIRMWARE_FLAGS 0x3010024 61 /* navi10 reg offset define */ 62 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 63 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 64 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 65 #define mmSDMA0_UCODE_DATA_NV10 0x5881 66 /* memory training timeout define */ 67 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 68 69 /* For large FW files the time to complete can be very long */ 70 #define USBC_PD_POLLING_LIMIT_S 240 71 72 static int psp_v11_0_init_microcode(struct psp_context *psp) 73 { 74 struct amdgpu_device *adev = psp->adev; 75 const char *chip_name; 76 char fw_name[30]; 77 int err = 0; 78 const struct ta_firmware_header_v1_0 *ta_hdr; 79 80 DRM_DEBUG("\n"); 81 82 switch (adev->asic_type) { 83 case CHIP_VEGA20: 84 chip_name = "vega20"; 85 break; 86 case CHIP_NAVI10: 87 chip_name = "navi10"; 88 break; 89 case CHIP_NAVI14: 90 chip_name = "navi14"; 91 break; 92 case CHIP_NAVI12: 93 chip_name = "navi12"; 94 break; 95 case CHIP_ARCTURUS: 96 chip_name = "arcturus"; 97 break; 98 default: 99 BUG(); 100 } 101 102 err = psp_init_sos_microcode(psp, chip_name); 103 if (err) 104 return err; 105 106 err = psp_init_asd_microcode(psp, chip_name); 107 if (err) 108 return err; 109 110 switch (adev->asic_type) { 111 case CHIP_VEGA20: 112 case CHIP_ARCTURUS: 113 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 114 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 115 if (err) { 116 release_firmware(adev->psp.ta_fw); 117 adev->psp.ta_fw = NULL; 118 dev_info(adev->dev, 119 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 120 } else { 121 err = amdgpu_ucode_validate(adev->psp.ta_fw); 122 if (err) 123 goto out2; 124 125 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 126 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 127 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 128 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 129 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 130 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 131 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); 132 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); 133 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + 134 le32_to_cpu(ta_hdr->ta_ras_offset_bytes); 135 } 136 break; 137 case CHIP_NAVI10: 138 case CHIP_NAVI14: 139 case CHIP_NAVI12: 140 if (amdgpu_sriov_vf(adev)) 141 break; 142 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 143 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 144 if (err) { 145 release_firmware(adev->psp.ta_fw); 146 adev->psp.ta_fw = NULL; 147 dev_info(adev->dev, 148 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 149 } else { 150 err = amdgpu_ucode_validate(adev->psp.ta_fw); 151 if (err) 152 goto out2; 153 154 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 155 adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 156 adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 157 adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr + 158 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 159 160 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 161 162 adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 163 adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 164 adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr + 165 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 166 } 167 break; 168 default: 169 BUG(); 170 } 171 172 return 0; 173 174 out2: 175 release_firmware(adev->psp.ta_fw); 176 adev->psp.ta_fw = NULL; 177 return err; 178 } 179 180 int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 181 { 182 struct amdgpu_device *adev = psp->adev; 183 184 int ret; 185 int retry_loop; 186 187 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 188 /* Wait for bootloader to signify that is 189 ready having bit 31 of C2PMSG_35 set to 1 */ 190 ret = psp_wait_for(psp, 191 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 192 0x80000000, 193 0x80000000, 194 false); 195 196 if (ret == 0) 197 return 0; 198 } 199 200 return ret; 201 } 202 203 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 204 { 205 struct amdgpu_device *adev = psp->adev; 206 uint32_t sol_reg; 207 208 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 209 210 return sol_reg != 0x0; 211 } 212 213 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 214 { 215 int ret; 216 uint32_t psp_gfxdrv_command_reg = 0; 217 struct amdgpu_device *adev = psp->adev; 218 219 /* Check tOS sign of life register to confirm sys driver and sOS 220 * are already been loaded. 221 */ 222 if (psp_v11_0_is_sos_alive(psp)) 223 return 0; 224 225 ret = psp_v11_0_wait_for_bootloader(psp); 226 if (ret) 227 return ret; 228 229 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 230 231 /* Copy PSP KDB binary to memory */ 232 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); 233 234 /* Provide the PSP KDB to bootloader */ 235 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 236 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 237 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; 238 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 239 psp_gfxdrv_command_reg); 240 241 ret = psp_v11_0_wait_for_bootloader(psp); 242 243 return ret; 244 } 245 246 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 247 { 248 int ret; 249 uint32_t psp_gfxdrv_command_reg = 0; 250 struct amdgpu_device *adev = psp->adev; 251 252 /* Check sOS sign of life register to confirm sys driver and sOS 253 * are already been loaded. 254 */ 255 if (psp_v11_0_is_sos_alive(psp)) 256 return 0; 257 258 ret = psp_v11_0_wait_for_bootloader(psp); 259 if (ret) 260 return ret; 261 262 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 263 264 /* Copy PSP System Driver binary to memory */ 265 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 266 267 /* Provide the sys driver to bootloader */ 268 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 269 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 270 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 271 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 272 psp_gfxdrv_command_reg); 273 274 /* there might be handshake issue with hardware which needs delay */ 275 mdelay(20); 276 277 ret = psp_v11_0_wait_for_bootloader(psp); 278 279 return ret; 280 } 281 282 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 283 { 284 int ret; 285 unsigned int psp_gfxdrv_command_reg = 0; 286 struct amdgpu_device *adev = psp->adev; 287 288 /* Check sOS sign of life register to confirm sys driver and sOS 289 * are already been loaded. 290 */ 291 if (psp_v11_0_is_sos_alive(psp)) 292 return 0; 293 294 ret = psp_v11_0_wait_for_bootloader(psp); 295 if (ret) 296 return ret; 297 298 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 299 300 /* Copy Secure OS binary to PSP memory */ 301 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 302 303 /* Provide the PSP secure OS to bootloader */ 304 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 305 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 306 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 307 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 308 psp_gfxdrv_command_reg); 309 310 /* there might be handshake issue with hardware which needs delay */ 311 mdelay(20); 312 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 313 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 314 0, true); 315 316 return ret; 317 } 318 319 static void psp_v11_0_reroute_ih(struct psp_context *psp) 320 { 321 struct amdgpu_device *adev = psp->adev; 322 uint32_t tmp; 323 324 /* Change IH ring for VMC */ 325 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 326 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 327 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 328 329 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 330 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 331 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 332 333 mdelay(20); 334 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 335 0x80000000, 0x8000FFFF, false); 336 337 /* Change IH ring for UMC */ 338 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 339 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 340 341 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 342 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 343 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 344 345 mdelay(20); 346 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 347 0x80000000, 0x8000FFFF, false); 348 } 349 350 static int psp_v11_0_ring_init(struct psp_context *psp, 351 enum psp_ring_type ring_type) 352 { 353 int ret = 0; 354 struct psp_ring *ring; 355 struct amdgpu_device *adev = psp->adev; 356 357 if (!amdgpu_sriov_vf(adev)) 358 psp_v11_0_reroute_ih(psp); 359 360 ring = &psp->km_ring; 361 362 ring->ring_type = ring_type; 363 364 /* allocate 4k Page of Local Frame Buffer memory for ring */ 365 ring->ring_size = 0x1000; 366 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 367 AMDGPU_GEM_DOMAIN_VRAM, 368 &adev->firmware.rbuf, 369 &ring->ring_mem_mc_addr, 370 (void **)&ring->ring_mem); 371 if (ret) { 372 ring->ring_size = 0; 373 return ret; 374 } 375 376 return 0; 377 } 378 379 static int psp_v11_0_ring_stop(struct psp_context *psp, 380 enum psp_ring_type ring_type) 381 { 382 int ret = 0; 383 struct amdgpu_device *adev = psp->adev; 384 385 /* Write the ring destroy command*/ 386 if (amdgpu_sriov_vf(adev)) 387 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 388 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 389 else 390 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 391 GFX_CTRL_CMD_ID_DESTROY_RINGS); 392 393 /* there might be handshake issue with hardware which needs delay */ 394 mdelay(20); 395 396 /* Wait for response flag (bit 31) */ 397 if (amdgpu_sriov_vf(adev)) 398 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 399 0x80000000, 0x80000000, false); 400 else 401 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 402 0x80000000, 0x80000000, false); 403 404 return ret; 405 } 406 407 static int psp_v11_0_ring_create(struct psp_context *psp, 408 enum psp_ring_type ring_type) 409 { 410 int ret = 0; 411 unsigned int psp_ring_reg = 0; 412 struct psp_ring *ring = &psp->km_ring; 413 struct amdgpu_device *adev = psp->adev; 414 415 if (amdgpu_sriov_vf(adev)) { 416 ret = psp_v11_0_ring_stop(psp, ring_type); 417 if (ret) { 418 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 419 return ret; 420 } 421 422 /* Write low address of the ring to C2PMSG_102 */ 423 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 424 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 425 /* Write high address of the ring to C2PMSG_103 */ 426 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 427 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 428 429 /* Write the ring initialization command to C2PMSG_101 */ 430 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 431 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 432 433 /* there might be handshake issue with hardware which needs delay */ 434 mdelay(20); 435 436 /* Wait for response flag (bit 31) in C2PMSG_101 */ 437 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 438 0x80000000, 0x8000FFFF, false); 439 440 } else { 441 /* Wait for sOS ready for ring creation */ 442 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 443 0x80000000, 0x80000000, false); 444 if (ret) { 445 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 446 return ret; 447 } 448 449 /* Write low address of the ring to C2PMSG_69 */ 450 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 451 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 452 /* Write high address of the ring to C2PMSG_70 */ 453 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 454 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 455 /* Write size of ring to C2PMSG_71 */ 456 psp_ring_reg = ring->ring_size; 457 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 458 /* Write the ring initialization command to C2PMSG_64 */ 459 psp_ring_reg = ring_type; 460 psp_ring_reg = psp_ring_reg << 16; 461 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 462 463 /* there might be handshake issue with hardware which needs delay */ 464 mdelay(20); 465 466 /* Wait for response flag (bit 31) in C2PMSG_64 */ 467 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 468 0x80000000, 0x8000FFFF, false); 469 } 470 471 return ret; 472 } 473 474 475 static int psp_v11_0_ring_destroy(struct psp_context *psp, 476 enum psp_ring_type ring_type) 477 { 478 int ret = 0; 479 struct psp_ring *ring = &psp->km_ring; 480 struct amdgpu_device *adev = psp->adev; 481 482 ret = psp_v11_0_ring_stop(psp, ring_type); 483 if (ret) 484 DRM_ERROR("Fail to stop psp ring\n"); 485 486 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 487 &ring->ring_mem_mc_addr, 488 (void **)&ring->ring_mem); 489 490 return ret; 491 } 492 493 static int psp_v11_0_mode1_reset(struct psp_context *psp) 494 { 495 int ret; 496 uint32_t offset; 497 struct amdgpu_device *adev = psp->adev; 498 499 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 500 501 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 502 503 if (ret) { 504 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 505 return -EINVAL; 506 } 507 508 /*send the mode 1 reset command*/ 509 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 510 511 msleep(500); 512 513 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 514 515 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 516 517 if (ret) { 518 DRM_INFO("psp mode 1 reset failed!\n"); 519 return -EINVAL; 520 } 521 522 DRM_INFO("psp mode1 reset succeed \n"); 523 524 return 0; 525 } 526 527 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 528 { 529 int ret; 530 int i; 531 uint32_t data_32; 532 int max_wait; 533 struct amdgpu_device *adev = psp->adev; 534 535 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 536 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 537 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 538 539 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 540 for (i = 0; i < max_wait; i++) { 541 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 542 0x80000000, 0x80000000, false); 543 if (ret == 0) 544 break; 545 } 546 if (i < max_wait) 547 ret = 0; 548 else 549 ret = -ETIME; 550 551 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 552 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 553 (ret == 0) ? "succeed" : "failed", 554 i, adev->usec_timeout/1000); 555 return ret; 556 } 557 558 /* 559 * save and restore proces 560 */ 561 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 562 { 563 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 564 uint32_t *pcache = (uint32_t*)ctx->sys_cache; 565 struct amdgpu_device *adev = psp->adev; 566 uint32_t p2c_header[4]; 567 uint32_t sz; 568 void *buf; 569 int ret; 570 571 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 572 DRM_DEBUG("Memory training is not supported.\n"); 573 return 0; 574 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 575 DRM_ERROR("Memory training initialization failure.\n"); 576 return -EINVAL; 577 } 578 579 if (psp_v11_0_is_sos_alive(psp)) { 580 DRM_DEBUG("SOS is alive, skip memory training.\n"); 581 return 0; 582 } 583 584 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 585 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 586 pcache[0], pcache[1], pcache[2], pcache[3], 587 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 588 589 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 590 DRM_DEBUG("Short training depends on restore.\n"); 591 ops |= PSP_MEM_TRAIN_RESTORE; 592 } 593 594 if ((ops & PSP_MEM_TRAIN_RESTORE) && 595 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 596 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 597 ops |= PSP_MEM_TRAIN_SAVE; 598 } 599 600 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 601 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 602 pcache[3] == p2c_header[3])) { 603 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 604 ops |= PSP_MEM_TRAIN_SAVE; 605 } 606 607 if ((ops & PSP_MEM_TRAIN_SAVE) && 608 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 609 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 610 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 611 } 612 613 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 614 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 615 ops |= PSP_MEM_TRAIN_SAVE; 616 } 617 618 DRM_DEBUG("Memory training ops:%x.\n", ops); 619 620 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 621 /* 622 * Long traing will encroach certain mount of bottom VRAM, 623 * saving the content of this bottom VRAM to system memory 624 * before training, and restoring it after training to avoid 625 * VRAM corruption. 626 */ 627 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 628 629 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 630 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 631 adev->gmc.visible_vram_size, 632 adev->mman.aper_base_kaddr); 633 return -EINVAL; 634 } 635 636 buf = vmalloc(sz); 637 if (!buf) { 638 DRM_ERROR("failed to allocate system memory.\n"); 639 return -ENOMEM; 640 } 641 642 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 643 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 644 if (ret) { 645 DRM_ERROR("Send long training msg failed.\n"); 646 vfree(buf); 647 return ret; 648 } 649 650 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 651 adev->nbio.funcs->hdp_flush(adev, NULL); 652 vfree(buf); 653 } 654 655 if (ops & PSP_MEM_TRAIN_SAVE) { 656 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 657 } 658 659 if (ops & PSP_MEM_TRAIN_RESTORE) { 660 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 661 } 662 663 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 664 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 665 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 666 if (ret) { 667 DRM_ERROR("send training msg failed.\n"); 668 return ret; 669 } 670 } 671 ctx->training_cnt++; 672 return 0; 673 } 674 675 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 676 { 677 uint32_t data; 678 struct amdgpu_device *adev = psp->adev; 679 680 if (amdgpu_sriov_vf(adev)) 681 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 682 else 683 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 684 685 return data; 686 } 687 688 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 689 { 690 struct amdgpu_device *adev = psp->adev; 691 692 if (amdgpu_sriov_vf(adev)) { 693 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 694 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 695 } else 696 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 697 } 698 699 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, dma_addr_t dma_addr) 700 { 701 struct amdgpu_device *adev = psp->adev; 702 uint32_t reg_status; 703 int ret, i = 0; 704 705 /* Write lower 32-bit address of the PD Controller FW */ 706 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, lower_32_bits(dma_addr)); 707 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 708 0x80000000, 0x80000000, false); 709 if (ret) 710 return ret; 711 712 /* Fireup interrupt so PSP can pick up the lower address */ 713 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x800000); 714 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 715 0x80000000, 0x80000000, false); 716 if (ret) 717 return ret; 718 719 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 720 721 if ((reg_status & 0xFFFF) != 0) { 722 DRM_ERROR("Lower address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %02x...\n", 723 reg_status & 0xFFFF); 724 return -EIO; 725 } 726 727 /* Write upper 32-bit address of the PD Controller FW */ 728 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, upper_32_bits(dma_addr)); 729 730 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 731 0x80000000, 0x80000000, false); 732 if (ret) 733 return ret; 734 735 /* Fireup interrupt so PSP can pick up the upper address */ 736 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x4000000); 737 738 /* FW load takes very long time */ 739 do { 740 msleep(1000); 741 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 742 743 if (reg_status & 0x80000000) 744 goto done; 745 746 } while (++i < USBC_PD_POLLING_LIMIT_S); 747 748 return -ETIME; 749 done: 750 751 if ((reg_status & 0xFFFF) != 0) { 752 DRM_ERROR("Upper address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = x%04x\n", 753 reg_status & 0xFFFF); 754 return -EIO; 755 } 756 757 return 0; 758 } 759 760 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 761 { 762 struct amdgpu_device *adev = psp->adev; 763 int ret; 764 765 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 766 767 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 768 0x80000000, 0x80000000, false); 769 if (!ret) 770 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36); 771 772 return ret; 773 } 774 775 static const struct psp_funcs psp_v11_0_funcs = { 776 .init_microcode = psp_v11_0_init_microcode, 777 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 778 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 779 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 780 .ring_init = psp_v11_0_ring_init, 781 .ring_create = psp_v11_0_ring_create, 782 .ring_stop = psp_v11_0_ring_stop, 783 .ring_destroy = psp_v11_0_ring_destroy, 784 .mode1_reset = psp_v11_0_mode1_reset, 785 .mem_training = psp_v11_0_memory_training, 786 .ring_get_wptr = psp_v11_0_ring_get_wptr, 787 .ring_set_wptr = psp_v11_0_ring_set_wptr, 788 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, 789 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw 790 }; 791 792 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 793 { 794 psp->funcs = &psp_v11_0_funcs; 795 } 796