1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_ucode.h" 33 #include "soc15_common.h" 34 #include "psp_v10_0.h" 35 36 #include "mp/mp_10_0_offset.h" 37 #include "gc/gc_9_1_offset.h" 38 #include "sdma0/sdma0_4_1_offset.h" 39 40 MODULE_FIRMWARE("amdgpu/raven_asd.bin"); 41 MODULE_FIRMWARE("amdgpu/picasso_asd.bin"); 42 MODULE_FIRMWARE("amdgpu/raven2_asd.bin"); 43 MODULE_FIRMWARE("amdgpu/picasso_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/raven2_ta.bin"); 45 MODULE_FIRMWARE("amdgpu/raven_ta.bin"); 46 47 static int psp_v10_0_init_microcode(struct psp_context *psp) 48 { 49 struct amdgpu_device *adev = psp->adev; 50 const char *chip_name; 51 char fw_name[30]; 52 int err = 0; 53 const struct psp_firmware_header_v1_0 *hdr; 54 const struct ta_firmware_header_v1_0 *ta_hdr; 55 DRM_DEBUG("\n"); 56 57 switch (adev->asic_type) { 58 case CHIP_RAVEN: 59 if (adev->rev_id >= 0x8) 60 chip_name = "raven2"; 61 else if (adev->pdev->device == 0x15d8) 62 chip_name = "picasso"; 63 else 64 chip_name = "raven"; 65 break; 66 default: BUG(); 67 } 68 69 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 70 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 71 if (err) 72 goto out; 73 74 err = amdgpu_ucode_validate(adev->psp.asd_fw); 75 if (err) 76 goto out; 77 78 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 79 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 80 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 81 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 82 adev->psp.asd_start_addr = (uint8_t *)hdr + 83 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 84 85 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 86 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 87 if (err) { 88 release_firmware(adev->psp.ta_fw); 89 adev->psp.ta_fw = NULL; 90 dev_info(adev->dev, 91 "psp v10.0: Failed to load firmware \"%s\"\n", 92 fw_name); 93 } else { 94 err = amdgpu_ucode_validate(adev->psp.ta_fw); 95 if (err) 96 goto out2; 97 98 ta_hdr = (const struct ta_firmware_header_v1_0 *) 99 adev->psp.ta_fw->data; 100 adev->psp.ta_hdcp_ucode_version = 101 le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 102 adev->psp.ta_hdcp_ucode_size = 103 le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 104 adev->psp.ta_hdcp_start_addr = 105 (uint8_t *)ta_hdr + 106 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 107 108 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 109 110 adev->psp.ta_dtm_ucode_version = 111 le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 112 adev->psp.ta_dtm_ucode_size = 113 le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 114 adev->psp.ta_dtm_start_addr = 115 (uint8_t *)adev->psp.ta_hdcp_start_addr + 116 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 117 } 118 119 return 0; 120 121 out2: 122 release_firmware(adev->psp.ta_fw); 123 adev->psp.ta_fw = NULL; 124 out: 125 if (err) { 126 dev_err(adev->dev, 127 "psp v10.0: Failed to load firmware \"%s\"\n", 128 fw_name); 129 release_firmware(adev->psp.asd_fw); 130 adev->psp.asd_fw = NULL; 131 } 132 133 return err; 134 } 135 136 static int psp_v10_0_ring_init(struct psp_context *psp, 137 enum psp_ring_type ring_type) 138 { 139 int ret = 0; 140 struct psp_ring *ring; 141 struct amdgpu_device *adev = psp->adev; 142 143 ring = &psp->km_ring; 144 145 ring->ring_type = ring_type; 146 147 /* allocate 4k Page of Local Frame Buffer memory for ring */ 148 ring->ring_size = 0x1000; 149 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 150 AMDGPU_GEM_DOMAIN_VRAM, 151 &adev->firmware.rbuf, 152 &ring->ring_mem_mc_addr, 153 (void **)&ring->ring_mem); 154 if (ret) { 155 ring->ring_size = 0; 156 return ret; 157 } 158 159 return 0; 160 } 161 162 static int psp_v10_0_ring_create(struct psp_context *psp, 163 enum psp_ring_type ring_type) 164 { 165 int ret = 0; 166 unsigned int psp_ring_reg = 0; 167 struct psp_ring *ring = &psp->km_ring; 168 struct amdgpu_device *adev = psp->adev; 169 170 /* Write low address of the ring to C2PMSG_69 */ 171 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 172 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 173 /* Write high address of the ring to C2PMSG_70 */ 174 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 175 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 176 /* Write size of ring to C2PMSG_71 */ 177 psp_ring_reg = ring->ring_size; 178 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 179 /* Write the ring initialization command to C2PMSG_64 */ 180 psp_ring_reg = ring_type; 181 psp_ring_reg = psp_ring_reg << 16; 182 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 183 184 /* There might be handshake issue with hardware which needs delay */ 185 mdelay(20); 186 187 /* Wait for response flag (bit 31) in C2PMSG_64 */ 188 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 189 0x80000000, 0x8000FFFF, false); 190 191 return ret; 192 } 193 194 static int psp_v10_0_ring_stop(struct psp_context *psp, 195 enum psp_ring_type ring_type) 196 { 197 int ret = 0; 198 unsigned int psp_ring_reg = 0; 199 struct amdgpu_device *adev = psp->adev; 200 201 /* Write the ring destroy command to C2PMSG_64 */ 202 psp_ring_reg = 3 << 16; 203 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 204 205 /* There might be handshake issue with hardware which needs delay */ 206 mdelay(20); 207 208 /* Wait for response flag (bit 31) in C2PMSG_64 */ 209 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 210 0x80000000, 0x80000000, false); 211 212 return ret; 213 } 214 215 static int psp_v10_0_ring_destroy(struct psp_context *psp, 216 enum psp_ring_type ring_type) 217 { 218 int ret = 0; 219 struct psp_ring *ring = &psp->km_ring; 220 struct amdgpu_device *adev = psp->adev; 221 222 ret = psp_v10_0_ring_stop(psp, ring_type); 223 if (ret) 224 DRM_ERROR("Fail to stop psp ring\n"); 225 226 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 227 &ring->ring_mem_mc_addr, 228 (void **)&ring->ring_mem); 229 230 return ret; 231 } 232 233 static int psp_v10_0_cmd_submit(struct psp_context *psp, 234 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 235 int index) 236 { 237 unsigned int psp_write_ptr_reg = 0; 238 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 239 struct psp_ring *ring = &psp->km_ring; 240 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 241 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 242 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 243 struct amdgpu_device *adev = psp->adev; 244 uint32_t ring_size_dw = ring->ring_size / 4; 245 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 246 247 /* KM (GPCOM) prepare write pointer */ 248 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 249 250 /* Update KM RB frame pointer to new frame */ 251 if ((psp_write_ptr_reg % ring_size_dw) == 0) 252 write_frame = ring_buffer_start; 253 else 254 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 255 /* Check invalid write_frame ptr address */ 256 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 257 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 258 ring_buffer_start, ring_buffer_end, write_frame); 259 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 260 return -EINVAL; 261 } 262 263 /* Initialize KM RB frame */ 264 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 265 266 /* Update KM RB frame */ 267 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 268 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 269 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 270 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 271 write_frame->fence_value = index; 272 amdgpu_asic_flush_hdp(adev, NULL); 273 274 /* Update the write Pointer in DWORDs */ 275 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 276 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 277 278 return 0; 279 } 280 281 static int 282 psp_v10_0_sram_map(struct amdgpu_device *adev, 283 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 284 unsigned int *sram_data_reg_offset, 285 enum AMDGPU_UCODE_ID ucode_id) 286 { 287 int ret = 0; 288 289 switch(ucode_id) { 290 /* TODO: needs to confirm */ 291 #if 0 292 case AMDGPU_UCODE_ID_SMC: 293 *sram_offset = 0; 294 *sram_addr_reg_offset = 0; 295 *sram_data_reg_offset = 0; 296 break; 297 #endif 298 299 case AMDGPU_UCODE_ID_CP_CE: 300 *sram_offset = 0x0; 301 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 302 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 303 break; 304 305 case AMDGPU_UCODE_ID_CP_PFP: 306 *sram_offset = 0x0; 307 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 308 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 309 break; 310 311 case AMDGPU_UCODE_ID_CP_ME: 312 *sram_offset = 0x0; 313 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 314 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 315 break; 316 317 case AMDGPU_UCODE_ID_CP_MEC1: 318 *sram_offset = 0x10000; 319 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 320 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 321 break; 322 323 case AMDGPU_UCODE_ID_CP_MEC2: 324 *sram_offset = 0x10000; 325 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 326 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 327 break; 328 329 case AMDGPU_UCODE_ID_RLC_G: 330 *sram_offset = 0x2000; 331 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 332 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 333 break; 334 335 case AMDGPU_UCODE_ID_SDMA0: 336 *sram_offset = 0x0; 337 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 338 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 339 break; 340 341 /* TODO: needs to confirm */ 342 #if 0 343 case AMDGPU_UCODE_ID_SDMA1: 344 *sram_offset = ; 345 *sram_addr_reg_offset = ; 346 break; 347 348 case AMDGPU_UCODE_ID_UVD: 349 *sram_offset = ; 350 *sram_addr_reg_offset = ; 351 break; 352 353 case AMDGPU_UCODE_ID_VCE: 354 *sram_offset = ; 355 *sram_addr_reg_offset = ; 356 break; 357 #endif 358 359 case AMDGPU_UCODE_ID_MAXIMUM: 360 default: 361 ret = -EINVAL; 362 break; 363 } 364 365 return ret; 366 } 367 368 static bool psp_v10_0_compare_sram_data(struct psp_context *psp, 369 struct amdgpu_firmware_info *ucode, 370 enum AMDGPU_UCODE_ID ucode_type) 371 { 372 int err = 0; 373 unsigned int fw_sram_reg_val = 0; 374 unsigned int fw_sram_addr_reg_offset = 0; 375 unsigned int fw_sram_data_reg_offset = 0; 376 unsigned int ucode_size; 377 uint32_t *ucode_mem = NULL; 378 struct amdgpu_device *adev = psp->adev; 379 380 err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 381 &fw_sram_data_reg_offset, ucode_type); 382 if (err) 383 return false; 384 385 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 386 387 ucode_size = ucode->ucode_size; 388 ucode_mem = (uint32_t *)ucode->kaddr; 389 while (!ucode_size) { 390 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 391 392 if (*ucode_mem != fw_sram_reg_val) 393 return false; 394 395 ucode_mem++; 396 /* 4 bytes */ 397 ucode_size -= 4; 398 } 399 400 return true; 401 } 402 403 404 static int psp_v10_0_mode1_reset(struct psp_context *psp) 405 { 406 DRM_INFO("psp mode 1 reset not supported now! \n"); 407 return -EINVAL; 408 } 409 410 static const struct psp_funcs psp_v10_0_funcs = { 411 .init_microcode = psp_v10_0_init_microcode, 412 .ring_init = psp_v10_0_ring_init, 413 .ring_create = psp_v10_0_ring_create, 414 .ring_stop = psp_v10_0_ring_stop, 415 .ring_destroy = psp_v10_0_ring_destroy, 416 .cmd_submit = psp_v10_0_cmd_submit, 417 .compare_sram_data = psp_v10_0_compare_sram_data, 418 .mode1_reset = psp_v10_0_mode1_reset, 419 }; 420 421 void psp_v10_0_set_psp_funcs(struct psp_context *psp) 422 { 423 psp->funcs = &psp_v10_0_funcs; 424 } 425