1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_ucode.h" 33 #include "soc15_common.h" 34 #include "psp_v10_0.h" 35 36 #include "mp/mp_10_0_offset.h" 37 #include "gc/gc_9_1_offset.h" 38 #include "sdma0/sdma0_4_1_offset.h" 39 40 MODULE_FIRMWARE("amdgpu/raven_asd.bin"); 41 MODULE_FIRMWARE("amdgpu/picasso_asd.bin"); 42 MODULE_FIRMWARE("amdgpu/raven2_asd.bin"); 43 MODULE_FIRMWARE("amdgpu/picasso_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/raven2_ta.bin"); 45 MODULE_FIRMWARE("amdgpu/raven_ta.bin"); 46 47 static int psp_v10_0_init_microcode(struct psp_context *psp) 48 { 49 struct amdgpu_device *adev = psp->adev; 50 char ucode_prefix[30]; 51 int err = 0; 52 DRM_DEBUG("\n"); 53 54 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 55 56 err = psp_init_asd_microcode(psp, ucode_prefix); 57 if (err) 58 return err; 59 60 return psp_init_ta_microcode(psp, ucode_prefix); 61 } 62 63 static int psp_v10_0_ring_create(struct psp_context *psp, 64 enum psp_ring_type ring_type) 65 { 66 int ret = 0; 67 unsigned int psp_ring_reg = 0; 68 struct psp_ring *ring = &psp->km_ring; 69 struct amdgpu_device *adev = psp->adev; 70 71 /* Write low address of the ring to C2PMSG_69 */ 72 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 73 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 74 /* Write high address of the ring to C2PMSG_70 */ 75 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 76 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 77 /* Write size of ring to C2PMSG_71 */ 78 psp_ring_reg = ring->ring_size; 79 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 80 /* Write the ring initialization command to C2PMSG_64 */ 81 psp_ring_reg = ring_type; 82 psp_ring_reg = psp_ring_reg << 16; 83 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 84 85 /* There might be handshake issue with hardware which needs delay */ 86 mdelay(20); 87 88 /* Wait for response flag (bit 31) in C2PMSG_64 */ 89 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 90 0x80000000, 0x8000FFFF, false); 91 92 return ret; 93 } 94 95 static int psp_v10_0_ring_stop(struct psp_context *psp, 96 enum psp_ring_type ring_type) 97 { 98 int ret = 0; 99 unsigned int psp_ring_reg = 0; 100 struct amdgpu_device *adev = psp->adev; 101 102 /* Write the ring destroy command to C2PMSG_64 */ 103 psp_ring_reg = 3 << 16; 104 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 105 106 /* There might be handshake issue with hardware which needs delay */ 107 mdelay(20); 108 109 /* Wait for response flag (bit 31) in C2PMSG_64 */ 110 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 111 0x80000000, 0x80000000, false); 112 113 return ret; 114 } 115 116 static int psp_v10_0_ring_destroy(struct psp_context *psp, 117 enum psp_ring_type ring_type) 118 { 119 int ret = 0; 120 struct psp_ring *ring = &psp->km_ring; 121 struct amdgpu_device *adev = psp->adev; 122 123 ret = psp_v10_0_ring_stop(psp, ring_type); 124 if (ret) 125 DRM_ERROR("Fail to stop psp ring\n"); 126 127 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 128 &ring->ring_mem_mc_addr, 129 (void **)&ring->ring_mem); 130 131 return ret; 132 } 133 134 static int psp_v10_0_mode1_reset(struct psp_context *psp) 135 { 136 DRM_INFO("psp mode 1 reset not supported now! \n"); 137 return -EINVAL; 138 } 139 140 static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp) 141 { 142 struct amdgpu_device *adev = psp->adev; 143 144 return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 145 } 146 147 static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 148 { 149 struct amdgpu_device *adev = psp->adev; 150 151 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 152 } 153 154 static const struct psp_funcs psp_v10_0_funcs = { 155 .init_microcode = psp_v10_0_init_microcode, 156 .ring_create = psp_v10_0_ring_create, 157 .ring_stop = psp_v10_0_ring_stop, 158 .ring_destroy = psp_v10_0_ring_destroy, 159 .mode1_reset = psp_v10_0_mode1_reset, 160 .ring_get_wptr = psp_v10_0_ring_get_wptr, 161 .ring_set_wptr = psp_v10_0_ring_set_wptr, 162 }; 163 164 void psp_v10_0_set_psp_funcs(struct psp_context *psp) 165 { 166 psp->funcs = &psp_v10_0_funcs; 167 } 168