1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_psp.h" 29 #include "amdgpu_ucode.h" 30 #include "soc15_common.h" 31 #include "psp_v10_0.h" 32 33 #include "mp/mp_10_0_offset.h" 34 #include "gc/gc_9_1_offset.h" 35 #include "sdma0/sdma0_4_1_offset.h" 36 37 MODULE_FIRMWARE("amdgpu/raven_asd.bin"); 38 39 static int 40 psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 41 { 42 switch(ucode->ucode_id) { 43 case AMDGPU_UCODE_ID_SDMA0: 44 *type = GFX_FW_TYPE_SDMA0; 45 break; 46 case AMDGPU_UCODE_ID_SDMA1: 47 *type = GFX_FW_TYPE_SDMA1; 48 break; 49 case AMDGPU_UCODE_ID_CP_CE: 50 *type = GFX_FW_TYPE_CP_CE; 51 break; 52 case AMDGPU_UCODE_ID_CP_PFP: 53 *type = GFX_FW_TYPE_CP_PFP; 54 break; 55 case AMDGPU_UCODE_ID_CP_ME: 56 *type = GFX_FW_TYPE_CP_ME; 57 break; 58 case AMDGPU_UCODE_ID_CP_MEC1: 59 *type = GFX_FW_TYPE_CP_MEC; 60 break; 61 case AMDGPU_UCODE_ID_CP_MEC1_JT: 62 *type = GFX_FW_TYPE_CP_MEC_ME1; 63 break; 64 case AMDGPU_UCODE_ID_CP_MEC2: 65 *type = GFX_FW_TYPE_CP_MEC; 66 break; 67 case AMDGPU_UCODE_ID_CP_MEC2_JT: 68 *type = GFX_FW_TYPE_CP_MEC_ME2; 69 break; 70 case AMDGPU_UCODE_ID_RLC_G: 71 *type = GFX_FW_TYPE_RLC_G; 72 break; 73 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 74 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL; 75 break; 76 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 77 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 78 break; 79 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 80 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 81 break; 82 case AMDGPU_UCODE_ID_SMC: 83 *type = GFX_FW_TYPE_SMU; 84 break; 85 case AMDGPU_UCODE_ID_UVD: 86 *type = GFX_FW_TYPE_UVD; 87 break; 88 case AMDGPU_UCODE_ID_VCE: 89 *type = GFX_FW_TYPE_VCE; 90 break; 91 case AMDGPU_UCODE_ID_MAXIMUM: 92 default: 93 return -EINVAL; 94 } 95 96 return 0; 97 } 98 99 static int psp_v10_0_init_microcode(struct psp_context *psp) 100 { 101 struct amdgpu_device *adev = psp->adev; 102 const char *chip_name; 103 char fw_name[30]; 104 int err = 0; 105 const struct psp_firmware_header_v1_0 *hdr; 106 107 DRM_DEBUG("\n"); 108 109 switch (adev->asic_type) { 110 case CHIP_RAVEN: 111 chip_name = "raven"; 112 break; 113 default: BUG(); 114 } 115 116 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 117 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 118 if (err) 119 goto out; 120 121 err = amdgpu_ucode_validate(adev->psp.asd_fw); 122 if (err) 123 goto out; 124 125 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 126 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 127 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 128 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 129 adev->psp.asd_start_addr = (uint8_t *)hdr + 130 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 131 132 return 0; 133 out: 134 if (err) { 135 dev_err(adev->dev, 136 "psp v10.0: Failed to load firmware \"%s\"\n", 137 fw_name); 138 release_firmware(adev->psp.asd_fw); 139 adev->psp.asd_fw = NULL; 140 } 141 142 return err; 143 } 144 145 static int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, 146 struct psp_gfx_cmd_resp *cmd) 147 { 148 int ret; 149 uint64_t fw_mem_mc_addr = ucode->mc_addr; 150 151 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 152 153 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 154 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 155 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 156 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 157 158 ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 159 if (ret) 160 DRM_ERROR("Unknown firmware type\n"); 161 162 return ret; 163 } 164 165 static int psp_v10_0_ring_init(struct psp_context *psp, 166 enum psp_ring_type ring_type) 167 { 168 int ret = 0; 169 struct psp_ring *ring; 170 struct amdgpu_device *adev = psp->adev; 171 172 ring = &psp->km_ring; 173 174 ring->ring_type = ring_type; 175 176 /* allocate 4k Page of Local Frame Buffer memory for ring */ 177 ring->ring_size = 0x1000; 178 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 179 AMDGPU_GEM_DOMAIN_VRAM, 180 &adev->firmware.rbuf, 181 &ring->ring_mem_mc_addr, 182 (void **)&ring->ring_mem); 183 if (ret) { 184 ring->ring_size = 0; 185 return ret; 186 } 187 188 return 0; 189 } 190 191 static int psp_v10_0_ring_create(struct psp_context *psp, 192 enum psp_ring_type ring_type) 193 { 194 int ret = 0; 195 unsigned int psp_ring_reg = 0; 196 struct psp_ring *ring = &psp->km_ring; 197 struct amdgpu_device *adev = psp->adev; 198 199 /* Write low address of the ring to C2PMSG_69 */ 200 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 201 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 202 /* Write high address of the ring to C2PMSG_70 */ 203 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 204 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 205 /* Write size of ring to C2PMSG_71 */ 206 psp_ring_reg = ring->ring_size; 207 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 208 /* Write the ring initialization command to C2PMSG_64 */ 209 psp_ring_reg = ring_type; 210 psp_ring_reg = psp_ring_reg << 16; 211 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 212 213 /* There might be handshake issue with hardware which needs delay */ 214 mdelay(20); 215 216 /* Wait for response flag (bit 31) in C2PMSG_64 */ 217 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 218 0x80000000, 0x8000FFFF, false); 219 220 return ret; 221 } 222 223 static int psp_v10_0_ring_stop(struct psp_context *psp, 224 enum psp_ring_type ring_type) 225 { 226 int ret = 0; 227 struct psp_ring *ring; 228 unsigned int psp_ring_reg = 0; 229 struct amdgpu_device *adev = psp->adev; 230 231 ring = &psp->km_ring; 232 233 /* Write the ring destroy command to C2PMSG_64 */ 234 psp_ring_reg = 3 << 16; 235 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 236 237 /* There might be handshake issue with hardware which needs delay */ 238 mdelay(20); 239 240 /* Wait for response flag (bit 31) in C2PMSG_64 */ 241 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 242 0x80000000, 0x80000000, false); 243 244 return ret; 245 } 246 247 static int psp_v10_0_ring_destroy(struct psp_context *psp, 248 enum psp_ring_type ring_type) 249 { 250 int ret = 0; 251 struct psp_ring *ring = &psp->km_ring; 252 struct amdgpu_device *adev = psp->adev; 253 254 ret = psp_v10_0_ring_stop(psp, ring_type); 255 if (ret) 256 DRM_ERROR("Fail to stop psp ring\n"); 257 258 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 259 &ring->ring_mem_mc_addr, 260 (void **)&ring->ring_mem); 261 262 return ret; 263 } 264 265 static int psp_v10_0_cmd_submit(struct psp_context *psp, 266 struct amdgpu_firmware_info *ucode, 267 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 268 int index) 269 { 270 unsigned int psp_write_ptr_reg = 0; 271 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 272 struct psp_ring *ring = &psp->km_ring; 273 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 274 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 275 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 276 struct amdgpu_device *adev = psp->adev; 277 uint32_t ring_size_dw = ring->ring_size / 4; 278 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 279 280 /* KM (GPCOM) prepare write pointer */ 281 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 282 283 /* Update KM RB frame pointer to new frame */ 284 if ((psp_write_ptr_reg % ring_size_dw) == 0) 285 write_frame = ring_buffer_start; 286 else 287 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 288 /* Check invalid write_frame ptr address */ 289 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 290 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 291 ring_buffer_start, ring_buffer_end, write_frame); 292 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 293 return -EINVAL; 294 } 295 296 /* Initialize KM RB frame */ 297 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 298 299 /* Update KM RB frame */ 300 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 301 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 302 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 303 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 304 write_frame->fence_value = index; 305 306 /* Update the write Pointer in DWORDs */ 307 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 308 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 309 310 return 0; 311 } 312 313 static int 314 psp_v10_0_sram_map(struct amdgpu_device *adev, 315 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 316 unsigned int *sram_data_reg_offset, 317 enum AMDGPU_UCODE_ID ucode_id) 318 { 319 int ret = 0; 320 321 switch(ucode_id) { 322 /* TODO: needs to confirm */ 323 #if 0 324 case AMDGPU_UCODE_ID_SMC: 325 *sram_offset = 0; 326 *sram_addr_reg_offset = 0; 327 *sram_data_reg_offset = 0; 328 break; 329 #endif 330 331 case AMDGPU_UCODE_ID_CP_CE: 332 *sram_offset = 0x0; 333 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 334 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 335 break; 336 337 case AMDGPU_UCODE_ID_CP_PFP: 338 *sram_offset = 0x0; 339 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 340 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 341 break; 342 343 case AMDGPU_UCODE_ID_CP_ME: 344 *sram_offset = 0x0; 345 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 346 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 347 break; 348 349 case AMDGPU_UCODE_ID_CP_MEC1: 350 *sram_offset = 0x10000; 351 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 352 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 353 break; 354 355 case AMDGPU_UCODE_ID_CP_MEC2: 356 *sram_offset = 0x10000; 357 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 358 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 359 break; 360 361 case AMDGPU_UCODE_ID_RLC_G: 362 *sram_offset = 0x2000; 363 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 364 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 365 break; 366 367 case AMDGPU_UCODE_ID_SDMA0: 368 *sram_offset = 0x0; 369 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 370 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 371 break; 372 373 /* TODO: needs to confirm */ 374 #if 0 375 case AMDGPU_UCODE_ID_SDMA1: 376 *sram_offset = ; 377 *sram_addr_reg_offset = ; 378 break; 379 380 case AMDGPU_UCODE_ID_UVD: 381 *sram_offset = ; 382 *sram_addr_reg_offset = ; 383 break; 384 385 case AMDGPU_UCODE_ID_VCE: 386 *sram_offset = ; 387 *sram_addr_reg_offset = ; 388 break; 389 #endif 390 391 case AMDGPU_UCODE_ID_MAXIMUM: 392 default: 393 ret = -EINVAL; 394 break; 395 } 396 397 return ret; 398 } 399 400 static bool psp_v10_0_compare_sram_data(struct psp_context *psp, 401 struct amdgpu_firmware_info *ucode, 402 enum AMDGPU_UCODE_ID ucode_type) 403 { 404 int err = 0; 405 unsigned int fw_sram_reg_val = 0; 406 unsigned int fw_sram_addr_reg_offset = 0; 407 unsigned int fw_sram_data_reg_offset = 0; 408 unsigned int ucode_size; 409 uint32_t *ucode_mem = NULL; 410 struct amdgpu_device *adev = psp->adev; 411 412 err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 413 &fw_sram_data_reg_offset, ucode_type); 414 if (err) 415 return false; 416 417 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 418 419 ucode_size = ucode->ucode_size; 420 ucode_mem = (uint32_t *)ucode->kaddr; 421 while (!ucode_size) { 422 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 423 424 if (*ucode_mem != fw_sram_reg_val) 425 return false; 426 427 ucode_mem++; 428 /* 4 bytes */ 429 ucode_size -= 4; 430 } 431 432 return true; 433 } 434 435 436 static int psp_v10_0_mode1_reset(struct psp_context *psp) 437 { 438 DRM_INFO("psp mode 1 reset not supported now! \n"); 439 return -EINVAL; 440 } 441 442 static const struct psp_funcs psp_v10_0_funcs = { 443 .init_microcode = psp_v10_0_init_microcode, 444 .prep_cmd_buf = psp_v10_0_prep_cmd_buf, 445 .ring_init = psp_v10_0_ring_init, 446 .ring_create = psp_v10_0_ring_create, 447 .ring_stop = psp_v10_0_ring_stop, 448 .ring_destroy = psp_v10_0_ring_destroy, 449 .cmd_submit = psp_v10_0_cmd_submit, 450 .compare_sram_data = psp_v10_0_compare_sram_data, 451 .mode1_reset = psp_v10_0_mode1_reset, 452 }; 453 454 void psp_v10_0_set_psp_funcs(struct psp_context *psp) 455 { 456 psp->funcs = &psp_v10_0_funcs; 457 } 458