1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _PSP_TEE_GFX_IF_H_ 25 #define _PSP_TEE_GFX_IF_H_ 26 27 #define PSP_GFX_CMD_BUF_VERSION 0x00000001 28 29 #define GFX_CMD_STATUS_MASK 0x0000FFFF 30 #define GFX_CMD_ID_MASK 0x000F0000 31 #define GFX_CMD_RESERVED_MASK 0x7FF00000 32 #define GFX_CMD_RESPONSE_MASK 0x80000000 33 34 /* TEE Gfx Command IDs for the register interface. 35 * Command ID must be between 0x00010000 and 0x000F0000. 36 */ 37 enum psp_gfx_crtl_cmd_id 38 { 39 GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */ 40 GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */ 41 GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */ 42 GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */ 43 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */ 44 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */ 45 GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */ 46 GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */ 47 GFX_CTRL_CMD_ID_CONSUME_CMD = 0x000A0000, /* send interrupt to psp for updating write pointer of vf */ 48 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */ 49 50 GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */ 51 }; 52 53 54 /*----------------------------------------------------------------------------- 55 NOTE: All physical addresses used in this interface are actually 56 GPU Virtual Addresses. 57 */ 58 59 60 /* Control registers of the TEE Gfx interface. These are located in 61 * SRBM-to-PSP mailbox registers (total 8 registers). 62 */ 63 struct psp_gfx_ctrl 64 { 65 volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */ 66 volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */ 67 volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */ 68 volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */ 69 volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */ 70 volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/ 71 volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */ 72 volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */ 73 74 }; 75 76 77 /* Response flag is set in the command when command is completed by PSP. 78 * Used in the GFX_CTRL.CmdResp. 79 * When PSP GFX I/F is initialized, the flag is set. 80 */ 81 #define GFX_FLAG_RESPONSE 0x80000000 82 83 84 /* TEE Gfx Command IDs for the ring buffer interface. */ 85 enum psp_gfx_cmd_id 86 { 87 GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */ 88 GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */ 89 GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */ 90 GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */ 91 GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */ 92 GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */ 93 GFX_CMD_ID_DESTROY_TMR = 0x00000007, /* destroy TMR region */ 94 GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */ 95 GFX_CMD_ID_SETUP_VMR = 0x00000009, /* setup VMR region */ 96 GFX_CMD_ID_DESTROY_VMR = 0x0000000A, /* destroy VMR region */ 97 }; 98 99 100 /* Command to load Trusted Application binary into PSP OS. */ 101 struct psp_gfx_cmd_load_ta 102 { 103 uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */ 104 uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */ 105 uint32_t app_len; /* length of the TA binary in bytes */ 106 uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */ 107 uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */ 108 uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */ 109 110 /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided 111 * for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead 112 * of using global persistent buffer. 113 */ 114 }; 115 116 117 /* Command to Unload Trusted Application binary from PSP OS. */ 118 struct psp_gfx_cmd_unload_ta 119 { 120 uint32_t session_id; /* Session ID of the loaded TA to be unloaded */ 121 122 }; 123 124 125 /* Shared buffers for InvokeCommand. 126 */ 127 struct psp_gfx_buf_desc 128 { 129 uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */ 130 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */ 131 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */ 132 133 }; 134 135 /* Max number of descriptors for one shared buffer (in how many different 136 * physical locations one shared buffer can be stored). If buffer is too much 137 * fragmented, error will be returned. 138 */ 139 #define GFX_BUF_MAX_DESC 64 140 141 struct psp_gfx_buf_list 142 { 143 uint32_t num_desc; /* number of buffer descriptors in the list */ 144 uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */ 145 struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */ 146 147 /* total 776 bytes */ 148 }; 149 150 /* Command to execute InvokeCommand entry point of the TA. */ 151 struct psp_gfx_cmd_invoke_cmd 152 { 153 uint32_t session_id; /* Session ID of the TA to be executed */ 154 uint32_t ta_cmd_id; /* Command ID to be sent to TA */ 155 struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */ 156 157 }; 158 159 160 /* Command to setup TMR region. */ 161 struct psp_gfx_cmd_setup_tmr 162 { 163 uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */ 164 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */ 165 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */ 166 167 }; 168 169 170 /* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */ 171 enum psp_gfx_fw_type 172 { 173 GFX_FW_TYPE_NONE = 0, 174 GFX_FW_TYPE_CP_ME = 1, 175 GFX_FW_TYPE_CP_PFP = 2, 176 GFX_FW_TYPE_CP_CE = 3, 177 GFX_FW_TYPE_CP_MEC = 4, 178 GFX_FW_TYPE_CP_MEC_ME1 = 5, 179 GFX_FW_TYPE_CP_MEC_ME2 = 6, 180 GFX_FW_TYPE_RLC_V = 7, 181 GFX_FW_TYPE_RLC_G = 8, 182 GFX_FW_TYPE_SDMA0 = 9, 183 GFX_FW_TYPE_SDMA1 = 10, 184 GFX_FW_TYPE_DMCU_ERAM = 11, 185 GFX_FW_TYPE_DMCU_ISR = 12, 186 GFX_FW_TYPE_VCN = 13, 187 GFX_FW_TYPE_UVD = 14, 188 GFX_FW_TYPE_VCE = 15, 189 GFX_FW_TYPE_ISP = 16, 190 GFX_FW_TYPE_ACP = 17, 191 GFX_FW_TYPE_SMU = 18, 192 GFX_FW_TYPE_MMSCH = 19, 193 GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20, 194 GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21, 195 GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = 22, 196 GFX_FW_TYPE_UVD1 = 23, 197 GFX_FW_TYPE_MAX = 24 198 }; 199 200 /* Command to load HW IP FW. */ 201 struct psp_gfx_cmd_load_ip_fw 202 { 203 uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */ 204 uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */ 205 uint32_t fw_size; /* FW buffer size in bytes */ 206 enum psp_gfx_fw_type fw_type; /* FW type */ 207 208 }; 209 210 /* Command to save/restore HW IP FW. */ 211 struct psp_gfx_cmd_save_restore_ip_fw 212 { 213 uint32_t save_fw; /* if set, command is used for saving fw otherwise for resetoring*/ 214 uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */ 215 uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */ 216 uint32_t buf_size; /* Size of the save/restore buffer in bytes */ 217 enum psp_gfx_fw_type fw_type; /* FW type */ 218 }; 219 220 /* All GFX ring buffer commands. */ 221 union psp_gfx_commands 222 { 223 struct psp_gfx_cmd_load_ta cmd_load_ta; 224 struct psp_gfx_cmd_unload_ta cmd_unload_ta; 225 struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd; 226 struct psp_gfx_cmd_setup_tmr cmd_setup_tmr; 227 struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw; 228 struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw; 229 }; 230 231 232 /* Structure of GFX Response buffer. 233 * For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI 234 * it is separate buffer. 235 */ 236 struct psp_gfx_resp 237 { 238 uint32_t status; /* +0 status of command execution */ 239 uint32_t session_id; /* +4 session ID in response to LoadTa command */ 240 uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */ 241 uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */ 242 243 uint32_t reserved[4]; 244 245 /* total 32 bytes */ 246 }; 247 248 /* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi 249 * and psp_gfx_rb_frame.cmd_buf_addr_lo. 250 */ 251 struct psp_gfx_cmd_resp 252 { 253 uint32_t buf_size; /* +0 total size of the buffer in bytes */ 254 uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */ 255 uint32_t cmd_id; /* +8 command ID */ 256 257 /* These fields are used for RBI only. They are all 0 in GPCOM commands 258 */ 259 uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */ 260 uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */ 261 uint32_t resp_offset; /* +20 offset within response buffer */ 262 uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */ 263 264 union psp_gfx_commands cmd; /* +28 command specific structures */ 265 266 uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28]; 267 268 /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response 269 * is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo. 270 */ 271 struct psp_gfx_resp resp; /* +864 response */ 272 273 uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)]; 274 275 /* total size 1024 bytes */ 276 }; 277 278 279 #define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/ 280 281 /* Structure of the Ring Buffer Frame */ 282 struct psp_gfx_rb_frame 283 { 284 uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */ 285 uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */ 286 uint32_t cmd_buf_size; /* +8 command buffer size in bytes */ 287 uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */ 288 uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */ 289 uint32_t fence_value; /* +20 Fence value */ 290 uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */ 291 uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */ 292 uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */ 293 uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */ 294 uint8_t reserved1[2]; /* +34 reserved, must be 0 */ 295 uint32_t reserved2[7]; /* +36 reserved, must be 0 */ 296 /* total 64 bytes */ 297 }; 298 299 #endif /* _PSP_TEE_GFX_IF_H_ */ 300