1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef _PSP_TEE_GFX_IF_H_
25 #define _PSP_TEE_GFX_IF_H_
26 
27 #define PSP_GFX_CMD_BUF_VERSION     0x00000001
28 
29 #define GFX_CMD_STATUS_MASK         0x0000FFFF
30 #define GFX_CMD_ID_MASK             0x000F0000
31 #define GFX_CMD_RESERVED_MASK       0x7FF00000
32 #define GFX_CMD_RESPONSE_MASK       0x80000000
33 
34 /* USBC PD FW version retrieval command */
35 #define C2PMSG_CMD_GFX_USB_PD_FW_VER 0x2000000
36 
37 /* TEE Gfx Command IDs for the register interface.
38 *  Command ID must be between 0x00010000 and 0x000F0000.
39 */
40 enum psp_gfx_crtl_cmd_id
41 {
42     GFX_CTRL_CMD_ID_INIT_RBI_RING   = 0x00010000,   /* initialize RBI ring */
43     GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000,   /* initialize GPCOM ring */
44     GFX_CTRL_CMD_ID_DESTROY_RINGS   = 0x00030000,   /* destroy rings */
45     GFX_CTRL_CMD_ID_CAN_INIT_RINGS  = 0x00040000,   /* is it allowed to initialized the rings */
46     GFX_CTRL_CMD_ID_ENABLE_INT      = 0x00050000,   /* enable PSP-to-Gfx interrupt */
47     GFX_CTRL_CMD_ID_DISABLE_INT     = 0x00060000,   /* disable PSP-to-Gfx interrupt */
48     GFX_CTRL_CMD_ID_MODE1_RST       = 0x00070000,   /* trigger the Mode 1 reset */
49     GFX_CTRL_CMD_ID_GBR_IH_SET      = 0x00080000,   /* set Gbr IH_RB_CNTL registers */
50     GFX_CTRL_CMD_ID_CONSUME_CMD     = 0x00090000,   /* send interrupt to psp for updating write pointer of vf */
51     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */
52 
53     GFX_CTRL_CMD_ID_MAX             = 0x000F0000,   /* max command ID */
54 };
55 
56 
57 /*-----------------------------------------------------------------------------
58     NOTE:   All physical addresses used in this interface are actually
59             GPU Virtual Addresses.
60 */
61 
62 
63 /* Control registers of the TEE Gfx interface. These are located in
64 *  SRBM-to-PSP mailbox registers (total 8 registers).
65 */
66 struct psp_gfx_ctrl
67 {
68     volatile uint32_t   cmd_resp;         /* +0   Command/Response register for Gfx commands */
69     volatile uint32_t   rbi_wptr;         /* +4   Write pointer (index) of RBI ring */
70     volatile uint32_t   rbi_rptr;         /* +8   Read pointer (index) of RBI ring */
71     volatile uint32_t   gpcom_wptr;       /* +12  Write pointer (index) of GPCOM ring */
72     volatile uint32_t   gpcom_rptr;       /* +16  Read pointer (index) of GPCOM ring */
73     volatile uint32_t   ring_addr_lo;     /* +20  bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
74     volatile uint32_t   ring_addr_hi;     /* +24  bits [63:32] of GPU Virtual of ring buffer (VMID=0) */
75     volatile uint32_t   ring_buf_size;    /* +28  Ring buffer size (in bytes) */
76 
77 };
78 
79 
80 /* Response flag is set in the command when command is completed by PSP.
81 *  Used in the GFX_CTRL.CmdResp.
82 *  When PSP GFX I/F is initialized, the flag is set.
83 */
84 #define GFX_FLAG_RESPONSE               0x80000000
85 
86 /* TEE Gfx Command IDs for the ring buffer interface. */
87 enum psp_gfx_cmd_id
88 {
89     GFX_CMD_ID_LOAD_TA            = 0x00000001,   /* load TA */
90     GFX_CMD_ID_UNLOAD_TA          = 0x00000002,   /* unload TA */
91     GFX_CMD_ID_INVOKE_CMD         = 0x00000003,   /* send command to TA */
92     GFX_CMD_ID_LOAD_ASD           = 0x00000004,   /* load ASD Driver */
93     GFX_CMD_ID_SETUP_TMR          = 0x00000005,   /* setup TMR region */
94     GFX_CMD_ID_LOAD_IP_FW         = 0x00000006,   /* load HW IP FW */
95     GFX_CMD_ID_DESTROY_TMR        = 0x00000007,   /* destroy TMR region */
96     GFX_CMD_ID_SAVE_RESTORE       = 0x00000008,   /* save/restore HW IP FW */
97     GFX_CMD_ID_SETUP_VMR          = 0x00000009,   /* setup VMR region */
98     GFX_CMD_ID_DESTROY_VMR        = 0x0000000A,   /* destroy VMR region */
99     GFX_CMD_ID_PROG_REG           = 0x0000000B,   /* program regs */
100     GFX_CMD_ID_GET_FW_ATTESTATION = 0x0000000F,   /* Query GPUVA of the Fw Attestation DB */
101     /* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */
102     GFX_CMD_ID_LOAD_TOC           = 0x00000020,   /* Load TOC and obtain TMR size */
103     GFX_CMD_ID_AUTOLOAD_RLC       = 0x00000021,   /* Indicates all graphics fw loaded, start RLC autoload */
104     GFX_CMD_ID_BOOT_CFG           = 0x00000022,   /* Boot Config */
105 };
106 
107 /* PSP boot config sub-commands */
108 enum psp_gfx_boot_config_cmd
109 {
110     BOOTCFG_CMD_SET         = 1, /* Set boot configuration settings */
111     BOOTCFG_CMD_GET         = 2, /* Get boot configuration settings */
112     BOOTCFG_CMD_INVALIDATE  = 3  /* Reset current boot configuration settings to VBIOS defaults */
113 };
114 
115 /* PSP boot config bitmask values */
116 enum psp_gfx_boot_config
117 {
118     BOOT_CONFIG_GECC = 0x1,
119 };
120 
121 /* Command to load Trusted Application binary into PSP OS. */
122 struct psp_gfx_cmd_load_ta
123 {
124     uint32_t        app_phy_addr_lo;        /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
125     uint32_t        app_phy_addr_hi;        /* bits [63:32] of the GPU Virtual address of the TA binary */
126     uint32_t        app_len;                /* length of the TA binary in bytes */
127     uint32_t        cmd_buf_phy_addr_lo;    /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
128     uint32_t        cmd_buf_phy_addr_hi;    /* bits [63:32] of the GPU Virtual address of CMD buffer */
129     uint32_t        cmd_buf_len;            /* length of the CMD buffer in bytes; must be multiple of 4 KB */
130 
131     /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided
132     *       for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead
133     *       of using global persistent buffer.
134     */
135 };
136 
137 
138 /* Command to Unload Trusted Application binary from PSP OS. */
139 struct psp_gfx_cmd_unload_ta
140 {
141     uint32_t        session_id;          /* Session ID of the loaded TA to be unloaded */
142 
143 };
144 
145 
146 /* Shared buffers for InvokeCommand.
147 */
148 struct psp_gfx_buf_desc
149 {
150     uint32_t        buf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
151     uint32_t        buf_phy_addr_hi;       /* bits [63:32] of GPU Virtual address of the buffer */
152     uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
153 
154 };
155 
156 /* Max number of descriptors for one shared buffer (in how many different
157 *  physical locations one shared buffer can be stored). If buffer is too much
158 *  fragmented, error will be returned.
159 */
160 #define GFX_BUF_MAX_DESC        64
161 
162 struct psp_gfx_buf_list
163 {
164     uint32_t                num_desc;                    /* number of buffer descriptors in the list */
165     uint32_t                total_size;                  /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
166     struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC];  /* list of buffer descriptors */
167 
168     /* total 776 bytes */
169 };
170 
171 /* Command to execute InvokeCommand entry point of the TA. */
172 struct psp_gfx_cmd_invoke_cmd
173 {
174     uint32_t                session_id;           /* Session ID of the TA to be executed */
175     uint32_t                ta_cmd_id;            /* Command ID to be sent to TA */
176     struct psp_gfx_buf_list buf;                  /* one indirect buffer (scatter/gather list) */
177 
178 };
179 
180 
181 /* Command to setup TMR region. */
182 struct psp_gfx_cmd_setup_tmr
183 {
184     uint32_t        buf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
185     uint32_t        buf_phy_addr_hi;       /* bits [63:32] of GPU Virtual address of TMR buffer */
186     uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB) */
187     union {
188 	struct {
189 		uint32_t	sriov_enabled:1; /* whether the device runs under SR-IOV*/
190 		uint32_t	virt_phy_addr:1; /* driver passes both virtual and physical address to PSP*/
191 		uint32_t	reserved:30;
192 	} bitfield;
193 	uint32_t        tmr_flags;
194     };
195     uint32_t        system_phy_addr_lo;        /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned) */
196     uint32_t        system_phy_addr_hi;        /* bits [63:32] of system physical address of TMR buffer */
197 
198 };
199 
200 /* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
201 enum psp_gfx_fw_type {
202 	GFX_FW_TYPE_NONE        = 0,    /* */
203 	GFX_FW_TYPE_CP_ME       = 1,    /* CP-ME                    VG + RV */
204 	GFX_FW_TYPE_CP_PFP      = 2,    /* CP-PFP                   VG + RV */
205 	GFX_FW_TYPE_CP_CE       = 3,    /* CP-CE                    VG + RV */
206 	GFX_FW_TYPE_CP_MEC      = 4,    /* CP-MEC FW                VG + RV */
207 	GFX_FW_TYPE_CP_MEC_ME1  = 5,    /* CP-MEC Jump Table 1      VG + RV */
208 	GFX_FW_TYPE_CP_MEC_ME2  = 6,    /* CP-MEC Jump Table 2      VG      */
209 	GFX_FW_TYPE_RLC_V       = 7,    /* RLC-V                    VG      */
210 	GFX_FW_TYPE_RLC_G       = 8,    /* RLC-G                    VG + RV */
211 	GFX_FW_TYPE_SDMA0       = 9,    /* SDMA0                    VG + RV */
212 	GFX_FW_TYPE_SDMA1       = 10,   /* SDMA1                    VG      */
213 	GFX_FW_TYPE_DMCU_ERAM   = 11,   /* DMCU-ERAM                VG + RV */
214 	GFX_FW_TYPE_DMCU_ISR    = 12,   /* DMCU-ISR                 VG + RV */
215 	GFX_FW_TYPE_VCN         = 13,   /* VCN                           RV */
216 	GFX_FW_TYPE_UVD         = 14,   /* UVD                      VG      */
217 	GFX_FW_TYPE_VCE         = 15,   /* VCE                      VG      */
218 	GFX_FW_TYPE_ISP         = 16,   /* ISP                           RV */
219 	GFX_FW_TYPE_ACP         = 17,   /* ACP                           RV */
220 	GFX_FW_TYPE_SMU         = 18,   /* SMU                      VG      */
221 	GFX_FW_TYPE_MMSCH       = 19,   /* MMSCH                    VG      */
222 	GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM        = 20,   /* RLC GPM                  VG + RV */
223 	GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM        = 21,   /* RLC SRM                  VG + RV */
224 	GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL       = 22,   /* RLC CNTL                 VG + RV */
225 	GFX_FW_TYPE_UVD1        = 23,   /* UVD1                     VG-20   */
226 	GFX_FW_TYPE_TOC         = 24,   /* TOC                      NV-10   */
227 	GFX_FW_TYPE_RLC_P                           = 25,   /* RLC P                    NV      */
228 	GFX_FW_TYPE_RLC_IRAM                        = 26,   /* RLC_IRAM                 NV      */
229 	GFX_FW_TYPE_GLOBAL_TAP_DELAYS               = 27,   /* GLOBAL TAP DELAYS        NV      */
230 	GFX_FW_TYPE_SE0_TAP_DELAYS                  = 28,   /* SE0 TAP DELAYS           NV      */
231 	GFX_FW_TYPE_SE1_TAP_DELAYS                  = 29,   /* SE1 TAP DELAYS           NV      */
232 	GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS      = 30,   /* GLOBAL SE0/1 SKEW DELAYS NV      */
233 	GFX_FW_TYPE_SDMA0_JT                        = 31,   /* SDMA0 JT                 NV      */
234 	GFX_FW_TYPE_SDMA1_JT                        = 32,   /* SDNA1 JT                 NV      */
235 	GFX_FW_TYPE_CP_MES                          = 33,   /* CP MES                   NV      */
236 	GFX_FW_TYPE_MES_STACK                       = 34,   /* MES STACK                NV      */
237 	GFX_FW_TYPE_RLC_SRM_DRAM_SR                 = 35,   /* RLC SRM DRAM             NV      */
238 	GFX_FW_TYPE_RLCG_SCRATCH_SR                 = 36,   /* RLCG SCRATCH             NV      */
239 	GFX_FW_TYPE_RLCP_SCRATCH_SR                 = 37,   /* RLCP SCRATCH             NV      */
240 	GFX_FW_TYPE_RLCV_SCRATCH_SR                 = 38,   /* RLCV SCRATCH             NV      */
241 	GFX_FW_TYPE_RLX6_DRAM_SR                    = 39,   /* RLX6 DRAM                NV      */
242 	GFX_FW_TYPE_SDMA0_PG_CONTEXT                = 40,   /* SDMA0 PG CONTEXT         NV      */
243 	GFX_FW_TYPE_SDMA1_PG_CONTEXT                = 41,   /* SDMA1 PG CONTEXT         NV      */
244 	GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM           = 42,   /* GLOBAL MUX SEL RAM       NV      */
245 	GFX_FW_TYPE_SE0_MUX_SELECT_RAM              = 43,   /* SE0 MUX SEL RAM          NV      */
246 	GFX_FW_TYPE_SE1_MUX_SELECT_RAM              = 44,   /* SE1 MUX SEL RAM          NV      */
247 	GFX_FW_TYPE_ACCUM_CTRL_RAM                  = 45,   /* ACCUM CTRL RAM           NV      */
248 	GFX_FW_TYPE_RLCP_CAM                        = 46,   /* RLCP CAM                 NV      */
249 	GFX_FW_TYPE_RLC_SPP_CAM_EXT                 = 47,   /* RLC SPP CAM EXT          NV      */
250 	GFX_FW_TYPE_RLC_DRAM_BOOT                   = 48,   /* RLC DRAM BOOT            NV      */
251 	GFX_FW_TYPE_VCN0_RAM                        = 49,   /* VCN_RAM                  NV + RN */
252 	GFX_FW_TYPE_VCN1_RAM                        = 50,   /* VCN_RAM                  NV + RN */
253 	GFX_FW_TYPE_DMUB                            = 51,   /* DMUB                          RN */
254 	GFX_FW_TYPE_SDMA2                           = 52,   /* SDMA2                    MI      */
255 	GFX_FW_TYPE_SDMA3                           = 53,   /* SDMA3                    MI      */
256 	GFX_FW_TYPE_SDMA4                           = 54,   /* SDMA4                    MI      */
257 	GFX_FW_TYPE_SDMA5                           = 55,   /* SDMA5                    MI      */
258 	GFX_FW_TYPE_SDMA6                           = 56,   /* SDMA6                    MI      */
259 	GFX_FW_TYPE_SDMA7                           = 57,   /* SDMA7                    MI      */
260 	GFX_FW_TYPE_VCN1                            = 58,   /* VCN1                     MI      */
261 	GFX_FW_TYPE_CAP                             = 62,   /* CAP_FW                           */
262 	GFX_FW_TYPE_REG_LIST                        = 67,   /* REG_LIST                 MI      */
263 	GFX_FW_TYPE_MAX
264 };
265 
266 /* Command to load HW IP FW. */
267 struct psp_gfx_cmd_load_ip_fw
268 {
269     uint32_t                fw_phy_addr_lo;    /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
270     uint32_t                fw_phy_addr_hi;    /* bits [63:32] of GPU Virtual address of FW location */
271     uint32_t                fw_size;           /* FW buffer size in bytes */
272     enum psp_gfx_fw_type    fw_type;           /* FW type */
273 
274 };
275 
276 /* Command to save/restore HW IP FW. */
277 struct psp_gfx_cmd_save_restore_ip_fw
278 {
279     uint32_t                save_fw;              /* if set, command is used for saving fw otherwise for resetoring*/
280     uint32_t                save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
281     uint32_t                save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */
282     uint32_t                buf_size;             /* Size of the save/restore buffer in bytes */
283     enum psp_gfx_fw_type    fw_type;              /* FW type */
284 };
285 
286 /* Command to setup register program */
287 struct psp_gfx_cmd_reg_prog {
288 	uint32_t	reg_value;
289 	uint32_t	reg_id;
290 };
291 
292 /* Command to load TOC */
293 struct psp_gfx_cmd_load_toc
294 {
295     uint32_t        toc_phy_addr_lo;        /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
296     uint32_t        toc_phy_addr_hi;        /* bits [63:32] of GPU Virtual address of FW location */
297     uint32_t        toc_size;               /* FW buffer size in bytes */
298 };
299 
300 /* Dynamic boot configuration */
301 struct psp_gfx_cmd_boot_cfg
302 {
303     uint32_t                        timestamp;            /* calendar time as number of seconds */
304     enum psp_gfx_boot_config_cmd    sub_cmd;              /* sub-command indicating how to process command data */
305     uint32_t                        boot_config;          /* dynamic boot configuration bitmask */
306     uint32_t                        boot_config_valid;    /* dynamic boot configuration valid bits bitmask */
307 };
308 
309 /* All GFX ring buffer commands. */
310 union psp_gfx_commands
311 {
312     struct psp_gfx_cmd_load_ta          cmd_load_ta;
313     struct psp_gfx_cmd_unload_ta        cmd_unload_ta;
314     struct psp_gfx_cmd_invoke_cmd       cmd_invoke_cmd;
315     struct psp_gfx_cmd_setup_tmr        cmd_setup_tmr;
316     struct psp_gfx_cmd_load_ip_fw       cmd_load_ip_fw;
317     struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw;
318     struct psp_gfx_cmd_reg_prog       cmd_setup_reg_prog;
319     struct psp_gfx_cmd_setup_tmr        cmd_setup_vmr;
320     struct psp_gfx_cmd_load_toc         cmd_load_toc;
321     struct psp_gfx_cmd_boot_cfg         boot_cfg;
322 };
323 
324 struct psp_gfx_uresp_reserved
325 {
326     uint32_t reserved[8];
327 };
328 
329 /* Command-specific response for Fw Attestation Db */
330 struct psp_gfx_uresp_fwar_db_info
331 {
332     uint32_t fwar_db_addr_lo;
333     uint32_t fwar_db_addr_hi;
334 };
335 
336 /* Command-specific response for boot config. */
337 struct psp_gfx_uresp_bootcfg {
338 	uint32_t boot_cfg;	/* boot config data */
339 };
340 
341 /* Union of command-specific responses for GPCOM ring. */
342 union psp_gfx_uresp {
343 	struct psp_gfx_uresp_reserved		reserved;
344 	struct psp_gfx_uresp_bootcfg		boot_cfg;
345 	struct psp_gfx_uresp_fwar_db_info	fwar_db_info;
346 };
347 
348 /* Structure of GFX Response buffer.
349 * For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI
350 * it is separate buffer.
351 */
352 struct psp_gfx_resp
353 {
354     uint32_t	status;		/* +0  status of command execution */
355     uint32_t	session_id;	/* +4  session ID in response to LoadTa command */
356     uint32_t	fw_addr_lo;	/* +8  bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */
357     uint32_t	fw_addr_hi;	/* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
358     uint32_t	tmr_size;	/* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */
359 
360     uint32_t	reserved[11];
361 
362     union psp_gfx_uresp uresp;      /* +64 response union containing command-specific responses */
363 
364     /* total 96 bytes */
365 };
366 
367 /* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi
368 *  and psp_gfx_rb_frame.cmd_buf_addr_lo.
369 */
370 struct psp_gfx_cmd_resp
371 {
372     uint32_t        buf_size;           /* +0  total size of the buffer in bytes */
373     uint32_t        buf_version;        /* +4  version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */
374     uint32_t        cmd_id;             /* +8  command ID */
375 
376     /* These fields are used for RBI only. They are all 0 in GPCOM commands
377     */
378     uint32_t        resp_buf_addr_lo;   /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
379     uint32_t        resp_buf_addr_hi;   /* +16 bits [63:32] of GPU Virtual address of response buffer */
380     uint32_t        resp_offset;        /* +20 offset within response buffer */
381     uint32_t        resp_buf_size;      /* +24 total size of the response buffer in bytes */
382 
383     union psp_gfx_commands  cmd;        /* +28 command specific structures */
384 
385     uint8_t         reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
386 
387     /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response
388     *        is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo.
389     */
390     struct psp_gfx_resp     resp;       /* +864 response */
391 
392     uint8_t         reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
393 
394     /* total size 1024 bytes */
395 };
396 
397 
398 #define FRAME_TYPE_DESTROY          1   /* frame sent by KMD driver when UMD Scheduler context is destroyed*/
399 
400 /* Structure of the Ring Buffer Frame */
401 struct psp_gfx_rb_frame
402 {
403     uint32_t    cmd_buf_addr_lo;    /* +0  bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
404     uint32_t    cmd_buf_addr_hi;    /* +4  bits [63:32] of GPU Virtual address of command buffer */
405     uint32_t    cmd_buf_size;       /* +8  command buffer size in bytes */
406     uint32_t    fence_addr_lo;      /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */
407     uint32_t    fence_addr_hi;      /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */
408     uint32_t    fence_value;        /* +20 Fence value */
409     uint32_t    sid_lo;             /* +24 bits [31:0] of SID value (used only for RBI frames) */
410     uint32_t    sid_hi;             /* +28 bits [63:32] of SID value (used only for RBI frames) */
411     uint8_t     vmid;               /* +32 VMID value used for mapping of all addresses for this frame */
412     uint8_t     frame_type;         /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */
413     uint8_t     reserved1[2];       /* +34 reserved, must be 0 */
414     uint32_t    reserved2[7];       /* +36 reserved, must be 0 */
415                 /* total 64 bytes */
416 };
417 
418 #define PSP_ERR_UNKNOWN_COMMAND 0x00000100
419 
420 enum tee_error_code {
421     TEE_SUCCESS                         = 0x00000000,
422     TEE_ERROR_NOT_SUPPORTED             = 0xFFFF000A,
423 };
424 
425 #endif /* _PSP_TEE_GFX_IF_H_ */
426