1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __NV_H__ 25 #define __NV_H__ 26 27 #include "nbio_v2_3.h" 28 29 void nv_grbm_select(struct amdgpu_device *adev, 30 u32 me, u32 pipe, u32 queue, u32 vmid); 31 void nv_set_virt_ops(struct amdgpu_device *adev); 32 int nv_set_ip_blocks(struct amdgpu_device *adev); 33 int navi10_reg_base_init(struct amdgpu_device *adev); 34 int navi14_reg_base_init(struct amdgpu_device *adev); 35 int navi12_reg_base_init(struct amdgpu_device *adev); 36 int sienna_cichlid_reg_base_init(struct amdgpu_device *adev); 37 void vangogh_reg_base_init(struct amdgpu_device *adev); 38 int dimgrey_cavefish_reg_base_init(struct amdgpu_device *adev); 39 #endif 40