1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang 24c6b6a421SHawking Zhang #ifndef __NV_H__ 25c6b6a421SHawking Zhang #define __NV_H__ 26c6b6a421SHawking Zhang 27c6b6a421SHawking Zhang #include "nbio_v2_3.h" 28c6b6a421SHawking Zhang 29c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 30c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid); 31c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev); 32c6b6a421SHawking Zhang int nv_set_ip_blocks(struct amdgpu_device *adev); 33c6b6a421SHawking Zhang int navi10_reg_base_init(struct amdgpu_device *adev); 34a0f6d926SXiaojie Yuan int navi14_reg_base_init(struct amdgpu_device *adev); 3503d0a073SXiaojie Yuan int navi12_reg_base_init(struct amdgpu_device *adev); 36dccdbf3fSLikun Gao int sienna_cichlid_reg_base_init(struct amdgpu_device *adev); 371f9dab43SHuang Rui void vangogh_reg_base_init(struct amdgpu_device *adev); 38*038d757bSTao Zhou int dimgrey_cavefish_reg_base_init(struct amdgpu_device *adev); 39c6b6a421SHawking Zhang #endif 40