1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "hdp/hdp_5_0_0_sh_mask.h" 43 #include "smuio/smuio_11_0_0_offset.h" 44 #include "mp/mp_11_0_offset.h" 45 46 #include "soc15.h" 47 #include "soc15_common.h" 48 #include "gmc_v10_0.h" 49 #include "gfxhub_v2_0.h" 50 #include "mmhub_v2_0.h" 51 #include "nbio_v2_3.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "dce_virtual.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 65 static const struct amd_ip_funcs nv_common_ip_funcs; 66 67 /* 68 * Indirect registers accessor 69 */ 70 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 71 { 72 unsigned long flags, address, data; 73 u32 r; 74 address = adev->nbio.funcs->get_pcie_index_offset(adev); 75 data = adev->nbio.funcs->get_pcie_data_offset(adev); 76 77 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 78 WREG32(address, reg); 79 (void)RREG32(address); 80 r = RREG32(data); 81 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 82 return r; 83 } 84 85 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 86 { 87 unsigned long flags, address, data; 88 89 address = adev->nbio.funcs->get_pcie_index_offset(adev); 90 data = adev->nbio.funcs->get_pcie_data_offset(adev); 91 92 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 93 WREG32(address, reg); 94 (void)RREG32(address); 95 WREG32(data, v); 96 (void)RREG32(data); 97 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 98 } 99 100 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 101 { 102 unsigned long flags, address, data; 103 u64 r; 104 address = adev->nbio.funcs->get_pcie_index_offset(adev); 105 data = adev->nbio.funcs->get_pcie_data_offset(adev); 106 107 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 108 /* read low 32 bit */ 109 WREG32(address, reg); 110 (void)RREG32(address); 111 r = RREG32(data); 112 113 /* read high 32 bit*/ 114 WREG32(address, reg + 4); 115 (void)RREG32(address); 116 r |= ((u64)RREG32(data) << 32); 117 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 118 return r; 119 } 120 121 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 122 { 123 unsigned long flags, address, data; 124 125 address = adev->nbio.funcs->get_pcie_index_offset(adev); 126 data = adev->nbio.funcs->get_pcie_data_offset(adev); 127 128 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 129 /* write low 32 bit */ 130 WREG32(address, reg); 131 (void)RREG32(address); 132 WREG32(data, (u32)(v & 0xffffffffULL)); 133 (void)RREG32(data); 134 135 /* write high 32 bit */ 136 WREG32(address, reg + 4); 137 (void)RREG32(address); 138 WREG32(data, (u32)(v >> 32)); 139 (void)RREG32(data); 140 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 141 } 142 143 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 144 { 145 unsigned long flags, address, data; 146 u32 r; 147 148 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 149 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 150 151 spin_lock_irqsave(&adev->didt_idx_lock, flags); 152 WREG32(address, (reg)); 153 r = RREG32(data); 154 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 155 return r; 156 } 157 158 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 159 { 160 unsigned long flags, address, data; 161 162 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 163 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 164 165 spin_lock_irqsave(&adev->didt_idx_lock, flags); 166 WREG32(address, (reg)); 167 WREG32(data, (v)); 168 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 169 } 170 171 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 172 { 173 return adev->nbio.funcs->get_memsize(adev); 174 } 175 176 static u32 nv_get_xclk(struct amdgpu_device *adev) 177 { 178 return adev->clock.spll.reference_freq; 179 } 180 181 182 void nv_grbm_select(struct amdgpu_device *adev, 183 u32 me, u32 pipe, u32 queue, u32 vmid) 184 { 185 u32 grbm_gfx_cntl = 0; 186 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 187 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 188 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 189 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 190 191 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 192 } 193 194 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 195 { 196 /* todo */ 197 } 198 199 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 200 { 201 /* todo */ 202 return false; 203 } 204 205 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 206 u8 *bios, u32 length_bytes) 207 { 208 u32 *dw_ptr; 209 u32 i, length_dw; 210 211 if (bios == NULL) 212 return false; 213 if (length_bytes == 0) 214 return false; 215 /* APU vbios image is part of sbios image */ 216 if (adev->flags & AMD_IS_APU) 217 return false; 218 219 dw_ptr = (u32 *)bios; 220 length_dw = ALIGN(length_bytes, 4) / 4; 221 222 /* set rom index to 0 */ 223 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 224 /* read out the rom data */ 225 for (i = 0; i < length_dw; i++) 226 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 227 228 return true; 229 } 230 231 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 232 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 233 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 234 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 235 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 236 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 237 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 238 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 239 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 240 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 241 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 242 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 243 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 244 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 245 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 246 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 247 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 248 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 249 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 250 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 251 }; 252 253 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 254 u32 sh_num, u32 reg_offset) 255 { 256 uint32_t val; 257 258 mutex_lock(&adev->grbm_idx_mutex); 259 if (se_num != 0xffffffff || sh_num != 0xffffffff) 260 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 261 262 val = RREG32(reg_offset); 263 264 if (se_num != 0xffffffff || sh_num != 0xffffffff) 265 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 266 mutex_unlock(&adev->grbm_idx_mutex); 267 return val; 268 } 269 270 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 271 bool indexed, u32 se_num, 272 u32 sh_num, u32 reg_offset) 273 { 274 if (indexed) { 275 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 276 } else { 277 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 278 return adev->gfx.config.gb_addr_config; 279 return RREG32(reg_offset); 280 } 281 } 282 283 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 284 u32 sh_num, u32 reg_offset, u32 *value) 285 { 286 uint32_t i; 287 struct soc15_allowed_register_entry *en; 288 289 *value = 0; 290 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 291 en = &nv_allowed_read_registers[i]; 292 if (reg_offset != 293 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 294 continue; 295 296 *value = nv_get_register_value(adev, 297 nv_allowed_read_registers[i].grbm_indexed, 298 se_num, sh_num, reg_offset); 299 return 0; 300 } 301 return -EINVAL; 302 } 303 304 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 305 { 306 u32 i; 307 int ret = 0; 308 309 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 310 311 /* disable BM */ 312 pci_clear_master(adev->pdev); 313 314 pci_save_state(adev->pdev); 315 316 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 317 dev_info(adev->dev, "GPU smu mode1 reset\n"); 318 ret = amdgpu_dpm_mode1_reset(adev); 319 } else { 320 dev_info(adev->dev, "GPU psp mode1 reset\n"); 321 ret = psp_gpu_reset(adev); 322 } 323 324 if (ret) 325 dev_err(adev->dev, "GPU mode1 reset failed\n"); 326 pci_restore_state(adev->pdev); 327 328 /* wait for asic to come out of reset */ 329 for (i = 0; i < adev->usec_timeout; i++) { 330 u32 memsize = adev->nbio.funcs->get_memsize(adev); 331 332 if (memsize != 0xffffffff) 333 break; 334 udelay(1); 335 } 336 337 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 338 339 return ret; 340 } 341 342 static bool nv_asic_supports_baco(struct amdgpu_device *adev) 343 { 344 struct smu_context *smu = &adev->smu; 345 346 if (smu_baco_is_support(smu)) 347 return true; 348 else 349 return false; 350 } 351 352 static enum amd_reset_method 353 nv_asic_reset_method(struct amdgpu_device *adev) 354 { 355 struct smu_context *smu = &adev->smu; 356 357 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 358 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 359 return amdgpu_reset_method; 360 361 if (amdgpu_reset_method != -1) 362 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 363 amdgpu_reset_method); 364 365 switch (adev->asic_type) { 366 case CHIP_SIENNA_CICHLID: 367 case CHIP_NAVY_FLOUNDER: 368 return AMD_RESET_METHOD_MODE1; 369 default: 370 if (smu_baco_is_support(smu)) 371 return AMD_RESET_METHOD_BACO; 372 else 373 return AMD_RESET_METHOD_MODE1; 374 } 375 } 376 377 static int nv_asic_reset(struct amdgpu_device *adev) 378 { 379 int ret = 0; 380 struct smu_context *smu = &adev->smu; 381 382 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 383 dev_info(adev->dev, "GPU BACO reset\n"); 384 385 ret = smu_baco_enter(smu); 386 if (ret) 387 return ret; 388 ret = smu_baco_exit(smu); 389 if (ret) 390 return ret; 391 } else 392 ret = nv_asic_mode1_reset(adev); 393 394 return ret; 395 } 396 397 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 398 { 399 /* todo */ 400 return 0; 401 } 402 403 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 404 { 405 /* todo */ 406 return 0; 407 } 408 409 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 410 { 411 if (pci_is_root_bus(adev->pdev->bus)) 412 return; 413 414 if (amdgpu_pcie_gen2 == 0) 415 return; 416 417 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 418 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 419 return; 420 421 /* todo */ 422 } 423 424 static void nv_program_aspm(struct amdgpu_device *adev) 425 { 426 427 if (amdgpu_aspm == 0) 428 return; 429 430 /* todo */ 431 } 432 433 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 434 bool enable) 435 { 436 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 437 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 438 } 439 440 static const struct amdgpu_ip_block_version nv_common_ip_block = 441 { 442 .type = AMD_IP_BLOCK_TYPE_COMMON, 443 .major = 1, 444 .minor = 0, 445 .rev = 0, 446 .funcs = &nv_common_ip_funcs, 447 }; 448 449 static int nv_reg_base_init(struct amdgpu_device *adev) 450 { 451 int r; 452 453 if (amdgpu_discovery) { 454 r = amdgpu_discovery_reg_base_init(adev); 455 if (r) { 456 DRM_WARN("failed to init reg base from ip discovery table, " 457 "fallback to legacy init method\n"); 458 goto legacy_init; 459 } 460 461 return 0; 462 } 463 464 legacy_init: 465 switch (adev->asic_type) { 466 case CHIP_NAVI10: 467 navi10_reg_base_init(adev); 468 break; 469 case CHIP_NAVI14: 470 navi14_reg_base_init(adev); 471 break; 472 case CHIP_NAVI12: 473 navi12_reg_base_init(adev); 474 break; 475 case CHIP_SIENNA_CICHLID: 476 case CHIP_NAVY_FLOUNDER: 477 sienna_cichlid_reg_base_init(adev); 478 break; 479 default: 480 return -EINVAL; 481 } 482 483 return 0; 484 } 485 486 void nv_set_virt_ops(struct amdgpu_device *adev) 487 { 488 adev->virt.ops = &xgpu_nv_virt_ops; 489 } 490 491 int nv_set_ip_blocks(struct amdgpu_device *adev) 492 { 493 int r; 494 495 adev->nbio.funcs = &nbio_v2_3_funcs; 496 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 497 498 if (adev->asic_type == CHIP_SIENNA_CICHLID) 499 adev->gmc.xgmi.supported = true; 500 501 /* Set IP register base before any HW register access */ 502 r = nv_reg_base_init(adev); 503 if (r) 504 return r; 505 506 switch (adev->asic_type) { 507 case CHIP_NAVI10: 508 case CHIP_NAVI14: 509 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 510 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 511 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 512 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 513 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 514 !amdgpu_sriov_vf(adev)) 515 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 516 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 517 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 518 #if defined(CONFIG_DRM_AMD_DC) 519 else if (amdgpu_device_has_dc_support(adev)) 520 amdgpu_device_ip_block_add(adev, &dm_ip_block); 521 #endif 522 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 523 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 524 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 525 !amdgpu_sriov_vf(adev)) 526 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 527 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 528 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 529 if (adev->enable_mes) 530 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 531 break; 532 case CHIP_NAVI12: 533 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 534 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 535 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 536 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 537 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 538 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 539 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 540 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 541 #if defined(CONFIG_DRM_AMD_DC) 542 else if (amdgpu_device_has_dc_support(adev)) 543 amdgpu_device_ip_block_add(adev, &dm_ip_block); 544 #endif 545 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 546 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 547 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 548 !amdgpu_sriov_vf(adev)) 549 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 550 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 551 if (!amdgpu_sriov_vf(adev)) 552 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 553 break; 554 case CHIP_SIENNA_CICHLID: 555 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 556 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 557 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 558 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 559 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 560 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 561 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 562 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 563 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 564 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 565 #if defined(CONFIG_DRM_AMD_DC) 566 else if (amdgpu_device_has_dc_support(adev)) 567 amdgpu_device_ip_block_add(adev, &dm_ip_block); 568 #endif 569 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 570 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 571 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 572 if (!amdgpu_sriov_vf(adev)) 573 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 574 575 if (adev->enable_mes) 576 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 577 break; 578 case CHIP_NAVY_FLOUNDER: 579 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 580 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 581 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 582 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 583 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 584 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 585 is_support_sw_smu(adev)) 586 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 587 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 588 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 589 #if defined(CONFIG_DRM_AMD_DC) 590 else if (amdgpu_device_has_dc_support(adev)) 591 amdgpu_device_ip_block_add(adev, &dm_ip_block); 592 #endif 593 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 594 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 595 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 596 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 597 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 598 is_support_sw_smu(adev)) 599 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 600 break; 601 default: 602 return -EINVAL; 603 } 604 605 return 0; 606 } 607 608 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 609 { 610 return adev->nbio.funcs->get_rev_id(adev); 611 } 612 613 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 614 { 615 adev->nbio.funcs->hdp_flush(adev, ring); 616 } 617 618 static void nv_invalidate_hdp(struct amdgpu_device *adev, 619 struct amdgpu_ring *ring) 620 { 621 if (!ring || !ring->funcs->emit_wreg) { 622 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 623 } else { 624 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 625 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 626 } 627 } 628 629 static bool nv_need_full_reset(struct amdgpu_device *adev) 630 { 631 return true; 632 } 633 634 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 635 { 636 u32 sol_reg; 637 638 if (adev->flags & AMD_IS_APU) 639 return false; 640 641 /* Check sOS sign of life register to confirm sys driver and sOS 642 * are already been loaded. 643 */ 644 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 645 if (sol_reg) 646 return true; 647 648 return false; 649 } 650 651 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 652 { 653 654 /* TODO 655 * dummy implement for pcie_replay_count sysfs interface 656 * */ 657 658 return 0; 659 } 660 661 static void nv_init_doorbell_index(struct amdgpu_device *adev) 662 { 663 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 664 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 665 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 666 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 667 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 668 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 669 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 670 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 671 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 672 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 673 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 674 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 675 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 676 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 677 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 678 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 679 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 680 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 681 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 682 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 683 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 684 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 685 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 686 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 687 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 688 689 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 690 adev->doorbell_index.sdma_doorbell_range = 20; 691 } 692 693 static const struct amdgpu_asic_funcs nv_asic_funcs = 694 { 695 .read_disabled_bios = &nv_read_disabled_bios, 696 .read_bios_from_rom = &nv_read_bios_from_rom, 697 .read_register = &nv_read_register, 698 .reset = &nv_asic_reset, 699 .reset_method = &nv_asic_reset_method, 700 .set_vga_state = &nv_vga_set_state, 701 .get_xclk = &nv_get_xclk, 702 .set_uvd_clocks = &nv_set_uvd_clocks, 703 .set_vce_clocks = &nv_set_vce_clocks, 704 .get_config_memsize = &nv_get_config_memsize, 705 .flush_hdp = &nv_flush_hdp, 706 .invalidate_hdp = &nv_invalidate_hdp, 707 .init_doorbell_index = &nv_init_doorbell_index, 708 .need_full_reset = &nv_need_full_reset, 709 .need_reset_on_init = &nv_need_reset_on_init, 710 .get_pcie_replay_count = &nv_get_pcie_replay_count, 711 .supports_baco = &nv_asic_supports_baco, 712 }; 713 714 static int nv_common_early_init(void *handle) 715 { 716 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 717 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 718 719 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 720 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 721 adev->smc_rreg = NULL; 722 adev->smc_wreg = NULL; 723 adev->pcie_rreg = &nv_pcie_rreg; 724 adev->pcie_wreg = &nv_pcie_wreg; 725 adev->pcie_rreg64 = &nv_pcie_rreg64; 726 adev->pcie_wreg64 = &nv_pcie_wreg64; 727 728 /* TODO: will add them during VCN v2 implementation */ 729 adev->uvd_ctx_rreg = NULL; 730 adev->uvd_ctx_wreg = NULL; 731 732 adev->didt_rreg = &nv_didt_rreg; 733 adev->didt_wreg = &nv_didt_wreg; 734 735 adev->asic_funcs = &nv_asic_funcs; 736 737 adev->rev_id = nv_get_rev_id(adev); 738 adev->external_rev_id = 0xff; 739 switch (adev->asic_type) { 740 case CHIP_NAVI10: 741 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 742 AMD_CG_SUPPORT_GFX_CGCG | 743 AMD_CG_SUPPORT_IH_CG | 744 AMD_CG_SUPPORT_HDP_MGCG | 745 AMD_CG_SUPPORT_HDP_LS | 746 AMD_CG_SUPPORT_SDMA_MGCG | 747 AMD_CG_SUPPORT_SDMA_LS | 748 AMD_CG_SUPPORT_MC_MGCG | 749 AMD_CG_SUPPORT_MC_LS | 750 AMD_CG_SUPPORT_ATHUB_MGCG | 751 AMD_CG_SUPPORT_ATHUB_LS | 752 AMD_CG_SUPPORT_VCN_MGCG | 753 AMD_CG_SUPPORT_JPEG_MGCG | 754 AMD_CG_SUPPORT_BIF_MGCG | 755 AMD_CG_SUPPORT_BIF_LS; 756 adev->pg_flags = AMD_PG_SUPPORT_VCN | 757 AMD_PG_SUPPORT_VCN_DPG | 758 AMD_PG_SUPPORT_JPEG | 759 AMD_PG_SUPPORT_ATHUB; 760 adev->external_rev_id = adev->rev_id + 0x1; 761 break; 762 case CHIP_NAVI14: 763 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 764 AMD_CG_SUPPORT_GFX_CGCG | 765 AMD_CG_SUPPORT_IH_CG | 766 AMD_CG_SUPPORT_HDP_MGCG | 767 AMD_CG_SUPPORT_HDP_LS | 768 AMD_CG_SUPPORT_SDMA_MGCG | 769 AMD_CG_SUPPORT_SDMA_LS | 770 AMD_CG_SUPPORT_MC_MGCG | 771 AMD_CG_SUPPORT_MC_LS | 772 AMD_CG_SUPPORT_ATHUB_MGCG | 773 AMD_CG_SUPPORT_ATHUB_LS | 774 AMD_CG_SUPPORT_VCN_MGCG | 775 AMD_CG_SUPPORT_JPEG_MGCG | 776 AMD_CG_SUPPORT_BIF_MGCG | 777 AMD_CG_SUPPORT_BIF_LS; 778 adev->pg_flags = AMD_PG_SUPPORT_VCN | 779 AMD_PG_SUPPORT_JPEG | 780 AMD_PG_SUPPORT_VCN_DPG; 781 adev->external_rev_id = adev->rev_id + 20; 782 break; 783 case CHIP_NAVI12: 784 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 785 AMD_CG_SUPPORT_GFX_MGLS | 786 AMD_CG_SUPPORT_GFX_CGCG | 787 AMD_CG_SUPPORT_GFX_CP_LS | 788 AMD_CG_SUPPORT_GFX_RLC_LS | 789 AMD_CG_SUPPORT_IH_CG | 790 AMD_CG_SUPPORT_HDP_MGCG | 791 AMD_CG_SUPPORT_HDP_LS | 792 AMD_CG_SUPPORT_SDMA_MGCG | 793 AMD_CG_SUPPORT_SDMA_LS | 794 AMD_CG_SUPPORT_MC_MGCG | 795 AMD_CG_SUPPORT_MC_LS | 796 AMD_CG_SUPPORT_ATHUB_MGCG | 797 AMD_CG_SUPPORT_ATHUB_LS | 798 AMD_CG_SUPPORT_VCN_MGCG | 799 AMD_CG_SUPPORT_JPEG_MGCG; 800 adev->pg_flags = AMD_PG_SUPPORT_VCN | 801 AMD_PG_SUPPORT_VCN_DPG | 802 AMD_PG_SUPPORT_JPEG | 803 AMD_PG_SUPPORT_ATHUB; 804 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 805 * as a consequence, the rev_id and external_rev_id are wrong. 806 * workaround it by hardcoding rev_id to 0 (default value). 807 */ 808 if (amdgpu_sriov_vf(adev)) 809 adev->rev_id = 0; 810 adev->external_rev_id = adev->rev_id + 0xa; 811 break; 812 case CHIP_SIENNA_CICHLID: 813 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 814 AMD_CG_SUPPORT_GFX_CGCG | 815 AMD_CG_SUPPORT_GFX_3D_CGCG | 816 AMD_CG_SUPPORT_MC_MGCG | 817 AMD_CG_SUPPORT_VCN_MGCG | 818 AMD_CG_SUPPORT_JPEG_MGCG | 819 AMD_CG_SUPPORT_HDP_MGCG | 820 AMD_CG_SUPPORT_HDP_LS | 821 AMD_CG_SUPPORT_IH_CG | 822 AMD_CG_SUPPORT_MC_LS; 823 adev->pg_flags = AMD_PG_SUPPORT_VCN | 824 AMD_PG_SUPPORT_VCN_DPG | 825 AMD_PG_SUPPORT_JPEG | 826 AMD_PG_SUPPORT_ATHUB | 827 AMD_PG_SUPPORT_MMHUB; 828 if (amdgpu_sriov_vf(adev)) { 829 /* hypervisor control CG and PG enablement */ 830 adev->cg_flags = 0; 831 adev->pg_flags = 0; 832 } 833 adev->external_rev_id = adev->rev_id + 0x28; 834 break; 835 case CHIP_NAVY_FLOUNDER: 836 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 837 AMD_CG_SUPPORT_GFX_CGCG | 838 AMD_CG_SUPPORT_GFX_3D_CGCG | 839 AMD_CG_SUPPORT_VCN_MGCG | 840 AMD_CG_SUPPORT_JPEG_MGCG | 841 AMD_CG_SUPPORT_MC_MGCG | 842 AMD_CG_SUPPORT_MC_LS | 843 AMD_CG_SUPPORT_HDP_MGCG | 844 AMD_CG_SUPPORT_HDP_LS | 845 AMD_CG_SUPPORT_IH_CG; 846 adev->pg_flags = AMD_PG_SUPPORT_VCN | 847 AMD_PG_SUPPORT_VCN_DPG | 848 AMD_PG_SUPPORT_JPEG | 849 AMD_PG_SUPPORT_ATHUB | 850 AMD_PG_SUPPORT_MMHUB; 851 adev->external_rev_id = adev->rev_id + 0x32; 852 break; 853 854 default: 855 /* FIXME: not supported yet */ 856 return -EINVAL; 857 } 858 859 if (amdgpu_sriov_vf(adev)) { 860 amdgpu_virt_init_setting(adev); 861 xgpu_nv_mailbox_set_irq_funcs(adev); 862 } 863 864 return 0; 865 } 866 867 static int nv_common_late_init(void *handle) 868 { 869 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 870 871 if (amdgpu_sriov_vf(adev)) 872 xgpu_nv_mailbox_get_irq(adev); 873 874 return 0; 875 } 876 877 static int nv_common_sw_init(void *handle) 878 { 879 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 880 881 if (amdgpu_sriov_vf(adev)) 882 xgpu_nv_mailbox_add_irq_id(adev); 883 884 return 0; 885 } 886 887 static int nv_common_sw_fini(void *handle) 888 { 889 return 0; 890 } 891 892 static int nv_common_hw_init(void *handle) 893 { 894 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 895 896 /* enable pcie gen2/3 link */ 897 nv_pcie_gen3_enable(adev); 898 /* enable aspm */ 899 nv_program_aspm(adev); 900 /* setup nbio registers */ 901 adev->nbio.funcs->init_registers(adev); 902 /* remap HDP registers to a hole in mmio space, 903 * for the purpose of expose those registers 904 * to process space 905 */ 906 if (adev->nbio.funcs->remap_hdp_registers) 907 adev->nbio.funcs->remap_hdp_registers(adev); 908 /* enable the doorbell aperture */ 909 nv_enable_doorbell_aperture(adev, true); 910 911 return 0; 912 } 913 914 static int nv_common_hw_fini(void *handle) 915 { 916 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 917 918 /* disable the doorbell aperture */ 919 nv_enable_doorbell_aperture(adev, false); 920 921 return 0; 922 } 923 924 static int nv_common_suspend(void *handle) 925 { 926 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 927 928 return nv_common_hw_fini(adev); 929 } 930 931 static int nv_common_resume(void *handle) 932 { 933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 934 935 return nv_common_hw_init(adev); 936 } 937 938 static bool nv_common_is_idle(void *handle) 939 { 940 return true; 941 } 942 943 static int nv_common_wait_for_idle(void *handle) 944 { 945 return 0; 946 } 947 948 static int nv_common_soft_reset(void *handle) 949 { 950 return 0; 951 } 952 953 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 954 bool enable) 955 { 956 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 957 uint32_t hdp_mem_pwr_cntl; 958 959 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 960 AMD_CG_SUPPORT_HDP_DS | 961 AMD_CG_SUPPORT_HDP_SD))) 962 return; 963 964 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 965 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 966 967 /* Before doing clock/power mode switch, 968 * forced on IPH & RC clock */ 969 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 970 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 971 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 972 RC_MEM_CLK_SOFT_OVERRIDE, 1); 973 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 974 975 /* HDP 5.0 doesn't support dynamic power mode switch, 976 * disable clock and power gating before any changing */ 977 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 978 IPH_MEM_POWER_CTRL_EN, 0); 979 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 980 IPH_MEM_POWER_LS_EN, 0); 981 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 982 IPH_MEM_POWER_DS_EN, 0); 983 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 984 IPH_MEM_POWER_SD_EN, 0); 985 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 986 RC_MEM_POWER_CTRL_EN, 0); 987 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 988 RC_MEM_POWER_LS_EN, 0); 989 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 990 RC_MEM_POWER_DS_EN, 0); 991 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 992 RC_MEM_POWER_SD_EN, 0); 993 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 994 995 /* only one clock gating mode (LS/DS/SD) can be enabled */ 996 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 997 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 998 HDP_MEM_POWER_CTRL, 999 IPH_MEM_POWER_LS_EN, enable); 1000 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1001 HDP_MEM_POWER_CTRL, 1002 RC_MEM_POWER_LS_EN, enable); 1003 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 1004 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1005 HDP_MEM_POWER_CTRL, 1006 IPH_MEM_POWER_DS_EN, enable); 1007 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1008 HDP_MEM_POWER_CTRL, 1009 RC_MEM_POWER_DS_EN, enable); 1010 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 1011 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1012 HDP_MEM_POWER_CTRL, 1013 IPH_MEM_POWER_SD_EN, enable); 1014 /* RC should not use shut down mode, fallback to ds */ 1015 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1016 HDP_MEM_POWER_CTRL, 1017 RC_MEM_POWER_DS_EN, enable); 1018 } 1019 1020 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 1021 * be set for SRAM LS/DS/SD */ 1022 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 1023 AMD_CG_SUPPORT_HDP_SD)) { 1024 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1025 IPH_MEM_POWER_CTRL_EN, 1); 1026 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1027 RC_MEM_POWER_CTRL_EN, 1); 1028 } 1029 1030 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1031 1032 /* restore IPH & RC clock override after clock/power mode changing */ 1033 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 1034 } 1035 1036 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 1037 bool enable) 1038 { 1039 uint32_t hdp_clk_cntl; 1040 1041 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1042 return; 1043 1044 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1045 1046 if (enable) { 1047 hdp_clk_cntl &= 1048 ~(uint32_t) 1049 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1050 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1051 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1052 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1053 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1054 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 1055 } else { 1056 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1057 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1058 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1059 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1060 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1061 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 1062 } 1063 1064 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1065 } 1066 1067 static int nv_common_set_clockgating_state(void *handle, 1068 enum amd_clockgating_state state) 1069 { 1070 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1071 1072 if (amdgpu_sriov_vf(adev)) 1073 return 0; 1074 1075 switch (adev->asic_type) { 1076 case CHIP_NAVI10: 1077 case CHIP_NAVI14: 1078 case CHIP_NAVI12: 1079 case CHIP_SIENNA_CICHLID: 1080 case CHIP_NAVY_FLOUNDER: 1081 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1082 state == AMD_CG_STATE_GATE); 1083 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1084 state == AMD_CG_STATE_GATE); 1085 nv_update_hdp_mem_power_gating(adev, 1086 state == AMD_CG_STATE_GATE); 1087 nv_update_hdp_clock_gating(adev, 1088 state == AMD_CG_STATE_GATE); 1089 break; 1090 default: 1091 break; 1092 } 1093 return 0; 1094 } 1095 1096 static int nv_common_set_powergating_state(void *handle, 1097 enum amd_powergating_state state) 1098 { 1099 /* TODO */ 1100 return 0; 1101 } 1102 1103 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1104 { 1105 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1106 uint32_t tmp; 1107 1108 if (amdgpu_sriov_vf(adev)) 1109 *flags = 0; 1110 1111 adev->nbio.funcs->get_clockgating_state(adev, flags); 1112 1113 /* AMD_CG_SUPPORT_HDP_MGCG */ 1114 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1115 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1116 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1117 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1118 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1119 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1120 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 1121 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1122 1123 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 1124 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1125 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 1126 *flags |= AMD_CG_SUPPORT_HDP_LS; 1127 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1128 *flags |= AMD_CG_SUPPORT_HDP_DS; 1129 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1130 *flags |= AMD_CG_SUPPORT_HDP_SD; 1131 1132 return; 1133 } 1134 1135 static const struct amd_ip_funcs nv_common_ip_funcs = { 1136 .name = "nv_common", 1137 .early_init = nv_common_early_init, 1138 .late_init = nv_common_late_init, 1139 .sw_init = nv_common_sw_init, 1140 .sw_fini = nv_common_sw_fini, 1141 .hw_init = nv_common_hw_init, 1142 .hw_fini = nv_common_hw_fini, 1143 .suspend = nv_common_suspend, 1144 .resume = nv_common_resume, 1145 .is_idle = nv_common_is_idle, 1146 .wait_for_idle = nv_common_wait_for_idle, 1147 .soft_reset = nv_common_soft_reset, 1148 .set_clockgating_state = nv_common_set_clockgating_state, 1149 .set_powergating_state = nv_common_set_powergating_state, 1150 .get_clockgating_state = nv_common_get_clockgating_state, 1151 }; 1152