1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "hdp/hdp_5_0_0_sh_mask.h" 43 #include "smuio/smuio_11_0_0_offset.h" 44 #include "mp/mp_11_0_offset.h" 45 46 #include "soc15.h" 47 #include "soc15_common.h" 48 #include "gmc_v10_0.h" 49 #include "gfxhub_v2_0.h" 50 #include "mmhub_v2_0.h" 51 #include "nbio_v2_3.h" 52 #include "nbio_v7_2.h" 53 #include "nv.h" 54 #include "navi10_ih.h" 55 #include "gfx_v10_0.h" 56 #include "sdma_v5_0.h" 57 #include "sdma_v5_2.h" 58 #include "vcn_v2_0.h" 59 #include "jpeg_v2_0.h" 60 #include "vcn_v3_0.h" 61 #include "jpeg_v3_0.h" 62 #include "dce_virtual.h" 63 #include "mes_v10_1.h" 64 #include "mxgpu_nv.h" 65 66 static const struct amd_ip_funcs nv_common_ip_funcs; 67 68 /* 69 * Indirect registers accessor 70 */ 71 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 72 { 73 unsigned long address, data; 74 address = adev->nbio.funcs->get_pcie_index_offset(adev); 75 data = adev->nbio.funcs->get_pcie_data_offset(adev); 76 77 return amdgpu_device_indirect_rreg(adev, address, data, reg); 78 } 79 80 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 81 { 82 unsigned long address, data; 83 84 address = adev->nbio.funcs->get_pcie_index_offset(adev); 85 data = adev->nbio.funcs->get_pcie_data_offset(adev); 86 87 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 88 } 89 90 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 91 { 92 unsigned long address, data; 93 address = adev->nbio.funcs->get_pcie_index_offset(adev); 94 data = adev->nbio.funcs->get_pcie_data_offset(adev); 95 96 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 97 } 98 99 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 100 { 101 unsigned long flags, address, data; 102 u32 r; 103 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 104 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 105 106 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 107 WREG32(address, reg * 4); 108 (void)RREG32(address); 109 r = RREG32(data); 110 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 111 return r; 112 } 113 114 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 115 { 116 unsigned long address, data; 117 118 address = adev->nbio.funcs->get_pcie_index_offset(adev); 119 data = adev->nbio.funcs->get_pcie_data_offset(adev); 120 121 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 122 } 123 124 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 125 { 126 unsigned long flags, address, data; 127 128 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 129 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 130 131 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 132 WREG32(address, reg * 4); 133 (void)RREG32(address); 134 WREG32(data, v); 135 (void)RREG32(data); 136 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 137 } 138 139 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 140 { 141 unsigned long flags, address, data; 142 u32 r; 143 144 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 145 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 146 147 spin_lock_irqsave(&adev->didt_idx_lock, flags); 148 WREG32(address, (reg)); 149 r = RREG32(data); 150 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 151 return r; 152 } 153 154 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 155 { 156 unsigned long flags, address, data; 157 158 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 159 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 160 161 spin_lock_irqsave(&adev->didt_idx_lock, flags); 162 WREG32(address, (reg)); 163 WREG32(data, (v)); 164 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 165 } 166 167 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 168 { 169 return adev->nbio.funcs->get_memsize(adev); 170 } 171 172 static u32 nv_get_xclk(struct amdgpu_device *adev) 173 { 174 return adev->clock.spll.reference_freq; 175 } 176 177 178 void nv_grbm_select(struct amdgpu_device *adev, 179 u32 me, u32 pipe, u32 queue, u32 vmid) 180 { 181 u32 grbm_gfx_cntl = 0; 182 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 183 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 184 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 185 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 186 187 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 188 } 189 190 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 191 { 192 /* todo */ 193 } 194 195 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 196 { 197 /* todo */ 198 return false; 199 } 200 201 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 202 u8 *bios, u32 length_bytes) 203 { 204 u32 *dw_ptr; 205 u32 i, length_dw; 206 207 if (bios == NULL) 208 return false; 209 if (length_bytes == 0) 210 return false; 211 /* APU vbios image is part of sbios image */ 212 if (adev->flags & AMD_IS_APU) 213 return false; 214 215 dw_ptr = (u32 *)bios; 216 length_dw = ALIGN(length_bytes, 4) / 4; 217 218 /* set rom index to 0 */ 219 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 220 /* read out the rom data */ 221 for (i = 0; i < length_dw; i++) 222 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 223 224 return true; 225 } 226 227 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 228 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 229 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 230 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 231 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 232 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 233 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 234 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 235 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 236 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 237 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 238 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 239 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 240 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 241 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 242 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 243 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 244 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 245 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 246 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 247 }; 248 249 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 250 u32 sh_num, u32 reg_offset) 251 { 252 uint32_t val; 253 254 mutex_lock(&adev->grbm_idx_mutex); 255 if (se_num != 0xffffffff || sh_num != 0xffffffff) 256 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 257 258 val = RREG32(reg_offset); 259 260 if (se_num != 0xffffffff || sh_num != 0xffffffff) 261 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 262 mutex_unlock(&adev->grbm_idx_mutex); 263 return val; 264 } 265 266 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 267 bool indexed, u32 se_num, 268 u32 sh_num, u32 reg_offset) 269 { 270 if (indexed) { 271 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 272 } else { 273 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 274 return adev->gfx.config.gb_addr_config; 275 return RREG32(reg_offset); 276 } 277 } 278 279 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 280 u32 sh_num, u32 reg_offset, u32 *value) 281 { 282 uint32_t i; 283 struct soc15_allowed_register_entry *en; 284 285 *value = 0; 286 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 287 en = &nv_allowed_read_registers[i]; 288 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 289 reg_offset != 290 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 291 continue; 292 293 *value = nv_get_register_value(adev, 294 nv_allowed_read_registers[i].grbm_indexed, 295 se_num, sh_num, reg_offset); 296 return 0; 297 } 298 return -EINVAL; 299 } 300 301 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 302 { 303 u32 i; 304 int ret = 0; 305 306 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 307 308 /* disable BM */ 309 pci_clear_master(adev->pdev); 310 311 amdgpu_device_cache_pci_state(adev->pdev); 312 313 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 314 dev_info(adev->dev, "GPU smu mode1 reset\n"); 315 ret = amdgpu_dpm_mode1_reset(adev); 316 } else { 317 dev_info(adev->dev, "GPU psp mode1 reset\n"); 318 ret = psp_gpu_reset(adev); 319 } 320 321 if (ret) 322 dev_err(adev->dev, "GPU mode1 reset failed\n"); 323 amdgpu_device_load_pci_state(adev->pdev); 324 325 /* wait for asic to come out of reset */ 326 for (i = 0; i < adev->usec_timeout; i++) { 327 u32 memsize = adev->nbio.funcs->get_memsize(adev); 328 329 if (memsize != 0xffffffff) 330 break; 331 udelay(1); 332 } 333 334 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 335 336 return ret; 337 } 338 339 static bool nv_asic_supports_baco(struct amdgpu_device *adev) 340 { 341 struct smu_context *smu = &adev->smu; 342 343 if (smu_baco_is_support(smu)) 344 return true; 345 else 346 return false; 347 } 348 349 static enum amd_reset_method 350 nv_asic_reset_method(struct amdgpu_device *adev) 351 { 352 struct smu_context *smu = &adev->smu; 353 354 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 355 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 356 return amdgpu_reset_method; 357 358 if (amdgpu_reset_method != -1) 359 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 360 amdgpu_reset_method); 361 362 switch (adev->asic_type) { 363 case CHIP_SIENNA_CICHLID: 364 case CHIP_NAVY_FLOUNDER: 365 case CHIP_DIMGREY_CAVEFISH: 366 return AMD_RESET_METHOD_MODE1; 367 default: 368 if (smu_baco_is_support(smu)) 369 return AMD_RESET_METHOD_BACO; 370 else 371 return AMD_RESET_METHOD_MODE1; 372 } 373 } 374 375 static int nv_asic_reset(struct amdgpu_device *adev) 376 { 377 int ret = 0; 378 struct smu_context *smu = &adev->smu; 379 380 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 381 dev_info(adev->dev, "BACO reset\n"); 382 383 ret = smu_baco_enter(smu); 384 if (ret) 385 return ret; 386 ret = smu_baco_exit(smu); 387 if (ret) 388 return ret; 389 } else { 390 dev_info(adev->dev, "MODE1 reset\n"); 391 ret = nv_asic_mode1_reset(adev); 392 } 393 394 return ret; 395 } 396 397 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 398 { 399 /* todo */ 400 return 0; 401 } 402 403 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 404 { 405 /* todo */ 406 return 0; 407 } 408 409 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 410 { 411 if (pci_is_root_bus(adev->pdev->bus)) 412 return; 413 414 if (amdgpu_pcie_gen2 == 0) 415 return; 416 417 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 418 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 419 return; 420 421 /* todo */ 422 } 423 424 static void nv_program_aspm(struct amdgpu_device *adev) 425 { 426 427 if (amdgpu_aspm == 0) 428 return; 429 430 /* todo */ 431 } 432 433 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 434 bool enable) 435 { 436 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 437 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 438 } 439 440 static const struct amdgpu_ip_block_version nv_common_ip_block = 441 { 442 .type = AMD_IP_BLOCK_TYPE_COMMON, 443 .major = 1, 444 .minor = 0, 445 .rev = 0, 446 .funcs = &nv_common_ip_funcs, 447 }; 448 449 static int nv_reg_base_init(struct amdgpu_device *adev) 450 { 451 int r; 452 453 if (amdgpu_discovery) { 454 r = amdgpu_discovery_reg_base_init(adev); 455 if (r) { 456 DRM_WARN("failed to init reg base from ip discovery table, " 457 "fallback to legacy init method\n"); 458 goto legacy_init; 459 } 460 461 return 0; 462 } 463 464 legacy_init: 465 switch (adev->asic_type) { 466 case CHIP_NAVI10: 467 navi10_reg_base_init(adev); 468 break; 469 case CHIP_NAVI14: 470 navi14_reg_base_init(adev); 471 break; 472 case CHIP_NAVI12: 473 navi12_reg_base_init(adev); 474 break; 475 case CHIP_SIENNA_CICHLID: 476 case CHIP_NAVY_FLOUNDER: 477 sienna_cichlid_reg_base_init(adev); 478 break; 479 case CHIP_VANGOGH: 480 vangogh_reg_base_init(adev); 481 break; 482 case CHIP_DIMGREY_CAVEFISH: 483 dimgrey_cavefish_reg_base_init(adev); 484 break; 485 default: 486 return -EINVAL; 487 } 488 489 return 0; 490 } 491 492 void nv_set_virt_ops(struct amdgpu_device *adev) 493 { 494 adev->virt.ops = &xgpu_nv_virt_ops; 495 } 496 497 static bool nv_is_headless_sku(struct pci_dev *pdev) 498 { 499 if ((pdev->device == 0x731E && 500 (pdev->revision == 0xC6 || pdev->revision == 0xC7)) || 501 (pdev->device == 0x7340 && pdev->revision == 0xC9)) 502 return true; 503 return false; 504 } 505 506 int nv_set_ip_blocks(struct amdgpu_device *adev) 507 { 508 int r; 509 510 if (adev->flags & AMD_IS_APU) { 511 adev->nbio.funcs = &nbio_v7_2_funcs; 512 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 513 } else { 514 adev->nbio.funcs = &nbio_v2_3_funcs; 515 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 516 } 517 518 if (adev->asic_type == CHIP_SIENNA_CICHLID) 519 adev->gmc.xgmi.supported = true; 520 521 /* Set IP register base before any HW register access */ 522 r = nv_reg_base_init(adev); 523 if (r) 524 return r; 525 526 switch (adev->asic_type) { 527 case CHIP_NAVI10: 528 case CHIP_NAVI14: 529 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 530 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 531 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 532 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 533 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 534 !amdgpu_sriov_vf(adev)) 535 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 536 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 537 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 538 #if defined(CONFIG_DRM_AMD_DC) 539 else if (amdgpu_device_has_dc_support(adev)) 540 amdgpu_device_ip_block_add(adev, &dm_ip_block); 541 #endif 542 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 543 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 544 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 545 !amdgpu_sriov_vf(adev)) 546 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 547 if (!nv_is_headless_sku(adev->pdev)) 548 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 549 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 550 if (adev->enable_mes) 551 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 552 break; 553 case CHIP_NAVI12: 554 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 555 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 556 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 557 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 558 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 559 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 560 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 561 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 562 #if defined(CONFIG_DRM_AMD_DC) 563 else if (amdgpu_device_has_dc_support(adev)) 564 amdgpu_device_ip_block_add(adev, &dm_ip_block); 565 #endif 566 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 567 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 568 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 569 !amdgpu_sriov_vf(adev)) 570 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 571 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 572 if (!amdgpu_sriov_vf(adev)) 573 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 574 break; 575 case CHIP_SIENNA_CICHLID: 576 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 577 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 578 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 579 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 580 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 581 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 582 is_support_sw_smu(adev)) 583 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 584 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 585 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 586 #if defined(CONFIG_DRM_AMD_DC) 587 else if (amdgpu_device_has_dc_support(adev)) 588 amdgpu_device_ip_block_add(adev, &dm_ip_block); 589 #endif 590 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 591 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 592 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 593 if (!amdgpu_sriov_vf(adev)) 594 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 595 596 if (adev->enable_mes) 597 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 598 break; 599 case CHIP_NAVY_FLOUNDER: 600 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 601 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 602 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 603 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 604 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 605 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 606 is_support_sw_smu(adev)) 607 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 608 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 609 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 610 #if defined(CONFIG_DRM_AMD_DC) 611 else if (amdgpu_device_has_dc_support(adev)) 612 amdgpu_device_ip_block_add(adev, &dm_ip_block); 613 #endif 614 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 615 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 616 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 617 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 618 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 619 is_support_sw_smu(adev)) 620 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 621 break; 622 case CHIP_VANGOGH: 623 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 624 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 625 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 626 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 627 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 628 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 629 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 630 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 631 #if defined(CONFIG_DRM_AMD_DC) 632 else if (amdgpu_device_has_dc_support(adev)) 633 amdgpu_device_ip_block_add(adev, &dm_ip_block); 634 #endif 635 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 636 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 637 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 638 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 639 break; 640 case CHIP_DIMGREY_CAVEFISH: 641 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 642 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 643 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 644 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 645 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 646 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 647 is_support_sw_smu(adev)) 648 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 649 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 650 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 651 #if defined(CONFIG_DRM_AMD_DC) 652 else if (amdgpu_device_has_dc_support(adev)) 653 amdgpu_device_ip_block_add(adev, &dm_ip_block); 654 #endif 655 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 656 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 657 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 658 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 659 break; 660 default: 661 return -EINVAL; 662 } 663 664 return 0; 665 } 666 667 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 668 { 669 return adev->nbio.funcs->get_rev_id(adev); 670 } 671 672 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 673 { 674 adev->nbio.funcs->hdp_flush(adev, ring); 675 } 676 677 static void nv_invalidate_hdp(struct amdgpu_device *adev, 678 struct amdgpu_ring *ring) 679 { 680 if (!ring || !ring->funcs->emit_wreg) { 681 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 682 } else { 683 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 684 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 685 } 686 } 687 688 static bool nv_need_full_reset(struct amdgpu_device *adev) 689 { 690 return true; 691 } 692 693 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 694 { 695 u32 sol_reg; 696 697 if (adev->flags & AMD_IS_APU) 698 return false; 699 700 /* Check sOS sign of life register to confirm sys driver and sOS 701 * are already been loaded. 702 */ 703 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 704 if (sol_reg) 705 return true; 706 707 return false; 708 } 709 710 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 711 { 712 713 /* TODO 714 * dummy implement for pcie_replay_count sysfs interface 715 * */ 716 717 return 0; 718 } 719 720 static void nv_init_doorbell_index(struct amdgpu_device *adev) 721 { 722 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 723 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 724 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 725 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 726 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 727 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 728 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 729 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 730 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 731 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 732 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 733 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 734 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 735 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 736 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 737 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 738 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 739 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 740 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 741 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 742 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 743 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 744 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 745 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 746 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 747 748 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 749 adev->doorbell_index.sdma_doorbell_range = 20; 750 } 751 752 static void nv_pre_asic_init(struct amdgpu_device *adev) 753 { 754 } 755 756 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 757 bool enter) 758 { 759 if (enter) 760 amdgpu_gfx_rlc_enter_safe_mode(adev); 761 else 762 amdgpu_gfx_rlc_exit_safe_mode(adev); 763 764 if (adev->gfx.funcs->update_perfmon_mgcg) 765 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 766 767 /* 768 * The ASPM function is not fully enabled and verified on 769 * Navi yet. Temporarily skip this until ASPM enabled. 770 */ 771 #if 0 772 if (adev->nbio.funcs->enable_aspm) 773 adev->nbio.funcs->enable_aspm(adev, !enter); 774 #endif 775 776 return 0; 777 } 778 779 static const struct amdgpu_asic_funcs nv_asic_funcs = 780 { 781 .read_disabled_bios = &nv_read_disabled_bios, 782 .read_bios_from_rom = &nv_read_bios_from_rom, 783 .read_register = &nv_read_register, 784 .reset = &nv_asic_reset, 785 .reset_method = &nv_asic_reset_method, 786 .set_vga_state = &nv_vga_set_state, 787 .get_xclk = &nv_get_xclk, 788 .set_uvd_clocks = &nv_set_uvd_clocks, 789 .set_vce_clocks = &nv_set_vce_clocks, 790 .get_config_memsize = &nv_get_config_memsize, 791 .flush_hdp = &nv_flush_hdp, 792 .invalidate_hdp = &nv_invalidate_hdp, 793 .init_doorbell_index = &nv_init_doorbell_index, 794 .need_full_reset = &nv_need_full_reset, 795 .need_reset_on_init = &nv_need_reset_on_init, 796 .get_pcie_replay_count = &nv_get_pcie_replay_count, 797 .supports_baco = &nv_asic_supports_baco, 798 .pre_asic_init = &nv_pre_asic_init, 799 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 800 }; 801 802 static int nv_common_early_init(void *handle) 803 { 804 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 805 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 806 807 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 808 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 809 adev->smc_rreg = NULL; 810 adev->smc_wreg = NULL; 811 adev->pcie_rreg = &nv_pcie_rreg; 812 adev->pcie_wreg = &nv_pcie_wreg; 813 adev->pcie_rreg64 = &nv_pcie_rreg64; 814 adev->pcie_wreg64 = &nv_pcie_wreg64; 815 adev->pciep_rreg = &nv_pcie_port_rreg; 816 adev->pciep_wreg = &nv_pcie_port_wreg; 817 818 /* TODO: will add them during VCN v2 implementation */ 819 adev->uvd_ctx_rreg = NULL; 820 adev->uvd_ctx_wreg = NULL; 821 822 adev->didt_rreg = &nv_didt_rreg; 823 adev->didt_wreg = &nv_didt_wreg; 824 825 adev->asic_funcs = &nv_asic_funcs; 826 827 adev->rev_id = nv_get_rev_id(adev); 828 adev->external_rev_id = 0xff; 829 switch (adev->asic_type) { 830 case CHIP_NAVI10: 831 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 832 AMD_CG_SUPPORT_GFX_CGCG | 833 AMD_CG_SUPPORT_IH_CG | 834 AMD_CG_SUPPORT_HDP_MGCG | 835 AMD_CG_SUPPORT_HDP_LS | 836 AMD_CG_SUPPORT_SDMA_MGCG | 837 AMD_CG_SUPPORT_SDMA_LS | 838 AMD_CG_SUPPORT_MC_MGCG | 839 AMD_CG_SUPPORT_MC_LS | 840 AMD_CG_SUPPORT_ATHUB_MGCG | 841 AMD_CG_SUPPORT_ATHUB_LS | 842 AMD_CG_SUPPORT_VCN_MGCG | 843 AMD_CG_SUPPORT_JPEG_MGCG | 844 AMD_CG_SUPPORT_BIF_MGCG | 845 AMD_CG_SUPPORT_BIF_LS; 846 adev->pg_flags = AMD_PG_SUPPORT_VCN | 847 AMD_PG_SUPPORT_VCN_DPG | 848 AMD_PG_SUPPORT_JPEG | 849 AMD_PG_SUPPORT_ATHUB; 850 adev->external_rev_id = adev->rev_id + 0x1; 851 break; 852 case CHIP_NAVI14: 853 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 854 AMD_CG_SUPPORT_GFX_CGCG | 855 AMD_CG_SUPPORT_IH_CG | 856 AMD_CG_SUPPORT_HDP_MGCG | 857 AMD_CG_SUPPORT_HDP_LS | 858 AMD_CG_SUPPORT_SDMA_MGCG | 859 AMD_CG_SUPPORT_SDMA_LS | 860 AMD_CG_SUPPORT_MC_MGCG | 861 AMD_CG_SUPPORT_MC_LS | 862 AMD_CG_SUPPORT_ATHUB_MGCG | 863 AMD_CG_SUPPORT_ATHUB_LS | 864 AMD_CG_SUPPORT_VCN_MGCG | 865 AMD_CG_SUPPORT_JPEG_MGCG | 866 AMD_CG_SUPPORT_BIF_MGCG | 867 AMD_CG_SUPPORT_BIF_LS; 868 adev->pg_flags = AMD_PG_SUPPORT_VCN | 869 AMD_PG_SUPPORT_JPEG | 870 AMD_PG_SUPPORT_VCN_DPG; 871 adev->external_rev_id = adev->rev_id + 20; 872 break; 873 case CHIP_NAVI12: 874 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 875 AMD_CG_SUPPORT_GFX_MGLS | 876 AMD_CG_SUPPORT_GFX_CGCG | 877 AMD_CG_SUPPORT_GFX_CP_LS | 878 AMD_CG_SUPPORT_GFX_RLC_LS | 879 AMD_CG_SUPPORT_IH_CG | 880 AMD_CG_SUPPORT_HDP_MGCG | 881 AMD_CG_SUPPORT_HDP_LS | 882 AMD_CG_SUPPORT_SDMA_MGCG | 883 AMD_CG_SUPPORT_SDMA_LS | 884 AMD_CG_SUPPORT_MC_MGCG | 885 AMD_CG_SUPPORT_MC_LS | 886 AMD_CG_SUPPORT_ATHUB_MGCG | 887 AMD_CG_SUPPORT_ATHUB_LS | 888 AMD_CG_SUPPORT_VCN_MGCG | 889 AMD_CG_SUPPORT_JPEG_MGCG; 890 adev->pg_flags = AMD_PG_SUPPORT_VCN | 891 AMD_PG_SUPPORT_VCN_DPG | 892 AMD_PG_SUPPORT_JPEG | 893 AMD_PG_SUPPORT_ATHUB; 894 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 895 * as a consequence, the rev_id and external_rev_id are wrong. 896 * workaround it by hardcoding rev_id to 0 (default value). 897 */ 898 if (amdgpu_sriov_vf(adev)) 899 adev->rev_id = 0; 900 adev->external_rev_id = adev->rev_id + 0xa; 901 break; 902 case CHIP_SIENNA_CICHLID: 903 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 904 AMD_CG_SUPPORT_GFX_CGCG | 905 AMD_CG_SUPPORT_GFX_3D_CGCG | 906 AMD_CG_SUPPORT_MC_MGCG | 907 AMD_CG_SUPPORT_VCN_MGCG | 908 AMD_CG_SUPPORT_JPEG_MGCG | 909 AMD_CG_SUPPORT_HDP_MGCG | 910 AMD_CG_SUPPORT_HDP_LS | 911 AMD_CG_SUPPORT_IH_CG | 912 AMD_CG_SUPPORT_MC_LS; 913 adev->pg_flags = AMD_PG_SUPPORT_VCN | 914 AMD_PG_SUPPORT_VCN_DPG | 915 AMD_PG_SUPPORT_JPEG | 916 AMD_PG_SUPPORT_ATHUB | 917 AMD_PG_SUPPORT_MMHUB; 918 if (amdgpu_sriov_vf(adev)) { 919 /* hypervisor control CG and PG enablement */ 920 adev->cg_flags = 0; 921 adev->pg_flags = 0; 922 } 923 adev->external_rev_id = adev->rev_id + 0x28; 924 break; 925 case CHIP_NAVY_FLOUNDER: 926 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 927 AMD_CG_SUPPORT_GFX_CGCG | 928 AMD_CG_SUPPORT_GFX_3D_CGCG | 929 AMD_CG_SUPPORT_VCN_MGCG | 930 AMD_CG_SUPPORT_JPEG_MGCG | 931 AMD_CG_SUPPORT_MC_MGCG | 932 AMD_CG_SUPPORT_MC_LS | 933 AMD_CG_SUPPORT_HDP_MGCG | 934 AMD_CG_SUPPORT_HDP_LS | 935 AMD_CG_SUPPORT_IH_CG; 936 adev->pg_flags = AMD_PG_SUPPORT_VCN | 937 AMD_PG_SUPPORT_VCN_DPG | 938 AMD_PG_SUPPORT_JPEG | 939 AMD_PG_SUPPORT_ATHUB | 940 AMD_PG_SUPPORT_MMHUB; 941 adev->external_rev_id = adev->rev_id + 0x32; 942 break; 943 944 case CHIP_VANGOGH: 945 adev->apu_flags |= AMD_APU_IS_VANGOGH; 946 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 947 AMD_CG_SUPPORT_GFX_MGLS | 948 AMD_CG_SUPPORT_GFX_CP_LS | 949 AMD_CG_SUPPORT_GFX_RLC_LS | 950 AMD_CG_SUPPORT_GFX_CGCG | 951 AMD_CG_SUPPORT_GFX_CGLS | 952 AMD_CG_SUPPORT_GFX_3D_CGCG | 953 AMD_CG_SUPPORT_GFX_3D_CGLS | 954 AMD_CG_SUPPORT_MC_MGCG | 955 AMD_CG_SUPPORT_MC_LS | 956 AMD_CG_SUPPORT_GFX_FGCG | 957 AMD_CG_SUPPORT_VCN_MGCG | 958 AMD_CG_SUPPORT_JPEG_MGCG; 959 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 960 AMD_PG_SUPPORT_VCN | 961 AMD_PG_SUPPORT_VCN_DPG | 962 AMD_PG_SUPPORT_JPEG; 963 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 964 adev->external_rev_id = adev->rev_id + 0x01; 965 break; 966 case CHIP_DIMGREY_CAVEFISH: 967 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 968 AMD_CG_SUPPORT_GFX_CGCG | 969 AMD_CG_SUPPORT_GFX_3D_CGCG | 970 AMD_CG_SUPPORT_VCN_MGCG | 971 AMD_CG_SUPPORT_JPEG_MGCG | 972 AMD_CG_SUPPORT_MC_MGCG | 973 AMD_CG_SUPPORT_MC_LS | 974 AMD_CG_SUPPORT_HDP_MGCG | 975 AMD_CG_SUPPORT_HDP_LS | 976 AMD_CG_SUPPORT_IH_CG; 977 adev->pg_flags = AMD_PG_SUPPORT_VCN | 978 AMD_PG_SUPPORT_VCN_DPG | 979 AMD_PG_SUPPORT_JPEG | 980 AMD_PG_SUPPORT_ATHUB | 981 AMD_PG_SUPPORT_MMHUB; 982 adev->external_rev_id = adev->rev_id + 0x3c; 983 break; 984 default: 985 /* FIXME: not supported yet */ 986 return -EINVAL; 987 } 988 989 if (amdgpu_sriov_vf(adev)) { 990 amdgpu_virt_init_setting(adev); 991 xgpu_nv_mailbox_set_irq_funcs(adev); 992 } 993 994 return 0; 995 } 996 997 static int nv_common_late_init(void *handle) 998 { 999 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1000 1001 if (amdgpu_sriov_vf(adev)) 1002 xgpu_nv_mailbox_get_irq(adev); 1003 1004 return 0; 1005 } 1006 1007 static int nv_common_sw_init(void *handle) 1008 { 1009 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1010 1011 if (amdgpu_sriov_vf(adev)) 1012 xgpu_nv_mailbox_add_irq_id(adev); 1013 1014 return 0; 1015 } 1016 1017 static int nv_common_sw_fini(void *handle) 1018 { 1019 return 0; 1020 } 1021 1022 static int nv_common_hw_init(void *handle) 1023 { 1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1025 1026 /* enable pcie gen2/3 link */ 1027 nv_pcie_gen3_enable(adev); 1028 /* enable aspm */ 1029 nv_program_aspm(adev); 1030 /* setup nbio registers */ 1031 adev->nbio.funcs->init_registers(adev); 1032 /* remap HDP registers to a hole in mmio space, 1033 * for the purpose of expose those registers 1034 * to process space 1035 */ 1036 if (adev->nbio.funcs->remap_hdp_registers) 1037 adev->nbio.funcs->remap_hdp_registers(adev); 1038 /* enable the doorbell aperture */ 1039 nv_enable_doorbell_aperture(adev, true); 1040 1041 return 0; 1042 } 1043 1044 static int nv_common_hw_fini(void *handle) 1045 { 1046 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1047 1048 /* disable the doorbell aperture */ 1049 nv_enable_doorbell_aperture(adev, false); 1050 1051 return 0; 1052 } 1053 1054 static int nv_common_suspend(void *handle) 1055 { 1056 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1057 1058 return nv_common_hw_fini(adev); 1059 } 1060 1061 static int nv_common_resume(void *handle) 1062 { 1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1064 1065 return nv_common_hw_init(adev); 1066 } 1067 1068 static bool nv_common_is_idle(void *handle) 1069 { 1070 return true; 1071 } 1072 1073 static int nv_common_wait_for_idle(void *handle) 1074 { 1075 return 0; 1076 } 1077 1078 static int nv_common_soft_reset(void *handle) 1079 { 1080 return 0; 1081 } 1082 1083 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 1084 bool enable) 1085 { 1086 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 1087 uint32_t hdp_mem_pwr_cntl; 1088 1089 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 1090 AMD_CG_SUPPORT_HDP_DS | 1091 AMD_CG_SUPPORT_HDP_SD))) 1092 return; 1093 1094 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1095 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1096 1097 /* Before doing clock/power mode switch, 1098 * forced on IPH & RC clock */ 1099 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 1100 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 1101 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 1102 RC_MEM_CLK_SOFT_OVERRIDE, 1); 1103 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1104 1105 /* HDP 5.0 doesn't support dynamic power mode switch, 1106 * disable clock and power gating before any changing */ 1107 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1108 IPH_MEM_POWER_CTRL_EN, 0); 1109 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1110 IPH_MEM_POWER_LS_EN, 0); 1111 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1112 IPH_MEM_POWER_DS_EN, 0); 1113 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1114 IPH_MEM_POWER_SD_EN, 0); 1115 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1116 RC_MEM_POWER_CTRL_EN, 0); 1117 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1118 RC_MEM_POWER_LS_EN, 0); 1119 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1120 RC_MEM_POWER_DS_EN, 0); 1121 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1122 RC_MEM_POWER_SD_EN, 0); 1123 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1124 1125 /* only one clock gating mode (LS/DS/SD) can be enabled */ 1126 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1127 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1128 HDP_MEM_POWER_CTRL, 1129 IPH_MEM_POWER_LS_EN, enable); 1130 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1131 HDP_MEM_POWER_CTRL, 1132 RC_MEM_POWER_LS_EN, enable); 1133 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 1134 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1135 HDP_MEM_POWER_CTRL, 1136 IPH_MEM_POWER_DS_EN, enable); 1137 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1138 HDP_MEM_POWER_CTRL, 1139 RC_MEM_POWER_DS_EN, enable); 1140 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 1141 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1142 HDP_MEM_POWER_CTRL, 1143 IPH_MEM_POWER_SD_EN, enable); 1144 /* RC should not use shut down mode, fallback to ds */ 1145 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1146 HDP_MEM_POWER_CTRL, 1147 RC_MEM_POWER_DS_EN, enable); 1148 } 1149 1150 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 1151 * be set for SRAM LS/DS/SD */ 1152 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 1153 AMD_CG_SUPPORT_HDP_SD)) { 1154 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1155 IPH_MEM_POWER_CTRL_EN, 1); 1156 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1157 RC_MEM_POWER_CTRL_EN, 1); 1158 } 1159 1160 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1161 1162 /* restore IPH & RC clock override after clock/power mode changing */ 1163 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 1164 } 1165 1166 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 1167 bool enable) 1168 { 1169 uint32_t hdp_clk_cntl; 1170 1171 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1172 return; 1173 1174 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1175 1176 if (enable) { 1177 hdp_clk_cntl &= 1178 ~(uint32_t) 1179 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1180 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1181 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1182 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1183 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1184 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 1185 } else { 1186 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1187 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1188 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1189 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1190 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1191 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 1192 } 1193 1194 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1195 } 1196 1197 static int nv_common_set_clockgating_state(void *handle, 1198 enum amd_clockgating_state state) 1199 { 1200 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1201 1202 if (amdgpu_sriov_vf(adev)) 1203 return 0; 1204 1205 switch (adev->asic_type) { 1206 case CHIP_NAVI10: 1207 case CHIP_NAVI14: 1208 case CHIP_NAVI12: 1209 case CHIP_SIENNA_CICHLID: 1210 case CHIP_NAVY_FLOUNDER: 1211 case CHIP_DIMGREY_CAVEFISH: 1212 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1213 state == AMD_CG_STATE_GATE); 1214 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1215 state == AMD_CG_STATE_GATE); 1216 nv_update_hdp_mem_power_gating(adev, 1217 state == AMD_CG_STATE_GATE); 1218 nv_update_hdp_clock_gating(adev, 1219 state == AMD_CG_STATE_GATE); 1220 break; 1221 default: 1222 break; 1223 } 1224 return 0; 1225 } 1226 1227 static int nv_common_set_powergating_state(void *handle, 1228 enum amd_powergating_state state) 1229 { 1230 /* TODO */ 1231 return 0; 1232 } 1233 1234 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1235 { 1236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1237 uint32_t tmp; 1238 1239 if (amdgpu_sriov_vf(adev)) 1240 *flags = 0; 1241 1242 adev->nbio.funcs->get_clockgating_state(adev, flags); 1243 1244 /* AMD_CG_SUPPORT_HDP_MGCG */ 1245 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1246 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1247 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1248 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1249 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1250 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1251 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 1252 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1253 1254 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 1255 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1256 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 1257 *flags |= AMD_CG_SUPPORT_HDP_LS; 1258 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1259 *flags |= AMD_CG_SUPPORT_HDP_DS; 1260 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1261 *flags |= AMD_CG_SUPPORT_HDP_SD; 1262 1263 return; 1264 } 1265 1266 static const struct amd_ip_funcs nv_common_ip_funcs = { 1267 .name = "nv_common", 1268 .early_init = nv_common_early_init, 1269 .late_init = nv_common_late_init, 1270 .sw_init = nv_common_sw_init, 1271 .sw_fini = nv_common_sw_fini, 1272 .hw_init = nv_common_hw_init, 1273 .hw_fini = nv_common_hw_fini, 1274 .suspend = nv_common_suspend, 1275 .resume = nv_common_resume, 1276 .is_idle = nv_common_is_idle, 1277 .wait_for_idle = nv_common_wait_for_idle, 1278 .soft_reset = nv_common_soft_reset, 1279 .set_clockgating_state = nv_common_set_clockgating_state, 1280 .set_powergating_state = nv_common_set_powergating_state, 1281 .get_clockgating_state = nv_common_get_clockgating_state, 1282 }; 1283