1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 74 }; 75 76 static const struct amdgpu_video_codecs nv_video_codecs_encode = 77 { 78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 79 .codec_array = nv_video_codecs_encode_array, 80 }; 81 82 /* Navi1x */ 83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 92 }; 93 94 static const struct amdgpu_video_codecs nv_video_codecs_decode = 95 { 96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 97 .codec_array = nv_video_codecs_decode_array, 98 }; 99 100 /* Sienna Cichlid */ 101 static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = { 102 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)}, 103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)}, 104 }; 105 106 static const struct amdgpu_video_codecs sc_video_codecs_encode = { 107 .codec_count = ARRAY_SIZE(sc_video_codecs_encode_array), 108 .codec_array = sc_video_codecs_encode_array, 109 }; 110 111 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = 112 { 113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 114 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 115 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 116 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 117 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 118 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 119 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 121 }; 122 123 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = 124 { 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 132 }; 133 134 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = 135 { 136 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0), 137 .codec_array = sc_video_codecs_decode_array_vcn0, 138 }; 139 140 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = 141 { 142 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1), 143 .codec_array = sc_video_codecs_decode_array_vcn1, 144 }; 145 146 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 147 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 148 { 149 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)}, 150 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)}, 151 }; 152 153 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = 154 { 155 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 162 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 163 }; 164 165 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = 166 { 167 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 168 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 169 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 170 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 171 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 172 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 173 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 174 }; 175 176 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 177 { 178 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 179 .codec_array = sriov_sc_video_codecs_encode_array, 180 }; 181 182 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = 183 { 184 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0), 185 .codec_array = sriov_sc_video_codecs_decode_array_vcn0, 186 }; 187 188 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = 189 { 190 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1), 191 .codec_array = sriov_sc_video_codecs_decode_array_vcn1, 192 }; 193 194 /* Beige Goby*/ 195 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 196 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 197 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 198 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 199 }; 200 201 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 202 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 203 .codec_array = bg_video_codecs_decode_array, 204 }; 205 206 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 207 .codec_count = 0, 208 .codec_array = NULL, 209 }; 210 211 /* Yellow Carp*/ 212 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 213 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 214 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 215 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 216 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 217 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 218 }; 219 220 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 221 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 222 .codec_array = yc_video_codecs_decode_array, 223 }; 224 225 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 226 const struct amdgpu_video_codecs **codecs) 227 { 228 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 229 return -EINVAL; 230 231 switch (adev->ip_versions[UVD_HWIP][0]) { 232 case IP_VERSION(3, 0, 0): 233 case IP_VERSION(3, 0, 64): 234 case IP_VERSION(3, 0, 192): 235 if (amdgpu_sriov_vf(adev)) { 236 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 237 if (encode) 238 *codecs = &sriov_sc_video_codecs_encode; 239 else 240 *codecs = &sriov_sc_video_codecs_decode_vcn1; 241 } else { 242 if (encode) 243 *codecs = &sriov_sc_video_codecs_encode; 244 else 245 *codecs = &sriov_sc_video_codecs_decode_vcn0; 246 } 247 } else { 248 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 249 if (encode) 250 *codecs = &sc_video_codecs_encode; 251 else 252 *codecs = &sc_video_codecs_decode_vcn1; 253 } else { 254 if (encode) 255 *codecs = &sc_video_codecs_encode; 256 else 257 *codecs = &sc_video_codecs_decode_vcn0; 258 } 259 } 260 return 0; 261 case IP_VERSION(3, 0, 16): 262 case IP_VERSION(3, 0, 2): 263 if (encode) 264 *codecs = &sc_video_codecs_encode; 265 else 266 *codecs = &sc_video_codecs_decode_vcn0; 267 return 0; 268 case IP_VERSION(3, 1, 1): 269 case IP_VERSION(3, 1, 2): 270 if (encode) 271 *codecs = &sc_video_codecs_encode; 272 else 273 *codecs = &yc_video_codecs_decode; 274 return 0; 275 case IP_VERSION(3, 0, 33): 276 if (encode) 277 *codecs = &bg_video_codecs_encode; 278 else 279 *codecs = &bg_video_codecs_decode; 280 return 0; 281 case IP_VERSION(2, 0, 0): 282 case IP_VERSION(2, 0, 2): 283 if (encode) 284 *codecs = &nv_video_codecs_encode; 285 else 286 *codecs = &nv_video_codecs_decode; 287 return 0; 288 default: 289 return -EINVAL; 290 } 291 } 292 293 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 294 { 295 unsigned long flags, address, data; 296 u32 r; 297 298 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 299 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 300 301 spin_lock_irqsave(&adev->didt_idx_lock, flags); 302 WREG32(address, (reg)); 303 r = RREG32(data); 304 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 305 return r; 306 } 307 308 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 309 { 310 unsigned long flags, address, data; 311 312 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 313 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 314 315 spin_lock_irqsave(&adev->didt_idx_lock, flags); 316 WREG32(address, (reg)); 317 WREG32(data, (v)); 318 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 319 } 320 321 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 322 { 323 return adev->nbio.funcs->get_memsize(adev); 324 } 325 326 static u32 nv_get_xclk(struct amdgpu_device *adev) 327 { 328 return adev->clock.spll.reference_freq; 329 } 330 331 332 void nv_grbm_select(struct amdgpu_device *adev, 333 u32 me, u32 pipe, u32 queue, u32 vmid) 334 { 335 u32 grbm_gfx_cntl = 0; 336 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 337 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 338 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 339 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 340 341 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 342 } 343 344 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 345 { 346 /* todo */ 347 return false; 348 } 349 350 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 351 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 352 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 353 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 354 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 355 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 356 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 357 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 358 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 359 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 360 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 361 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 362 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 363 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 364 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 365 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 366 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 367 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 368 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 369 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 370 }; 371 372 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 373 u32 sh_num, u32 reg_offset) 374 { 375 uint32_t val; 376 377 mutex_lock(&adev->grbm_idx_mutex); 378 if (se_num != 0xffffffff || sh_num != 0xffffffff) 379 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 380 381 val = RREG32(reg_offset); 382 383 if (se_num != 0xffffffff || sh_num != 0xffffffff) 384 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 385 mutex_unlock(&adev->grbm_idx_mutex); 386 return val; 387 } 388 389 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 390 bool indexed, u32 se_num, 391 u32 sh_num, u32 reg_offset) 392 { 393 if (indexed) { 394 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 395 } else { 396 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 397 return adev->gfx.config.gb_addr_config; 398 return RREG32(reg_offset); 399 } 400 } 401 402 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 403 u32 sh_num, u32 reg_offset, u32 *value) 404 { 405 uint32_t i; 406 struct soc15_allowed_register_entry *en; 407 408 *value = 0; 409 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 410 en = &nv_allowed_read_registers[i]; 411 if (!adev->reg_offset[en->hwip][en->inst]) 412 continue; 413 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 414 + en->reg_offset)) 415 continue; 416 417 *value = nv_get_register_value(adev, 418 nv_allowed_read_registers[i].grbm_indexed, 419 se_num, sh_num, reg_offset); 420 return 0; 421 } 422 return -EINVAL; 423 } 424 425 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 426 { 427 u32 i; 428 int ret = 0; 429 430 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 431 432 /* disable BM */ 433 pci_clear_master(adev->pdev); 434 435 amdgpu_device_cache_pci_state(adev->pdev); 436 437 ret = amdgpu_dpm_mode2_reset(adev); 438 if (ret) 439 dev_err(adev->dev, "GPU mode2 reset failed\n"); 440 441 amdgpu_device_load_pci_state(adev->pdev); 442 443 /* wait for asic to come out of reset */ 444 for (i = 0; i < adev->usec_timeout; i++) { 445 u32 memsize = adev->nbio.funcs->get_memsize(adev); 446 447 if (memsize != 0xffffffff) 448 break; 449 udelay(1); 450 } 451 452 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 453 454 return ret; 455 } 456 457 static enum amd_reset_method 458 nv_asic_reset_method(struct amdgpu_device *adev) 459 { 460 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 461 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 462 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 463 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 464 return amdgpu_reset_method; 465 466 if (amdgpu_reset_method != -1) 467 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 468 amdgpu_reset_method); 469 470 switch (adev->ip_versions[MP1_HWIP][0]) { 471 case IP_VERSION(11, 5, 0): 472 case IP_VERSION(13, 0, 1): 473 case IP_VERSION(13, 0, 3): 474 case IP_VERSION(13, 0, 5): 475 case IP_VERSION(13, 0, 8): 476 return AMD_RESET_METHOD_MODE2; 477 case IP_VERSION(11, 0, 7): 478 case IP_VERSION(11, 0, 11): 479 case IP_VERSION(11, 0, 12): 480 case IP_VERSION(11, 0, 13): 481 return AMD_RESET_METHOD_MODE1; 482 default: 483 if (amdgpu_dpm_is_baco_supported(adev)) 484 return AMD_RESET_METHOD_BACO; 485 else 486 return AMD_RESET_METHOD_MODE1; 487 } 488 } 489 490 static int nv_asic_reset(struct amdgpu_device *adev) 491 { 492 int ret = 0; 493 494 switch (nv_asic_reset_method(adev)) { 495 case AMD_RESET_METHOD_PCI: 496 dev_info(adev->dev, "PCI reset\n"); 497 ret = amdgpu_device_pci_reset(adev); 498 break; 499 case AMD_RESET_METHOD_BACO: 500 dev_info(adev->dev, "BACO reset\n"); 501 ret = amdgpu_dpm_baco_reset(adev); 502 break; 503 case AMD_RESET_METHOD_MODE2: 504 dev_info(adev->dev, "MODE2 reset\n"); 505 ret = nv_asic_mode2_reset(adev); 506 break; 507 default: 508 dev_info(adev->dev, "MODE1 reset\n"); 509 ret = amdgpu_device_mode1_reset(adev); 510 break; 511 } 512 513 return ret; 514 } 515 516 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 517 { 518 /* todo */ 519 return 0; 520 } 521 522 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 523 { 524 /* todo */ 525 return 0; 526 } 527 528 static void nv_program_aspm(struct amdgpu_device *adev) 529 { 530 if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_aspm_support_quirk()) 531 return; 532 533 if (!(adev->flags & AMD_IS_APU) && 534 (adev->nbio.funcs->program_aspm)) 535 adev->nbio.funcs->program_aspm(adev); 536 537 } 538 539 const struct amdgpu_ip_block_version nv_common_ip_block = 540 { 541 .type = AMD_IP_BLOCK_TYPE_COMMON, 542 .major = 1, 543 .minor = 0, 544 .rev = 0, 545 .funcs = &nv_common_ip_funcs, 546 }; 547 548 void nv_set_virt_ops(struct amdgpu_device *adev) 549 { 550 adev->virt.ops = &xgpu_nv_virt_ops; 551 } 552 553 static bool nv_need_full_reset(struct amdgpu_device *adev) 554 { 555 return true; 556 } 557 558 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 559 { 560 u32 sol_reg; 561 562 if (adev->flags & AMD_IS_APU) 563 return false; 564 565 /* Check sOS sign of life register to confirm sys driver and sOS 566 * are already been loaded. 567 */ 568 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 569 if (sol_reg) 570 return true; 571 572 return false; 573 } 574 575 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 576 { 577 578 /* TODO 579 * dummy implement for pcie_replay_count sysfs interface 580 * */ 581 582 return 0; 583 } 584 585 static void nv_init_doorbell_index(struct amdgpu_device *adev) 586 { 587 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 588 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 589 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 590 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 591 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 592 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 593 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 594 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 595 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 596 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 597 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 598 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 599 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 600 adev->doorbell_index.gfx_userqueue_start = 601 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 602 adev->doorbell_index.gfx_userqueue_end = 603 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 604 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 605 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 606 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 607 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 608 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 609 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 610 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 611 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 612 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 613 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 614 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 615 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 616 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 617 618 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 619 adev->doorbell_index.sdma_doorbell_range = 20; 620 } 621 622 static void nv_pre_asic_init(struct amdgpu_device *adev) 623 { 624 } 625 626 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 627 bool enter) 628 { 629 if (enter) 630 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 631 else 632 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 633 634 if (adev->gfx.funcs->update_perfmon_mgcg) 635 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 636 637 if (!(adev->flags & AMD_IS_APU) && 638 (adev->nbio.funcs->enable_aspm) && 639 amdgpu_device_should_use_aspm(adev)) 640 adev->nbio.funcs->enable_aspm(adev, !enter); 641 642 return 0; 643 } 644 645 static const struct amdgpu_asic_funcs nv_asic_funcs = 646 { 647 .read_disabled_bios = &nv_read_disabled_bios, 648 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 649 .read_register = &nv_read_register, 650 .reset = &nv_asic_reset, 651 .reset_method = &nv_asic_reset_method, 652 .get_xclk = &nv_get_xclk, 653 .set_uvd_clocks = &nv_set_uvd_clocks, 654 .set_vce_clocks = &nv_set_vce_clocks, 655 .get_config_memsize = &nv_get_config_memsize, 656 .init_doorbell_index = &nv_init_doorbell_index, 657 .need_full_reset = &nv_need_full_reset, 658 .need_reset_on_init = &nv_need_reset_on_init, 659 .get_pcie_replay_count = &nv_get_pcie_replay_count, 660 .supports_baco = &amdgpu_dpm_is_baco_supported, 661 .pre_asic_init = &nv_pre_asic_init, 662 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 663 .query_video_codecs = &nv_query_video_codecs, 664 }; 665 666 static int nv_common_early_init(void *handle) 667 { 668 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 669 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 670 671 if (!amdgpu_sriov_vf(adev)) { 672 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 673 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 674 } 675 adev->smc_rreg = NULL; 676 adev->smc_wreg = NULL; 677 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 678 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 679 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 680 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 681 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 682 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 683 684 /* TODO: will add them during VCN v2 implementation */ 685 adev->uvd_ctx_rreg = NULL; 686 adev->uvd_ctx_wreg = NULL; 687 688 adev->didt_rreg = &nv_didt_rreg; 689 adev->didt_wreg = &nv_didt_wreg; 690 691 adev->asic_funcs = &nv_asic_funcs; 692 693 adev->rev_id = amdgpu_device_get_rev_id(adev); 694 adev->external_rev_id = 0xff; 695 /* TODO: split the GC and PG flags based on the relevant IP version for which 696 * they are relevant. 697 */ 698 switch (adev->ip_versions[GC_HWIP][0]) { 699 case IP_VERSION(10, 1, 10): 700 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 701 AMD_CG_SUPPORT_GFX_CGCG | 702 AMD_CG_SUPPORT_IH_CG | 703 AMD_CG_SUPPORT_HDP_MGCG | 704 AMD_CG_SUPPORT_HDP_LS | 705 AMD_CG_SUPPORT_SDMA_MGCG | 706 AMD_CG_SUPPORT_SDMA_LS | 707 AMD_CG_SUPPORT_MC_MGCG | 708 AMD_CG_SUPPORT_MC_LS | 709 AMD_CG_SUPPORT_ATHUB_MGCG | 710 AMD_CG_SUPPORT_ATHUB_LS | 711 AMD_CG_SUPPORT_VCN_MGCG | 712 AMD_CG_SUPPORT_JPEG_MGCG | 713 AMD_CG_SUPPORT_BIF_MGCG | 714 AMD_CG_SUPPORT_BIF_LS; 715 adev->pg_flags = AMD_PG_SUPPORT_VCN | 716 AMD_PG_SUPPORT_VCN_DPG | 717 AMD_PG_SUPPORT_JPEG | 718 AMD_PG_SUPPORT_ATHUB; 719 adev->external_rev_id = adev->rev_id + 0x1; 720 break; 721 case IP_VERSION(10, 1, 1): 722 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 723 AMD_CG_SUPPORT_GFX_CGCG | 724 AMD_CG_SUPPORT_IH_CG | 725 AMD_CG_SUPPORT_HDP_MGCG | 726 AMD_CG_SUPPORT_HDP_LS | 727 AMD_CG_SUPPORT_SDMA_MGCG | 728 AMD_CG_SUPPORT_SDMA_LS | 729 AMD_CG_SUPPORT_MC_MGCG | 730 AMD_CG_SUPPORT_MC_LS | 731 AMD_CG_SUPPORT_ATHUB_MGCG | 732 AMD_CG_SUPPORT_ATHUB_LS | 733 AMD_CG_SUPPORT_VCN_MGCG | 734 AMD_CG_SUPPORT_JPEG_MGCG | 735 AMD_CG_SUPPORT_BIF_MGCG | 736 AMD_CG_SUPPORT_BIF_LS; 737 adev->pg_flags = AMD_PG_SUPPORT_VCN | 738 AMD_PG_SUPPORT_JPEG | 739 AMD_PG_SUPPORT_VCN_DPG; 740 adev->external_rev_id = adev->rev_id + 20; 741 break; 742 case IP_VERSION(10, 1, 2): 743 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 744 AMD_CG_SUPPORT_GFX_MGLS | 745 AMD_CG_SUPPORT_GFX_CGCG | 746 AMD_CG_SUPPORT_GFX_CP_LS | 747 AMD_CG_SUPPORT_GFX_RLC_LS | 748 AMD_CG_SUPPORT_IH_CG | 749 AMD_CG_SUPPORT_HDP_MGCG | 750 AMD_CG_SUPPORT_HDP_LS | 751 AMD_CG_SUPPORT_SDMA_MGCG | 752 AMD_CG_SUPPORT_SDMA_LS | 753 AMD_CG_SUPPORT_MC_MGCG | 754 AMD_CG_SUPPORT_MC_LS | 755 AMD_CG_SUPPORT_ATHUB_MGCG | 756 AMD_CG_SUPPORT_ATHUB_LS | 757 AMD_CG_SUPPORT_VCN_MGCG | 758 AMD_CG_SUPPORT_JPEG_MGCG; 759 adev->pg_flags = AMD_PG_SUPPORT_VCN | 760 AMD_PG_SUPPORT_VCN_DPG | 761 AMD_PG_SUPPORT_JPEG | 762 AMD_PG_SUPPORT_ATHUB; 763 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 764 * as a consequence, the rev_id and external_rev_id are wrong. 765 * workaround it by hardcoding rev_id to 0 (default value). 766 */ 767 if (amdgpu_sriov_vf(adev)) 768 adev->rev_id = 0; 769 adev->external_rev_id = adev->rev_id + 0xa; 770 break; 771 case IP_VERSION(10, 3, 0): 772 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 773 AMD_CG_SUPPORT_GFX_CGCG | 774 AMD_CG_SUPPORT_GFX_CGLS | 775 AMD_CG_SUPPORT_GFX_3D_CGCG | 776 AMD_CG_SUPPORT_MC_MGCG | 777 AMD_CG_SUPPORT_VCN_MGCG | 778 AMD_CG_SUPPORT_JPEG_MGCG | 779 AMD_CG_SUPPORT_HDP_MGCG | 780 AMD_CG_SUPPORT_HDP_LS | 781 AMD_CG_SUPPORT_IH_CG | 782 AMD_CG_SUPPORT_MC_LS; 783 adev->pg_flags = AMD_PG_SUPPORT_VCN | 784 AMD_PG_SUPPORT_VCN_DPG | 785 AMD_PG_SUPPORT_JPEG | 786 AMD_PG_SUPPORT_ATHUB | 787 AMD_PG_SUPPORT_MMHUB; 788 if (amdgpu_sriov_vf(adev)) { 789 /* hypervisor control CG and PG enablement */ 790 adev->cg_flags = 0; 791 adev->pg_flags = 0; 792 } 793 adev->external_rev_id = adev->rev_id + 0x28; 794 break; 795 case IP_VERSION(10, 3, 2): 796 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 797 AMD_CG_SUPPORT_GFX_CGCG | 798 AMD_CG_SUPPORT_GFX_CGLS | 799 AMD_CG_SUPPORT_GFX_3D_CGCG | 800 AMD_CG_SUPPORT_VCN_MGCG | 801 AMD_CG_SUPPORT_JPEG_MGCG | 802 AMD_CG_SUPPORT_MC_MGCG | 803 AMD_CG_SUPPORT_MC_LS | 804 AMD_CG_SUPPORT_HDP_MGCG | 805 AMD_CG_SUPPORT_HDP_LS | 806 AMD_CG_SUPPORT_IH_CG; 807 adev->pg_flags = AMD_PG_SUPPORT_VCN | 808 AMD_PG_SUPPORT_VCN_DPG | 809 AMD_PG_SUPPORT_JPEG | 810 AMD_PG_SUPPORT_ATHUB | 811 AMD_PG_SUPPORT_MMHUB; 812 adev->external_rev_id = adev->rev_id + 0x32; 813 break; 814 case IP_VERSION(10, 3, 1): 815 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 816 AMD_CG_SUPPORT_GFX_MGLS | 817 AMD_CG_SUPPORT_GFX_CP_LS | 818 AMD_CG_SUPPORT_GFX_RLC_LS | 819 AMD_CG_SUPPORT_GFX_CGCG | 820 AMD_CG_SUPPORT_GFX_CGLS | 821 AMD_CG_SUPPORT_GFX_3D_CGCG | 822 AMD_CG_SUPPORT_GFX_3D_CGLS | 823 AMD_CG_SUPPORT_MC_MGCG | 824 AMD_CG_SUPPORT_MC_LS | 825 AMD_CG_SUPPORT_GFX_FGCG | 826 AMD_CG_SUPPORT_VCN_MGCG | 827 AMD_CG_SUPPORT_SDMA_MGCG | 828 AMD_CG_SUPPORT_SDMA_LS | 829 AMD_CG_SUPPORT_JPEG_MGCG; 830 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 831 AMD_PG_SUPPORT_VCN | 832 AMD_PG_SUPPORT_VCN_DPG | 833 AMD_PG_SUPPORT_JPEG; 834 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 835 adev->external_rev_id = adev->rev_id + 0x01; 836 break; 837 case IP_VERSION(10, 3, 4): 838 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 839 AMD_CG_SUPPORT_GFX_CGCG | 840 AMD_CG_SUPPORT_GFX_CGLS | 841 AMD_CG_SUPPORT_GFX_3D_CGCG | 842 AMD_CG_SUPPORT_VCN_MGCG | 843 AMD_CG_SUPPORT_JPEG_MGCG | 844 AMD_CG_SUPPORT_MC_MGCG | 845 AMD_CG_SUPPORT_MC_LS | 846 AMD_CG_SUPPORT_HDP_MGCG | 847 AMD_CG_SUPPORT_HDP_LS | 848 AMD_CG_SUPPORT_IH_CG; 849 adev->pg_flags = AMD_PG_SUPPORT_VCN | 850 AMD_PG_SUPPORT_VCN_DPG | 851 AMD_PG_SUPPORT_JPEG | 852 AMD_PG_SUPPORT_ATHUB | 853 AMD_PG_SUPPORT_MMHUB; 854 adev->external_rev_id = adev->rev_id + 0x3c; 855 break; 856 case IP_VERSION(10, 3, 5): 857 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 858 AMD_CG_SUPPORT_GFX_CGCG | 859 AMD_CG_SUPPORT_GFX_CGLS | 860 AMD_CG_SUPPORT_GFX_3D_CGCG | 861 AMD_CG_SUPPORT_MC_MGCG | 862 AMD_CG_SUPPORT_MC_LS | 863 AMD_CG_SUPPORT_HDP_MGCG | 864 AMD_CG_SUPPORT_HDP_LS | 865 AMD_CG_SUPPORT_IH_CG | 866 AMD_CG_SUPPORT_VCN_MGCG; 867 adev->pg_flags = AMD_PG_SUPPORT_VCN | 868 AMD_PG_SUPPORT_VCN_DPG | 869 AMD_PG_SUPPORT_ATHUB | 870 AMD_PG_SUPPORT_MMHUB; 871 adev->external_rev_id = adev->rev_id + 0x46; 872 break; 873 case IP_VERSION(10, 3, 3): 874 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 875 AMD_CG_SUPPORT_GFX_MGLS | 876 AMD_CG_SUPPORT_GFX_CGCG | 877 AMD_CG_SUPPORT_GFX_CGLS | 878 AMD_CG_SUPPORT_GFX_3D_CGCG | 879 AMD_CG_SUPPORT_GFX_3D_CGLS | 880 AMD_CG_SUPPORT_GFX_RLC_LS | 881 AMD_CG_SUPPORT_GFX_CP_LS | 882 AMD_CG_SUPPORT_GFX_FGCG | 883 AMD_CG_SUPPORT_MC_MGCG | 884 AMD_CG_SUPPORT_MC_LS | 885 AMD_CG_SUPPORT_SDMA_LS | 886 AMD_CG_SUPPORT_HDP_MGCG | 887 AMD_CG_SUPPORT_HDP_LS | 888 AMD_CG_SUPPORT_ATHUB_MGCG | 889 AMD_CG_SUPPORT_ATHUB_LS | 890 AMD_CG_SUPPORT_IH_CG | 891 AMD_CG_SUPPORT_VCN_MGCG | 892 AMD_CG_SUPPORT_JPEG_MGCG; 893 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 894 AMD_PG_SUPPORT_VCN | 895 AMD_PG_SUPPORT_VCN_DPG | 896 AMD_PG_SUPPORT_JPEG; 897 if (adev->pdev->device == 0x1681) 898 adev->external_rev_id = 0x20; 899 else 900 adev->external_rev_id = adev->rev_id + 0x01; 901 break; 902 case IP_VERSION(10, 1, 3): 903 case IP_VERSION(10, 1, 4): 904 adev->cg_flags = 0; 905 adev->pg_flags = 0; 906 adev->external_rev_id = adev->rev_id + 0x82; 907 break; 908 case IP_VERSION(10, 3, 6): 909 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 910 AMD_CG_SUPPORT_GFX_MGLS | 911 AMD_CG_SUPPORT_GFX_CGCG | 912 AMD_CG_SUPPORT_GFX_CGLS | 913 AMD_CG_SUPPORT_GFX_3D_CGCG | 914 AMD_CG_SUPPORT_GFX_3D_CGLS | 915 AMD_CG_SUPPORT_GFX_RLC_LS | 916 AMD_CG_SUPPORT_GFX_CP_LS | 917 AMD_CG_SUPPORT_GFX_FGCG | 918 AMD_CG_SUPPORT_MC_MGCG | 919 AMD_CG_SUPPORT_MC_LS | 920 AMD_CG_SUPPORT_SDMA_LS | 921 AMD_CG_SUPPORT_HDP_MGCG | 922 AMD_CG_SUPPORT_HDP_LS | 923 AMD_CG_SUPPORT_ATHUB_MGCG | 924 AMD_CG_SUPPORT_ATHUB_LS | 925 AMD_CG_SUPPORT_IH_CG | 926 AMD_CG_SUPPORT_VCN_MGCG | 927 AMD_CG_SUPPORT_JPEG_MGCG; 928 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 929 AMD_PG_SUPPORT_VCN | 930 AMD_PG_SUPPORT_VCN_DPG | 931 AMD_PG_SUPPORT_JPEG; 932 adev->external_rev_id = adev->rev_id + 0x01; 933 break; 934 case IP_VERSION(10, 3, 7): 935 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 936 AMD_CG_SUPPORT_GFX_MGLS | 937 AMD_CG_SUPPORT_GFX_CGCG | 938 AMD_CG_SUPPORT_GFX_CGLS | 939 AMD_CG_SUPPORT_GFX_3D_CGCG | 940 AMD_CG_SUPPORT_GFX_3D_CGLS | 941 AMD_CG_SUPPORT_GFX_RLC_LS | 942 AMD_CG_SUPPORT_GFX_CP_LS | 943 AMD_CG_SUPPORT_GFX_FGCG | 944 AMD_CG_SUPPORT_MC_MGCG | 945 AMD_CG_SUPPORT_MC_LS | 946 AMD_CG_SUPPORT_SDMA_LS | 947 AMD_CG_SUPPORT_HDP_MGCG | 948 AMD_CG_SUPPORT_HDP_LS | 949 AMD_CG_SUPPORT_ATHUB_MGCG | 950 AMD_CG_SUPPORT_ATHUB_LS | 951 AMD_CG_SUPPORT_IH_CG | 952 AMD_CG_SUPPORT_VCN_MGCG | 953 AMD_CG_SUPPORT_JPEG_MGCG; 954 adev->pg_flags = AMD_PG_SUPPORT_VCN | 955 AMD_PG_SUPPORT_VCN_DPG | 956 AMD_PG_SUPPORT_JPEG | 957 AMD_PG_SUPPORT_GFX_PG; 958 adev->external_rev_id = adev->rev_id + 0x01; 959 break; 960 default: 961 /* FIXME: not supported yet */ 962 return -EINVAL; 963 } 964 965 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 966 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 967 AMD_PG_SUPPORT_VCN_DPG | 968 AMD_PG_SUPPORT_JPEG); 969 970 if (amdgpu_sriov_vf(adev)) { 971 amdgpu_virt_init_setting(adev); 972 xgpu_nv_mailbox_set_irq_funcs(adev); 973 } 974 975 return 0; 976 } 977 978 static int nv_common_late_init(void *handle) 979 { 980 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 981 982 if (amdgpu_sriov_vf(adev)) { 983 xgpu_nv_mailbox_get_irq(adev); 984 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 985 amdgpu_virt_update_sriov_video_codec(adev, 986 sriov_sc_video_codecs_encode_array, 987 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 988 sriov_sc_video_codecs_decode_array_vcn1, 989 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1)); 990 } else { 991 amdgpu_virt_update_sriov_video_codec(adev, 992 sriov_sc_video_codecs_encode_array, 993 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 994 sriov_sc_video_codecs_decode_array_vcn0, 995 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0)); 996 } 997 } 998 999 /* Enable selfring doorbell aperture late because doorbell BAR 1000 * aperture will change if resize BAR successfully in gmc sw_init. 1001 */ 1002 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 1003 1004 return 0; 1005 } 1006 1007 static int nv_common_sw_init(void *handle) 1008 { 1009 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1010 1011 if (amdgpu_sriov_vf(adev)) 1012 xgpu_nv_mailbox_add_irq_id(adev); 1013 1014 return 0; 1015 } 1016 1017 static int nv_common_sw_fini(void *handle) 1018 { 1019 return 0; 1020 } 1021 1022 static int nv_common_hw_init(void *handle) 1023 { 1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1025 1026 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 1027 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 1028 1029 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1030 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1031 1032 /* enable aspm */ 1033 nv_program_aspm(adev); 1034 /* setup nbio registers */ 1035 adev->nbio.funcs->init_registers(adev); 1036 /* remap HDP registers to a hole in mmio space, 1037 * for the purpose of expose those registers 1038 * to process space 1039 */ 1040 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1041 adev->nbio.funcs->remap_hdp_registers(adev); 1042 /* enable the doorbell aperture */ 1043 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1044 1045 return 0; 1046 } 1047 1048 static int nv_common_hw_fini(void *handle) 1049 { 1050 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1051 1052 /* Disable the doorbell aperture and selfring doorbell aperture 1053 * separately in hw_fini because nv_enable_doorbell_aperture 1054 * has been removed and there is no need to delay disabling 1055 * selfring doorbell. 1056 */ 1057 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1058 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1059 1060 return 0; 1061 } 1062 1063 static int nv_common_suspend(void *handle) 1064 { 1065 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1066 1067 return nv_common_hw_fini(adev); 1068 } 1069 1070 static int nv_common_resume(void *handle) 1071 { 1072 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1073 1074 return nv_common_hw_init(adev); 1075 } 1076 1077 static bool nv_common_is_idle(void *handle) 1078 { 1079 return true; 1080 } 1081 1082 static int nv_common_wait_for_idle(void *handle) 1083 { 1084 return 0; 1085 } 1086 1087 static int nv_common_soft_reset(void *handle) 1088 { 1089 return 0; 1090 } 1091 1092 static int nv_common_set_clockgating_state(void *handle, 1093 enum amd_clockgating_state state) 1094 { 1095 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1096 1097 if (amdgpu_sriov_vf(adev)) 1098 return 0; 1099 1100 switch (adev->ip_versions[NBIO_HWIP][0]) { 1101 case IP_VERSION(2, 3, 0): 1102 case IP_VERSION(2, 3, 1): 1103 case IP_VERSION(2, 3, 2): 1104 case IP_VERSION(3, 3, 0): 1105 case IP_VERSION(3, 3, 1): 1106 case IP_VERSION(3, 3, 2): 1107 case IP_VERSION(3, 3, 3): 1108 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1109 state == AMD_CG_STATE_GATE); 1110 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1111 state == AMD_CG_STATE_GATE); 1112 adev->hdp.funcs->update_clock_gating(adev, 1113 state == AMD_CG_STATE_GATE); 1114 adev->smuio.funcs->update_rom_clock_gating(adev, 1115 state == AMD_CG_STATE_GATE); 1116 break; 1117 default: 1118 break; 1119 } 1120 return 0; 1121 } 1122 1123 static int nv_common_set_powergating_state(void *handle, 1124 enum amd_powergating_state state) 1125 { 1126 /* TODO */ 1127 return 0; 1128 } 1129 1130 static void nv_common_get_clockgating_state(void *handle, u64 *flags) 1131 { 1132 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1133 1134 if (amdgpu_sriov_vf(adev)) 1135 *flags = 0; 1136 1137 adev->nbio.funcs->get_clockgating_state(adev, flags); 1138 1139 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1140 1141 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1142 1143 return; 1144 } 1145 1146 static const struct amd_ip_funcs nv_common_ip_funcs = { 1147 .name = "nv_common", 1148 .early_init = nv_common_early_init, 1149 .late_init = nv_common_late_init, 1150 .sw_init = nv_common_sw_init, 1151 .sw_fini = nv_common_sw_fini, 1152 .hw_init = nv_common_hw_init, 1153 .hw_fini = nv_common_hw_fini, 1154 .suspend = nv_common_suspend, 1155 .resume = nv_common_resume, 1156 .is_idle = nv_common_is_idle, 1157 .wait_for_idle = nv_common_wait_for_idle, 1158 .soft_reset = nv_common_soft_reset, 1159 .set_clockgating_state = nv_common_set_clockgating_state, 1160 .set_powergating_state = nv_common_set_powergating_state, 1161 .get_clockgating_state = nv_common_get_clockgating_state, 1162 }; 1163