1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 74 }; 75 76 static const struct amdgpu_video_codecs nv_video_codecs_encode = 77 { 78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 79 .codec_array = nv_video_codecs_encode_array, 80 }; 81 82 /* Navi1x */ 83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 92 }; 93 94 static const struct amdgpu_video_codecs nv_video_codecs_decode = 95 { 96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 97 .codec_array = nv_video_codecs_decode_array, 98 }; 99 100 /* Sienna Cichlid */ 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 102 { 103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 104 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 111 }; 112 113 static const struct amdgpu_video_codecs sc_video_codecs_decode = 114 { 115 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 116 .codec_array = sc_video_codecs_decode_array, 117 }; 118 119 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 120 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 121 { 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 124 }; 125 126 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = 127 { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136 }; 137 138 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 139 { 140 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 141 .codec_array = sriov_sc_video_codecs_encode_array, 142 }; 143 144 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = 145 { 146 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), 147 .codec_array = sriov_sc_video_codecs_decode_array, 148 }; 149 150 /* Beige Goby*/ 151 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 153 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 154 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 155 }; 156 157 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 158 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 159 .codec_array = bg_video_codecs_decode_array, 160 }; 161 162 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 163 .codec_count = 0, 164 .codec_array = NULL, 165 }; 166 167 /* Yellow Carp*/ 168 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 169 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 170 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 171 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 172 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 173 }; 174 175 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 176 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 177 .codec_array = yc_video_codecs_decode_array, 178 }; 179 180 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 181 const struct amdgpu_video_codecs **codecs) 182 { 183 switch (adev->ip_versions[UVD_HWIP][0]) { 184 case IP_VERSION(3, 0, 0): 185 case IP_VERSION(3, 0, 64): 186 case IP_VERSION(3, 0, 192): 187 if (amdgpu_sriov_vf(adev)) { 188 if (encode) 189 *codecs = &sriov_sc_video_codecs_encode; 190 else 191 *codecs = &sriov_sc_video_codecs_decode; 192 } else { 193 if (encode) 194 *codecs = &nv_video_codecs_encode; 195 else 196 *codecs = &sc_video_codecs_decode; 197 } 198 return 0; 199 case IP_VERSION(3, 0, 16): 200 case IP_VERSION(3, 0, 2): 201 if (encode) 202 *codecs = &nv_video_codecs_encode; 203 else 204 *codecs = &sc_video_codecs_decode; 205 return 0; 206 case IP_VERSION(3, 1, 1): 207 case IP_VERSION(3, 1, 2): 208 if (encode) 209 *codecs = &nv_video_codecs_encode; 210 else 211 *codecs = &yc_video_codecs_decode; 212 return 0; 213 case IP_VERSION(3, 0, 33): 214 if (encode) 215 *codecs = &bg_video_codecs_encode; 216 else 217 *codecs = &bg_video_codecs_decode; 218 return 0; 219 case IP_VERSION(2, 0, 0): 220 case IP_VERSION(2, 0, 2): 221 if (encode) 222 *codecs = &nv_video_codecs_encode; 223 else 224 *codecs = &nv_video_codecs_decode; 225 return 0; 226 default: 227 return -EINVAL; 228 } 229 } 230 231 /* 232 * Indirect registers accessor 233 */ 234 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 235 { 236 unsigned long address, data; 237 address = adev->nbio.funcs->get_pcie_index_offset(adev); 238 data = adev->nbio.funcs->get_pcie_data_offset(adev); 239 240 return amdgpu_device_indirect_rreg(adev, address, data, reg); 241 } 242 243 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 244 { 245 unsigned long address, data; 246 247 address = adev->nbio.funcs->get_pcie_index_offset(adev); 248 data = adev->nbio.funcs->get_pcie_data_offset(adev); 249 250 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 251 } 252 253 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 254 { 255 unsigned long address, data; 256 address = adev->nbio.funcs->get_pcie_index_offset(adev); 257 data = adev->nbio.funcs->get_pcie_data_offset(adev); 258 259 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 260 } 261 262 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 263 { 264 unsigned long address, data; 265 266 address = adev->nbio.funcs->get_pcie_index_offset(adev); 267 data = adev->nbio.funcs->get_pcie_data_offset(adev); 268 269 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 270 } 271 272 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 273 { 274 unsigned long flags, address, data; 275 u32 r; 276 277 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 278 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 279 280 spin_lock_irqsave(&adev->didt_idx_lock, flags); 281 WREG32(address, (reg)); 282 r = RREG32(data); 283 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 284 return r; 285 } 286 287 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 288 { 289 unsigned long flags, address, data; 290 291 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 292 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 293 294 spin_lock_irqsave(&adev->didt_idx_lock, flags); 295 WREG32(address, (reg)); 296 WREG32(data, (v)); 297 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 298 } 299 300 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 301 { 302 return adev->nbio.funcs->get_memsize(adev); 303 } 304 305 static u32 nv_get_xclk(struct amdgpu_device *adev) 306 { 307 return adev->clock.spll.reference_freq; 308 } 309 310 311 void nv_grbm_select(struct amdgpu_device *adev, 312 u32 me, u32 pipe, u32 queue, u32 vmid) 313 { 314 u32 grbm_gfx_cntl = 0; 315 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 316 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 317 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 318 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 319 320 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 321 } 322 323 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 324 { 325 /* todo */ 326 } 327 328 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 329 { 330 /* todo */ 331 return false; 332 } 333 334 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 335 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 336 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 340 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 341 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 342 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 343 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 344 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 345 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 346 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 347 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 348 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 349 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 352 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 353 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 354 }; 355 356 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 357 u32 sh_num, u32 reg_offset) 358 { 359 uint32_t val; 360 361 mutex_lock(&adev->grbm_idx_mutex); 362 if (se_num != 0xffffffff || sh_num != 0xffffffff) 363 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 364 365 val = RREG32(reg_offset); 366 367 if (se_num != 0xffffffff || sh_num != 0xffffffff) 368 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 369 mutex_unlock(&adev->grbm_idx_mutex); 370 return val; 371 } 372 373 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 374 bool indexed, u32 se_num, 375 u32 sh_num, u32 reg_offset) 376 { 377 if (indexed) { 378 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 379 } else { 380 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 381 return adev->gfx.config.gb_addr_config; 382 return RREG32(reg_offset); 383 } 384 } 385 386 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 387 u32 sh_num, u32 reg_offset, u32 *value) 388 { 389 uint32_t i; 390 struct soc15_allowed_register_entry *en; 391 392 *value = 0; 393 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 394 en = &nv_allowed_read_registers[i]; 395 if (adev->reg_offset[en->hwip][en->inst] && 396 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 397 + en->reg_offset)) 398 continue; 399 400 *value = nv_get_register_value(adev, 401 nv_allowed_read_registers[i].grbm_indexed, 402 se_num, sh_num, reg_offset); 403 return 0; 404 } 405 return -EINVAL; 406 } 407 408 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 409 { 410 u32 i; 411 int ret = 0; 412 413 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 414 415 /* disable BM */ 416 pci_clear_master(adev->pdev); 417 418 amdgpu_device_cache_pci_state(adev->pdev); 419 420 ret = amdgpu_dpm_mode2_reset(adev); 421 if (ret) 422 dev_err(adev->dev, "GPU mode2 reset failed\n"); 423 424 amdgpu_device_load_pci_state(adev->pdev); 425 426 /* wait for asic to come out of reset */ 427 for (i = 0; i < adev->usec_timeout; i++) { 428 u32 memsize = adev->nbio.funcs->get_memsize(adev); 429 430 if (memsize != 0xffffffff) 431 break; 432 udelay(1); 433 } 434 435 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 436 437 return ret; 438 } 439 440 static enum amd_reset_method 441 nv_asic_reset_method(struct amdgpu_device *adev) 442 { 443 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 444 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 445 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 446 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 447 return amdgpu_reset_method; 448 449 if (amdgpu_reset_method != -1) 450 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 451 amdgpu_reset_method); 452 453 switch (adev->ip_versions[MP1_HWIP][0]) { 454 case IP_VERSION(11, 5, 0): 455 case IP_VERSION(13, 0, 1): 456 case IP_VERSION(13, 0, 3): 457 case IP_VERSION(13, 0, 5): 458 case IP_VERSION(13, 0, 8): 459 return AMD_RESET_METHOD_MODE2; 460 case IP_VERSION(11, 0, 7): 461 case IP_VERSION(11, 0, 11): 462 case IP_VERSION(11, 0, 12): 463 case IP_VERSION(11, 0, 13): 464 return AMD_RESET_METHOD_MODE1; 465 default: 466 if (amdgpu_dpm_is_baco_supported(adev)) 467 return AMD_RESET_METHOD_BACO; 468 else 469 return AMD_RESET_METHOD_MODE1; 470 } 471 } 472 473 static int nv_asic_reset(struct amdgpu_device *adev) 474 { 475 int ret = 0; 476 477 switch (nv_asic_reset_method(adev)) { 478 case AMD_RESET_METHOD_PCI: 479 dev_info(adev->dev, "PCI reset\n"); 480 ret = amdgpu_device_pci_reset(adev); 481 break; 482 case AMD_RESET_METHOD_BACO: 483 dev_info(adev->dev, "BACO reset\n"); 484 ret = amdgpu_dpm_baco_reset(adev); 485 break; 486 case AMD_RESET_METHOD_MODE2: 487 dev_info(adev->dev, "MODE2 reset\n"); 488 ret = nv_asic_mode2_reset(adev); 489 break; 490 default: 491 dev_info(adev->dev, "MODE1 reset\n"); 492 ret = amdgpu_device_mode1_reset(adev); 493 break; 494 } 495 496 return ret; 497 } 498 499 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 500 { 501 /* todo */ 502 return 0; 503 } 504 505 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 506 { 507 /* todo */ 508 return 0; 509 } 510 511 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 512 { 513 if (pci_is_root_bus(adev->pdev->bus)) 514 return; 515 516 if (amdgpu_pcie_gen2 == 0) 517 return; 518 519 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 520 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 521 return; 522 523 /* todo */ 524 } 525 526 static void nv_program_aspm(struct amdgpu_device *adev) 527 { 528 if (!amdgpu_device_should_use_aspm(adev)) 529 return; 530 531 if (!(adev->flags & AMD_IS_APU) && 532 (adev->nbio.funcs->program_aspm)) 533 adev->nbio.funcs->program_aspm(adev); 534 535 } 536 537 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 538 bool enable) 539 { 540 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 541 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 542 } 543 544 const struct amdgpu_ip_block_version nv_common_ip_block = 545 { 546 .type = AMD_IP_BLOCK_TYPE_COMMON, 547 .major = 1, 548 .minor = 0, 549 .rev = 0, 550 .funcs = &nv_common_ip_funcs, 551 }; 552 553 void nv_set_virt_ops(struct amdgpu_device *adev) 554 { 555 adev->virt.ops = &xgpu_nv_virt_ops; 556 } 557 558 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 559 { 560 return adev->nbio.funcs->get_rev_id(adev); 561 } 562 563 static bool nv_need_full_reset(struct amdgpu_device *adev) 564 { 565 return true; 566 } 567 568 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 569 { 570 u32 sol_reg; 571 572 if (adev->flags & AMD_IS_APU) 573 return false; 574 575 /* Check sOS sign of life register to confirm sys driver and sOS 576 * are already been loaded. 577 */ 578 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 579 if (sol_reg) 580 return true; 581 582 return false; 583 } 584 585 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 586 { 587 588 /* TODO 589 * dummy implement for pcie_replay_count sysfs interface 590 * */ 591 592 return 0; 593 } 594 595 static void nv_init_doorbell_index(struct amdgpu_device *adev) 596 { 597 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 598 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 599 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 600 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 601 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 602 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 603 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 604 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 605 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 606 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 607 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 608 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 609 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 610 adev->doorbell_index.gfx_userqueue_start = 611 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 612 adev->doorbell_index.gfx_userqueue_end = 613 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 614 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 615 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 616 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 617 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 618 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 619 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 620 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 621 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 622 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 623 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 624 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 625 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 626 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 627 628 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 629 adev->doorbell_index.sdma_doorbell_range = 20; 630 } 631 632 static void nv_pre_asic_init(struct amdgpu_device *adev) 633 { 634 } 635 636 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 637 bool enter) 638 { 639 if (enter) 640 amdgpu_gfx_rlc_enter_safe_mode(adev); 641 else 642 amdgpu_gfx_rlc_exit_safe_mode(adev); 643 644 if (adev->gfx.funcs->update_perfmon_mgcg) 645 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 646 647 if (!(adev->flags & AMD_IS_APU) && 648 (adev->nbio.funcs->enable_aspm) && 649 amdgpu_device_should_use_aspm(adev)) 650 adev->nbio.funcs->enable_aspm(adev, !enter); 651 652 return 0; 653 } 654 655 static const struct amdgpu_asic_funcs nv_asic_funcs = 656 { 657 .read_disabled_bios = &nv_read_disabled_bios, 658 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 659 .read_register = &nv_read_register, 660 .reset = &nv_asic_reset, 661 .reset_method = &nv_asic_reset_method, 662 .set_vga_state = &nv_vga_set_state, 663 .get_xclk = &nv_get_xclk, 664 .set_uvd_clocks = &nv_set_uvd_clocks, 665 .set_vce_clocks = &nv_set_vce_clocks, 666 .get_config_memsize = &nv_get_config_memsize, 667 .init_doorbell_index = &nv_init_doorbell_index, 668 .need_full_reset = &nv_need_full_reset, 669 .need_reset_on_init = &nv_need_reset_on_init, 670 .get_pcie_replay_count = &nv_get_pcie_replay_count, 671 .supports_baco = &amdgpu_dpm_is_baco_supported, 672 .pre_asic_init = &nv_pre_asic_init, 673 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 674 .query_video_codecs = &nv_query_video_codecs, 675 }; 676 677 static int nv_common_early_init(void *handle) 678 { 679 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 680 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 681 682 if (!amdgpu_sriov_vf(adev)) { 683 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 684 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 685 } 686 adev->smc_rreg = NULL; 687 adev->smc_wreg = NULL; 688 adev->pcie_rreg = &nv_pcie_rreg; 689 adev->pcie_wreg = &nv_pcie_wreg; 690 adev->pcie_rreg64 = &nv_pcie_rreg64; 691 adev->pcie_wreg64 = &nv_pcie_wreg64; 692 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 693 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 694 695 /* TODO: will add them during VCN v2 implementation */ 696 adev->uvd_ctx_rreg = NULL; 697 adev->uvd_ctx_wreg = NULL; 698 699 adev->didt_rreg = &nv_didt_rreg; 700 adev->didt_wreg = &nv_didt_wreg; 701 702 adev->asic_funcs = &nv_asic_funcs; 703 704 adev->rev_id = nv_get_rev_id(adev); 705 adev->external_rev_id = 0xff; 706 /* TODO: split the GC and PG flags based on the relevant IP version for which 707 * they are relevant. 708 */ 709 switch (adev->ip_versions[GC_HWIP][0]) { 710 case IP_VERSION(10, 1, 10): 711 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 712 AMD_CG_SUPPORT_GFX_CGCG | 713 AMD_CG_SUPPORT_IH_CG | 714 AMD_CG_SUPPORT_HDP_MGCG | 715 AMD_CG_SUPPORT_HDP_LS | 716 AMD_CG_SUPPORT_SDMA_MGCG | 717 AMD_CG_SUPPORT_SDMA_LS | 718 AMD_CG_SUPPORT_MC_MGCG | 719 AMD_CG_SUPPORT_MC_LS | 720 AMD_CG_SUPPORT_ATHUB_MGCG | 721 AMD_CG_SUPPORT_ATHUB_LS | 722 AMD_CG_SUPPORT_VCN_MGCG | 723 AMD_CG_SUPPORT_JPEG_MGCG | 724 AMD_CG_SUPPORT_BIF_MGCG | 725 AMD_CG_SUPPORT_BIF_LS; 726 adev->pg_flags = AMD_PG_SUPPORT_VCN | 727 AMD_PG_SUPPORT_VCN_DPG | 728 AMD_PG_SUPPORT_JPEG | 729 AMD_PG_SUPPORT_ATHUB; 730 adev->external_rev_id = adev->rev_id + 0x1; 731 break; 732 case IP_VERSION(10, 1, 1): 733 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 734 AMD_CG_SUPPORT_GFX_CGCG | 735 AMD_CG_SUPPORT_IH_CG | 736 AMD_CG_SUPPORT_HDP_MGCG | 737 AMD_CG_SUPPORT_HDP_LS | 738 AMD_CG_SUPPORT_SDMA_MGCG | 739 AMD_CG_SUPPORT_SDMA_LS | 740 AMD_CG_SUPPORT_MC_MGCG | 741 AMD_CG_SUPPORT_MC_LS | 742 AMD_CG_SUPPORT_ATHUB_MGCG | 743 AMD_CG_SUPPORT_ATHUB_LS | 744 AMD_CG_SUPPORT_VCN_MGCG | 745 AMD_CG_SUPPORT_JPEG_MGCG | 746 AMD_CG_SUPPORT_BIF_MGCG | 747 AMD_CG_SUPPORT_BIF_LS; 748 adev->pg_flags = AMD_PG_SUPPORT_VCN | 749 AMD_PG_SUPPORT_JPEG | 750 AMD_PG_SUPPORT_VCN_DPG; 751 adev->external_rev_id = adev->rev_id + 20; 752 break; 753 case IP_VERSION(10, 1, 2): 754 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 755 AMD_CG_SUPPORT_GFX_MGLS | 756 AMD_CG_SUPPORT_GFX_CGCG | 757 AMD_CG_SUPPORT_GFX_CP_LS | 758 AMD_CG_SUPPORT_GFX_RLC_LS | 759 AMD_CG_SUPPORT_IH_CG | 760 AMD_CG_SUPPORT_HDP_MGCG | 761 AMD_CG_SUPPORT_HDP_LS | 762 AMD_CG_SUPPORT_SDMA_MGCG | 763 AMD_CG_SUPPORT_SDMA_LS | 764 AMD_CG_SUPPORT_MC_MGCG | 765 AMD_CG_SUPPORT_MC_LS | 766 AMD_CG_SUPPORT_ATHUB_MGCG | 767 AMD_CG_SUPPORT_ATHUB_LS | 768 AMD_CG_SUPPORT_VCN_MGCG | 769 AMD_CG_SUPPORT_JPEG_MGCG; 770 adev->pg_flags = AMD_PG_SUPPORT_VCN | 771 AMD_PG_SUPPORT_VCN_DPG | 772 AMD_PG_SUPPORT_JPEG | 773 AMD_PG_SUPPORT_ATHUB; 774 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 775 * as a consequence, the rev_id and external_rev_id are wrong. 776 * workaround it by hardcoding rev_id to 0 (default value). 777 */ 778 if (amdgpu_sriov_vf(adev)) 779 adev->rev_id = 0; 780 adev->external_rev_id = adev->rev_id + 0xa; 781 break; 782 case IP_VERSION(10, 3, 0): 783 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 784 AMD_CG_SUPPORT_GFX_CGCG | 785 AMD_CG_SUPPORT_GFX_CGLS | 786 AMD_CG_SUPPORT_GFX_3D_CGCG | 787 AMD_CG_SUPPORT_MC_MGCG | 788 AMD_CG_SUPPORT_VCN_MGCG | 789 AMD_CG_SUPPORT_JPEG_MGCG | 790 AMD_CG_SUPPORT_HDP_MGCG | 791 AMD_CG_SUPPORT_HDP_LS | 792 AMD_CG_SUPPORT_IH_CG | 793 AMD_CG_SUPPORT_MC_LS; 794 adev->pg_flags = AMD_PG_SUPPORT_VCN | 795 AMD_PG_SUPPORT_VCN_DPG | 796 AMD_PG_SUPPORT_JPEG | 797 AMD_PG_SUPPORT_ATHUB | 798 AMD_PG_SUPPORT_MMHUB; 799 if (amdgpu_sriov_vf(adev)) { 800 /* hypervisor control CG and PG enablement */ 801 adev->cg_flags = 0; 802 adev->pg_flags = 0; 803 } 804 adev->external_rev_id = adev->rev_id + 0x28; 805 break; 806 case IP_VERSION(10, 3, 2): 807 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 808 AMD_CG_SUPPORT_GFX_CGCG | 809 AMD_CG_SUPPORT_GFX_CGLS | 810 AMD_CG_SUPPORT_GFX_3D_CGCG | 811 AMD_CG_SUPPORT_VCN_MGCG | 812 AMD_CG_SUPPORT_JPEG_MGCG | 813 AMD_CG_SUPPORT_MC_MGCG | 814 AMD_CG_SUPPORT_MC_LS | 815 AMD_CG_SUPPORT_HDP_MGCG | 816 AMD_CG_SUPPORT_HDP_LS | 817 AMD_CG_SUPPORT_IH_CG; 818 adev->pg_flags = AMD_PG_SUPPORT_VCN | 819 AMD_PG_SUPPORT_VCN_DPG | 820 AMD_PG_SUPPORT_JPEG | 821 AMD_PG_SUPPORT_ATHUB | 822 AMD_PG_SUPPORT_MMHUB; 823 adev->external_rev_id = adev->rev_id + 0x32; 824 break; 825 case IP_VERSION(10, 3, 1): 826 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 827 AMD_CG_SUPPORT_GFX_MGLS | 828 AMD_CG_SUPPORT_GFX_CP_LS | 829 AMD_CG_SUPPORT_GFX_RLC_LS | 830 AMD_CG_SUPPORT_GFX_CGCG | 831 AMD_CG_SUPPORT_GFX_CGLS | 832 AMD_CG_SUPPORT_GFX_3D_CGCG | 833 AMD_CG_SUPPORT_GFX_3D_CGLS | 834 AMD_CG_SUPPORT_MC_MGCG | 835 AMD_CG_SUPPORT_MC_LS | 836 AMD_CG_SUPPORT_GFX_FGCG | 837 AMD_CG_SUPPORT_VCN_MGCG | 838 AMD_CG_SUPPORT_SDMA_MGCG | 839 AMD_CG_SUPPORT_SDMA_LS | 840 AMD_CG_SUPPORT_JPEG_MGCG; 841 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 842 AMD_PG_SUPPORT_VCN | 843 AMD_PG_SUPPORT_VCN_DPG | 844 AMD_PG_SUPPORT_JPEG; 845 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 846 adev->external_rev_id = adev->rev_id + 0x01; 847 break; 848 case IP_VERSION(10, 3, 4): 849 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 850 AMD_CG_SUPPORT_GFX_CGCG | 851 AMD_CG_SUPPORT_GFX_CGLS | 852 AMD_CG_SUPPORT_GFX_3D_CGCG | 853 AMD_CG_SUPPORT_VCN_MGCG | 854 AMD_CG_SUPPORT_JPEG_MGCG | 855 AMD_CG_SUPPORT_MC_MGCG | 856 AMD_CG_SUPPORT_MC_LS | 857 AMD_CG_SUPPORT_HDP_MGCG | 858 AMD_CG_SUPPORT_HDP_LS | 859 AMD_CG_SUPPORT_IH_CG; 860 adev->pg_flags = AMD_PG_SUPPORT_VCN | 861 AMD_PG_SUPPORT_VCN_DPG | 862 AMD_PG_SUPPORT_JPEG | 863 AMD_PG_SUPPORT_ATHUB | 864 AMD_PG_SUPPORT_MMHUB; 865 adev->external_rev_id = adev->rev_id + 0x3c; 866 break; 867 case IP_VERSION(10, 3, 5): 868 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 869 AMD_CG_SUPPORT_GFX_CGCG | 870 AMD_CG_SUPPORT_GFX_CGLS | 871 AMD_CG_SUPPORT_GFX_3D_CGCG | 872 AMD_CG_SUPPORT_MC_MGCG | 873 AMD_CG_SUPPORT_MC_LS | 874 AMD_CG_SUPPORT_HDP_MGCG | 875 AMD_CG_SUPPORT_HDP_LS | 876 AMD_CG_SUPPORT_IH_CG | 877 AMD_CG_SUPPORT_VCN_MGCG; 878 adev->pg_flags = AMD_PG_SUPPORT_VCN | 879 AMD_PG_SUPPORT_VCN_DPG | 880 AMD_PG_SUPPORT_ATHUB | 881 AMD_PG_SUPPORT_MMHUB; 882 adev->external_rev_id = adev->rev_id + 0x46; 883 break; 884 case IP_VERSION(10, 3, 3): 885 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 886 AMD_CG_SUPPORT_GFX_MGLS | 887 AMD_CG_SUPPORT_GFX_CGCG | 888 AMD_CG_SUPPORT_GFX_CGLS | 889 AMD_CG_SUPPORT_GFX_3D_CGCG | 890 AMD_CG_SUPPORT_GFX_3D_CGLS | 891 AMD_CG_SUPPORT_GFX_RLC_LS | 892 AMD_CG_SUPPORT_GFX_CP_LS | 893 AMD_CG_SUPPORT_GFX_FGCG | 894 AMD_CG_SUPPORT_MC_MGCG | 895 AMD_CG_SUPPORT_MC_LS | 896 AMD_CG_SUPPORT_SDMA_LS | 897 AMD_CG_SUPPORT_HDP_MGCG | 898 AMD_CG_SUPPORT_HDP_LS | 899 AMD_CG_SUPPORT_ATHUB_MGCG | 900 AMD_CG_SUPPORT_ATHUB_LS | 901 AMD_CG_SUPPORT_IH_CG | 902 AMD_CG_SUPPORT_VCN_MGCG | 903 AMD_CG_SUPPORT_JPEG_MGCG; 904 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 905 AMD_PG_SUPPORT_VCN | 906 AMD_PG_SUPPORT_VCN_DPG | 907 AMD_PG_SUPPORT_JPEG; 908 if (adev->pdev->device == 0x1681) 909 adev->external_rev_id = 0x20; 910 else 911 adev->external_rev_id = adev->rev_id + 0x01; 912 break; 913 case IP_VERSION(10, 1, 3): 914 case IP_VERSION(10, 1, 4): 915 adev->cg_flags = 0; 916 adev->pg_flags = 0; 917 adev->external_rev_id = adev->rev_id + 0x82; 918 break; 919 case IP_VERSION(10, 3, 6): 920 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 921 AMD_CG_SUPPORT_GFX_MGLS | 922 AMD_CG_SUPPORT_GFX_CGCG | 923 AMD_CG_SUPPORT_GFX_CGLS | 924 AMD_CG_SUPPORT_GFX_3D_CGCG | 925 AMD_CG_SUPPORT_GFX_3D_CGLS | 926 AMD_CG_SUPPORT_GFX_RLC_LS | 927 AMD_CG_SUPPORT_GFX_CP_LS | 928 AMD_CG_SUPPORT_GFX_FGCG | 929 AMD_CG_SUPPORT_MC_MGCG | 930 AMD_CG_SUPPORT_MC_LS | 931 AMD_CG_SUPPORT_SDMA_LS | 932 AMD_CG_SUPPORT_HDP_MGCG | 933 AMD_CG_SUPPORT_HDP_LS | 934 AMD_CG_SUPPORT_ATHUB_MGCG | 935 AMD_CG_SUPPORT_ATHUB_LS | 936 AMD_CG_SUPPORT_IH_CG | 937 AMD_CG_SUPPORT_VCN_MGCG | 938 AMD_CG_SUPPORT_JPEG_MGCG; 939 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 940 AMD_PG_SUPPORT_VCN | 941 AMD_PG_SUPPORT_VCN_DPG | 942 AMD_PG_SUPPORT_JPEG; 943 adev->external_rev_id = adev->rev_id + 0x01; 944 break; 945 case IP_VERSION(10, 3, 7): 946 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 947 AMD_CG_SUPPORT_GFX_MGLS | 948 AMD_CG_SUPPORT_GFX_CGCG | 949 AMD_CG_SUPPORT_GFX_CGLS | 950 AMD_CG_SUPPORT_GFX_3D_CGCG | 951 AMD_CG_SUPPORT_GFX_3D_CGLS | 952 AMD_CG_SUPPORT_GFX_RLC_LS | 953 AMD_CG_SUPPORT_GFX_CP_LS | 954 AMD_CG_SUPPORT_GFX_FGCG | 955 AMD_CG_SUPPORT_MC_MGCG | 956 AMD_CG_SUPPORT_MC_LS | 957 AMD_CG_SUPPORT_SDMA_LS | 958 AMD_CG_SUPPORT_HDP_MGCG | 959 AMD_CG_SUPPORT_HDP_LS | 960 AMD_CG_SUPPORT_ATHUB_MGCG | 961 AMD_CG_SUPPORT_ATHUB_LS | 962 AMD_CG_SUPPORT_IH_CG | 963 AMD_CG_SUPPORT_VCN_MGCG | 964 AMD_CG_SUPPORT_JPEG_MGCG; 965 adev->pg_flags = AMD_PG_SUPPORT_VCN | 966 AMD_PG_SUPPORT_VCN_DPG | 967 AMD_PG_SUPPORT_JPEG | 968 AMD_PG_SUPPORT_GFX_PG; 969 adev->external_rev_id = adev->rev_id + 0x01; 970 break; 971 default: 972 /* FIXME: not supported yet */ 973 return -EINVAL; 974 } 975 976 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 977 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 978 AMD_PG_SUPPORT_VCN_DPG | 979 AMD_PG_SUPPORT_JPEG); 980 981 if (amdgpu_sriov_vf(adev)) { 982 amdgpu_virt_init_setting(adev); 983 xgpu_nv_mailbox_set_irq_funcs(adev); 984 } 985 986 return 0; 987 } 988 989 static int nv_common_late_init(void *handle) 990 { 991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 992 993 if (amdgpu_sriov_vf(adev)) { 994 xgpu_nv_mailbox_get_irq(adev); 995 amdgpu_virt_update_sriov_video_codec(adev, 996 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 997 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); 998 } 999 1000 return 0; 1001 } 1002 1003 static int nv_common_sw_init(void *handle) 1004 { 1005 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1006 1007 if (amdgpu_sriov_vf(adev)) 1008 xgpu_nv_mailbox_add_irq_id(adev); 1009 1010 return 0; 1011 } 1012 1013 static int nv_common_sw_fini(void *handle) 1014 { 1015 return 0; 1016 } 1017 1018 static int nv_common_hw_init(void *handle) 1019 { 1020 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1021 1022 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 1023 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 1024 1025 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1026 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1027 1028 /* enable pcie gen2/3 link */ 1029 nv_pcie_gen3_enable(adev); 1030 /* enable aspm */ 1031 nv_program_aspm(adev); 1032 /* setup nbio registers */ 1033 adev->nbio.funcs->init_registers(adev); 1034 /* remap HDP registers to a hole in mmio space, 1035 * for the purpose of expose those registers 1036 * to process space 1037 */ 1038 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1039 adev->nbio.funcs->remap_hdp_registers(adev); 1040 /* enable the doorbell aperture */ 1041 nv_enable_doorbell_aperture(adev, true); 1042 1043 return 0; 1044 } 1045 1046 static int nv_common_hw_fini(void *handle) 1047 { 1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1049 1050 /* disable the doorbell aperture */ 1051 nv_enable_doorbell_aperture(adev, false); 1052 1053 return 0; 1054 } 1055 1056 static int nv_common_suspend(void *handle) 1057 { 1058 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1059 1060 return nv_common_hw_fini(adev); 1061 } 1062 1063 static int nv_common_resume(void *handle) 1064 { 1065 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1066 1067 return nv_common_hw_init(adev); 1068 } 1069 1070 static bool nv_common_is_idle(void *handle) 1071 { 1072 return true; 1073 } 1074 1075 static int nv_common_wait_for_idle(void *handle) 1076 { 1077 return 0; 1078 } 1079 1080 static int nv_common_soft_reset(void *handle) 1081 { 1082 return 0; 1083 } 1084 1085 static int nv_common_set_clockgating_state(void *handle, 1086 enum amd_clockgating_state state) 1087 { 1088 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1089 1090 if (amdgpu_sriov_vf(adev)) 1091 return 0; 1092 1093 switch (adev->ip_versions[NBIO_HWIP][0]) { 1094 case IP_VERSION(2, 3, 0): 1095 case IP_VERSION(2, 3, 1): 1096 case IP_VERSION(2, 3, 2): 1097 case IP_VERSION(3, 3, 0): 1098 case IP_VERSION(3, 3, 1): 1099 case IP_VERSION(3, 3, 2): 1100 case IP_VERSION(3, 3, 3): 1101 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1102 state == AMD_CG_STATE_GATE); 1103 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1104 state == AMD_CG_STATE_GATE); 1105 adev->hdp.funcs->update_clock_gating(adev, 1106 state == AMD_CG_STATE_GATE); 1107 adev->smuio.funcs->update_rom_clock_gating(adev, 1108 state == AMD_CG_STATE_GATE); 1109 break; 1110 default: 1111 break; 1112 } 1113 return 0; 1114 } 1115 1116 static int nv_common_set_powergating_state(void *handle, 1117 enum amd_powergating_state state) 1118 { 1119 /* TODO */ 1120 return 0; 1121 } 1122 1123 static void nv_common_get_clockgating_state(void *handle, u64 *flags) 1124 { 1125 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1126 1127 if (amdgpu_sriov_vf(adev)) 1128 *flags = 0; 1129 1130 adev->nbio.funcs->get_clockgating_state(adev, flags); 1131 1132 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1133 1134 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1135 1136 return; 1137 } 1138 1139 static const struct amd_ip_funcs nv_common_ip_funcs = { 1140 .name = "nv_common", 1141 .early_init = nv_common_early_init, 1142 .late_init = nv_common_late_init, 1143 .sw_init = nv_common_sw_init, 1144 .sw_fini = nv_common_sw_fini, 1145 .hw_init = nv_common_hw_init, 1146 .hw_fini = nv_common_hw_fini, 1147 .suspend = nv_common_suspend, 1148 .resume = nv_common_resume, 1149 .is_idle = nv_common_is_idle, 1150 .wait_for_idle = nv_common_wait_for_idle, 1151 .soft_reset = nv_common_soft_reset, 1152 .set_clockgating_state = nv_common_set_clockgating_state, 1153 .set_powergating_state = nv_common_set_powergating_state, 1154 .get_clockgating_state = nv_common_get_clockgating_state, 1155 }; 1156