1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "hdp/hdp_5_0_0_sh_mask.h" 43 #include "smuio/smuio_11_0_0_offset.h" 44 #include "mp/mp_11_0_offset.h" 45 46 #include "soc15.h" 47 #include "soc15_common.h" 48 #include "gmc_v10_0.h" 49 #include "gfxhub_v2_0.h" 50 #include "mmhub_v2_0.h" 51 #include "nbio_v2_3.h" 52 #include "nbio_v7_2.h" 53 #include "nv.h" 54 #include "navi10_ih.h" 55 #include "gfx_v10_0.h" 56 #include "sdma_v5_0.h" 57 #include "sdma_v5_2.h" 58 #include "vcn_v2_0.h" 59 #include "jpeg_v2_0.h" 60 #include "vcn_v3_0.h" 61 #include "jpeg_v3_0.h" 62 #include "dce_virtual.h" 63 #include "mes_v10_1.h" 64 #include "mxgpu_nv.h" 65 66 static const struct amd_ip_funcs nv_common_ip_funcs; 67 68 /* 69 * Indirect registers accessor 70 */ 71 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 72 { 73 unsigned long address, data; 74 address = adev->nbio.funcs->get_pcie_index_offset(adev); 75 data = adev->nbio.funcs->get_pcie_data_offset(adev); 76 77 return amdgpu_device_indirect_rreg(adev, address, data, reg); 78 } 79 80 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 81 { 82 unsigned long address, data; 83 84 address = adev->nbio.funcs->get_pcie_index_offset(adev); 85 data = adev->nbio.funcs->get_pcie_data_offset(adev); 86 87 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 88 } 89 90 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 91 { 92 unsigned long address, data; 93 address = adev->nbio.funcs->get_pcie_index_offset(adev); 94 data = adev->nbio.funcs->get_pcie_data_offset(adev); 95 96 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 97 } 98 99 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 100 { 101 unsigned long flags, address, data; 102 u32 r; 103 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 104 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 105 106 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 107 WREG32(address, reg * 4); 108 (void)RREG32(address); 109 r = RREG32(data); 110 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 111 return r; 112 } 113 114 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 115 { 116 unsigned long address, data; 117 118 address = adev->nbio.funcs->get_pcie_index_offset(adev); 119 data = adev->nbio.funcs->get_pcie_data_offset(adev); 120 121 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 122 } 123 124 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 125 { 126 unsigned long flags, address, data; 127 128 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 129 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 130 131 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 132 WREG32(address, reg * 4); 133 (void)RREG32(address); 134 WREG32(data, v); 135 (void)RREG32(data); 136 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 137 } 138 139 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 140 { 141 unsigned long flags, address, data; 142 u32 r; 143 144 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 145 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 146 147 spin_lock_irqsave(&adev->didt_idx_lock, flags); 148 WREG32(address, (reg)); 149 r = RREG32(data); 150 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 151 return r; 152 } 153 154 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 155 { 156 unsigned long flags, address, data; 157 158 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 159 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 160 161 spin_lock_irqsave(&adev->didt_idx_lock, flags); 162 WREG32(address, (reg)); 163 WREG32(data, (v)); 164 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 165 } 166 167 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 168 { 169 return adev->nbio.funcs->get_memsize(adev); 170 } 171 172 static u32 nv_get_xclk(struct amdgpu_device *adev) 173 { 174 return adev->clock.spll.reference_freq; 175 } 176 177 178 void nv_grbm_select(struct amdgpu_device *adev, 179 u32 me, u32 pipe, u32 queue, u32 vmid) 180 { 181 u32 grbm_gfx_cntl = 0; 182 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 183 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 184 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 185 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 186 187 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 188 } 189 190 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 191 { 192 /* todo */ 193 } 194 195 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 196 { 197 /* todo */ 198 return false; 199 } 200 201 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 202 u8 *bios, u32 length_bytes) 203 { 204 u32 *dw_ptr; 205 u32 i, length_dw; 206 207 if (bios == NULL) 208 return false; 209 if (length_bytes == 0) 210 return false; 211 /* APU vbios image is part of sbios image */ 212 if (adev->flags & AMD_IS_APU) 213 return false; 214 215 dw_ptr = (u32 *)bios; 216 length_dw = ALIGN(length_bytes, 4) / 4; 217 218 /* set rom index to 0 */ 219 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 220 /* read out the rom data */ 221 for (i = 0; i < length_dw; i++) 222 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 223 224 return true; 225 } 226 227 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 228 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 229 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 230 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 231 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 232 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 233 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 234 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 235 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 236 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 237 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 238 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 239 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 240 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 241 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 242 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 243 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 244 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 245 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 246 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 247 }; 248 249 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 250 u32 sh_num, u32 reg_offset) 251 { 252 uint32_t val; 253 254 mutex_lock(&adev->grbm_idx_mutex); 255 if (se_num != 0xffffffff || sh_num != 0xffffffff) 256 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 257 258 val = RREG32(reg_offset); 259 260 if (se_num != 0xffffffff || sh_num != 0xffffffff) 261 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 262 mutex_unlock(&adev->grbm_idx_mutex); 263 return val; 264 } 265 266 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 267 bool indexed, u32 se_num, 268 u32 sh_num, u32 reg_offset) 269 { 270 if (indexed) { 271 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 272 } else { 273 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 274 return adev->gfx.config.gb_addr_config; 275 return RREG32(reg_offset); 276 } 277 } 278 279 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 280 u32 sh_num, u32 reg_offset, u32 *value) 281 { 282 uint32_t i; 283 struct soc15_allowed_register_entry *en; 284 285 *value = 0; 286 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 287 en = &nv_allowed_read_registers[i]; 288 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 289 reg_offset != 290 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 291 continue; 292 293 *value = nv_get_register_value(adev, 294 nv_allowed_read_registers[i].grbm_indexed, 295 se_num, sh_num, reg_offset); 296 return 0; 297 } 298 return -EINVAL; 299 } 300 301 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 302 { 303 u32 i; 304 int ret = 0; 305 306 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 307 308 /* disable BM */ 309 pci_clear_master(adev->pdev); 310 311 amdgpu_device_cache_pci_state(adev->pdev); 312 313 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 314 dev_info(adev->dev, "GPU smu mode1 reset\n"); 315 ret = amdgpu_dpm_mode1_reset(adev); 316 } else { 317 dev_info(adev->dev, "GPU psp mode1 reset\n"); 318 ret = psp_gpu_reset(adev); 319 } 320 321 if (ret) 322 dev_err(adev->dev, "GPU mode1 reset failed\n"); 323 amdgpu_device_load_pci_state(adev->pdev); 324 325 /* wait for asic to come out of reset */ 326 for (i = 0; i < adev->usec_timeout; i++) { 327 u32 memsize = adev->nbio.funcs->get_memsize(adev); 328 329 if (memsize != 0xffffffff) 330 break; 331 udelay(1); 332 } 333 334 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 335 336 return ret; 337 } 338 339 static bool nv_asic_supports_baco(struct amdgpu_device *adev) 340 { 341 struct smu_context *smu = &adev->smu; 342 343 if (smu_baco_is_support(smu)) 344 return true; 345 else 346 return false; 347 } 348 349 static enum amd_reset_method 350 nv_asic_reset_method(struct amdgpu_device *adev) 351 { 352 struct smu_context *smu = &adev->smu; 353 354 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 355 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 356 return amdgpu_reset_method; 357 358 if (amdgpu_reset_method != -1) 359 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 360 amdgpu_reset_method); 361 362 switch (adev->asic_type) { 363 case CHIP_SIENNA_CICHLID: 364 case CHIP_NAVY_FLOUNDER: 365 return AMD_RESET_METHOD_MODE1; 366 default: 367 if (smu_baco_is_support(smu)) 368 return AMD_RESET_METHOD_BACO; 369 else 370 return AMD_RESET_METHOD_MODE1; 371 } 372 } 373 374 static int nv_asic_reset(struct amdgpu_device *adev) 375 { 376 int ret = 0; 377 struct smu_context *smu = &adev->smu; 378 379 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 380 dev_info(adev->dev, "BACO reset\n"); 381 382 ret = smu_baco_enter(smu); 383 if (ret) 384 return ret; 385 ret = smu_baco_exit(smu); 386 if (ret) 387 return ret; 388 } else { 389 dev_info(adev->dev, "MODE1 reset\n"); 390 ret = nv_asic_mode1_reset(adev); 391 } 392 393 return ret; 394 } 395 396 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 397 { 398 /* todo */ 399 return 0; 400 } 401 402 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 403 { 404 /* todo */ 405 return 0; 406 } 407 408 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 409 { 410 if (pci_is_root_bus(adev->pdev->bus)) 411 return; 412 413 if (amdgpu_pcie_gen2 == 0) 414 return; 415 416 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 417 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 418 return; 419 420 /* todo */ 421 } 422 423 static void nv_program_aspm(struct amdgpu_device *adev) 424 { 425 426 if (amdgpu_aspm == 0) 427 return; 428 429 /* todo */ 430 } 431 432 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 433 bool enable) 434 { 435 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 436 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 437 } 438 439 static const struct amdgpu_ip_block_version nv_common_ip_block = 440 { 441 .type = AMD_IP_BLOCK_TYPE_COMMON, 442 .major = 1, 443 .minor = 0, 444 .rev = 0, 445 .funcs = &nv_common_ip_funcs, 446 }; 447 448 static int nv_reg_base_init(struct amdgpu_device *adev) 449 { 450 int r; 451 452 if (amdgpu_discovery) { 453 r = amdgpu_discovery_reg_base_init(adev); 454 if (r) { 455 DRM_WARN("failed to init reg base from ip discovery table, " 456 "fallback to legacy init method\n"); 457 goto legacy_init; 458 } 459 460 return 0; 461 } 462 463 legacy_init: 464 switch (adev->asic_type) { 465 case CHIP_NAVI10: 466 navi10_reg_base_init(adev); 467 break; 468 case CHIP_NAVI14: 469 navi14_reg_base_init(adev); 470 break; 471 case CHIP_NAVI12: 472 navi12_reg_base_init(adev); 473 break; 474 case CHIP_SIENNA_CICHLID: 475 case CHIP_NAVY_FLOUNDER: 476 sienna_cichlid_reg_base_init(adev); 477 break; 478 case CHIP_VANGOGH: 479 vangogh_reg_base_init(adev); 480 break; 481 case CHIP_DIMGREY_CAVEFISH: 482 dimgrey_cavefish_reg_base_init(adev); 483 break; 484 default: 485 return -EINVAL; 486 } 487 488 return 0; 489 } 490 491 void nv_set_virt_ops(struct amdgpu_device *adev) 492 { 493 adev->virt.ops = &xgpu_nv_virt_ops; 494 } 495 496 static bool nv_is_headless_sku(struct pci_dev *pdev) 497 { 498 if ((pdev->device == 0x731E && 499 (pdev->revision == 0xC6 || pdev->revision == 0xC7)) || 500 (pdev->device == 0x7340 && pdev->revision == 0xC9)) 501 return true; 502 return false; 503 } 504 505 int nv_set_ip_blocks(struct amdgpu_device *adev) 506 { 507 int r; 508 509 if (adev->flags & AMD_IS_APU) { 510 adev->nbio.funcs = &nbio_v7_2_funcs; 511 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 512 } else { 513 adev->nbio.funcs = &nbio_v2_3_funcs; 514 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 515 } 516 517 if (adev->asic_type == CHIP_SIENNA_CICHLID) 518 adev->gmc.xgmi.supported = true; 519 520 /* Set IP register base before any HW register access */ 521 r = nv_reg_base_init(adev); 522 if (r) 523 return r; 524 525 switch (adev->asic_type) { 526 case CHIP_NAVI10: 527 case CHIP_NAVI14: 528 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 529 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 530 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 531 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 532 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 533 !amdgpu_sriov_vf(adev)) 534 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 535 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 536 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 537 #if defined(CONFIG_DRM_AMD_DC) 538 else if (amdgpu_device_has_dc_support(adev)) 539 amdgpu_device_ip_block_add(adev, &dm_ip_block); 540 #endif 541 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 542 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 543 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 544 !amdgpu_sriov_vf(adev)) 545 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 546 if (!nv_is_headless_sku(adev->pdev)) 547 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 548 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 549 if (adev->enable_mes) 550 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 551 break; 552 case CHIP_NAVI12: 553 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 554 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 555 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 556 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 557 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 558 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 559 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 560 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 561 #if defined(CONFIG_DRM_AMD_DC) 562 else if (amdgpu_device_has_dc_support(adev)) 563 amdgpu_device_ip_block_add(adev, &dm_ip_block); 564 #endif 565 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 566 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 567 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 568 !amdgpu_sriov_vf(adev)) 569 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 570 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 571 if (!amdgpu_sriov_vf(adev)) 572 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 573 break; 574 case CHIP_SIENNA_CICHLID: 575 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 576 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 577 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 578 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 579 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 580 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 581 is_support_sw_smu(adev)) 582 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 583 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 584 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 585 #if defined(CONFIG_DRM_AMD_DC) 586 else if (amdgpu_device_has_dc_support(adev)) 587 amdgpu_device_ip_block_add(adev, &dm_ip_block); 588 #endif 589 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 590 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 591 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 592 if (!amdgpu_sriov_vf(adev)) 593 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 594 595 if (adev->enable_mes) 596 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 597 break; 598 case CHIP_NAVY_FLOUNDER: 599 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 600 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 601 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 602 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 603 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 604 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 605 is_support_sw_smu(adev)) 606 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 607 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 608 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 609 #if defined(CONFIG_DRM_AMD_DC) 610 else if (amdgpu_device_has_dc_support(adev)) 611 amdgpu_device_ip_block_add(adev, &dm_ip_block); 612 #endif 613 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 614 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 615 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 616 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 617 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 618 is_support_sw_smu(adev)) 619 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 620 break; 621 case CHIP_VANGOGH: 622 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 623 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 624 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 625 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 626 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 627 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 628 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 629 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 630 #if defined(CONFIG_DRM_AMD_DC) 631 else if (amdgpu_device_has_dc_support(adev)) 632 amdgpu_device_ip_block_add(adev, &dm_ip_block); 633 #endif 634 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 635 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 636 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 637 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 638 break; 639 case CHIP_DIMGREY_CAVEFISH: 640 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 641 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 642 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 643 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 644 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 645 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 646 is_support_sw_smu(adev)) 647 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 648 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 649 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 650 #if defined(CONFIG_DRM_AMD_DC) 651 else if (amdgpu_device_has_dc_support(adev)) 652 amdgpu_device_ip_block_add(adev, &dm_ip_block); 653 #endif 654 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 655 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 656 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 657 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 658 break; 659 default: 660 return -EINVAL; 661 } 662 663 return 0; 664 } 665 666 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 667 { 668 return adev->nbio.funcs->get_rev_id(adev); 669 } 670 671 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 672 { 673 adev->nbio.funcs->hdp_flush(adev, ring); 674 } 675 676 static void nv_invalidate_hdp(struct amdgpu_device *adev, 677 struct amdgpu_ring *ring) 678 { 679 if (!ring || !ring->funcs->emit_wreg) { 680 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 681 } else { 682 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 683 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 684 } 685 } 686 687 static bool nv_need_full_reset(struct amdgpu_device *adev) 688 { 689 return true; 690 } 691 692 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 693 { 694 u32 sol_reg; 695 696 if (adev->flags & AMD_IS_APU) 697 return false; 698 699 /* Check sOS sign of life register to confirm sys driver and sOS 700 * are already been loaded. 701 */ 702 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 703 if (sol_reg) 704 return true; 705 706 return false; 707 } 708 709 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 710 { 711 712 /* TODO 713 * dummy implement for pcie_replay_count sysfs interface 714 * */ 715 716 return 0; 717 } 718 719 static void nv_init_doorbell_index(struct amdgpu_device *adev) 720 { 721 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 722 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 723 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 724 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 725 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 726 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 727 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 728 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 729 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 730 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 731 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 732 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 733 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 734 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 735 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 736 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 737 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 738 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 739 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 740 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 741 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 742 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 743 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 744 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 745 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 746 747 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 748 adev->doorbell_index.sdma_doorbell_range = 20; 749 } 750 751 static void nv_pre_asic_init(struct amdgpu_device *adev) 752 { 753 } 754 755 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 756 bool enter) 757 { 758 if (enter) 759 amdgpu_gfx_rlc_enter_safe_mode(adev); 760 else 761 amdgpu_gfx_rlc_exit_safe_mode(adev); 762 763 if (adev->gfx.funcs->update_perfmon_mgcg) 764 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 765 766 /* 767 * The ASPM function is not fully enabled and verified on 768 * Navi yet. Temporarily skip this until ASPM enabled. 769 */ 770 #if 0 771 if (adev->nbio.funcs->enable_aspm) 772 adev->nbio.funcs->enable_aspm(adev, !enter); 773 #endif 774 775 return 0; 776 } 777 778 static const struct amdgpu_asic_funcs nv_asic_funcs = 779 { 780 .read_disabled_bios = &nv_read_disabled_bios, 781 .read_bios_from_rom = &nv_read_bios_from_rom, 782 .read_register = &nv_read_register, 783 .reset = &nv_asic_reset, 784 .reset_method = &nv_asic_reset_method, 785 .set_vga_state = &nv_vga_set_state, 786 .get_xclk = &nv_get_xclk, 787 .set_uvd_clocks = &nv_set_uvd_clocks, 788 .set_vce_clocks = &nv_set_vce_clocks, 789 .get_config_memsize = &nv_get_config_memsize, 790 .flush_hdp = &nv_flush_hdp, 791 .invalidate_hdp = &nv_invalidate_hdp, 792 .init_doorbell_index = &nv_init_doorbell_index, 793 .need_full_reset = &nv_need_full_reset, 794 .need_reset_on_init = &nv_need_reset_on_init, 795 .get_pcie_replay_count = &nv_get_pcie_replay_count, 796 .supports_baco = &nv_asic_supports_baco, 797 .pre_asic_init = &nv_pre_asic_init, 798 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 799 }; 800 801 static int nv_common_early_init(void *handle) 802 { 803 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 804 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 805 806 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 807 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 808 adev->smc_rreg = NULL; 809 adev->smc_wreg = NULL; 810 adev->pcie_rreg = &nv_pcie_rreg; 811 adev->pcie_wreg = &nv_pcie_wreg; 812 adev->pcie_rreg64 = &nv_pcie_rreg64; 813 adev->pcie_wreg64 = &nv_pcie_wreg64; 814 adev->pciep_rreg = &nv_pcie_port_rreg; 815 adev->pciep_wreg = &nv_pcie_port_wreg; 816 817 /* TODO: will add them during VCN v2 implementation */ 818 adev->uvd_ctx_rreg = NULL; 819 adev->uvd_ctx_wreg = NULL; 820 821 adev->didt_rreg = &nv_didt_rreg; 822 adev->didt_wreg = &nv_didt_wreg; 823 824 adev->asic_funcs = &nv_asic_funcs; 825 826 adev->rev_id = nv_get_rev_id(adev); 827 adev->external_rev_id = 0xff; 828 switch (adev->asic_type) { 829 case CHIP_NAVI10: 830 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 831 AMD_CG_SUPPORT_GFX_CGCG | 832 AMD_CG_SUPPORT_IH_CG | 833 AMD_CG_SUPPORT_HDP_MGCG | 834 AMD_CG_SUPPORT_HDP_LS | 835 AMD_CG_SUPPORT_SDMA_MGCG | 836 AMD_CG_SUPPORT_SDMA_LS | 837 AMD_CG_SUPPORT_MC_MGCG | 838 AMD_CG_SUPPORT_MC_LS | 839 AMD_CG_SUPPORT_ATHUB_MGCG | 840 AMD_CG_SUPPORT_ATHUB_LS | 841 AMD_CG_SUPPORT_VCN_MGCG | 842 AMD_CG_SUPPORT_JPEG_MGCG | 843 AMD_CG_SUPPORT_BIF_MGCG | 844 AMD_CG_SUPPORT_BIF_LS; 845 adev->pg_flags = AMD_PG_SUPPORT_VCN | 846 AMD_PG_SUPPORT_VCN_DPG | 847 AMD_PG_SUPPORT_JPEG | 848 AMD_PG_SUPPORT_ATHUB; 849 adev->external_rev_id = adev->rev_id + 0x1; 850 break; 851 case CHIP_NAVI14: 852 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 853 AMD_CG_SUPPORT_GFX_CGCG | 854 AMD_CG_SUPPORT_IH_CG | 855 AMD_CG_SUPPORT_HDP_MGCG | 856 AMD_CG_SUPPORT_HDP_LS | 857 AMD_CG_SUPPORT_SDMA_MGCG | 858 AMD_CG_SUPPORT_SDMA_LS | 859 AMD_CG_SUPPORT_MC_MGCG | 860 AMD_CG_SUPPORT_MC_LS | 861 AMD_CG_SUPPORT_ATHUB_MGCG | 862 AMD_CG_SUPPORT_ATHUB_LS | 863 AMD_CG_SUPPORT_VCN_MGCG | 864 AMD_CG_SUPPORT_JPEG_MGCG | 865 AMD_CG_SUPPORT_BIF_MGCG | 866 AMD_CG_SUPPORT_BIF_LS; 867 adev->pg_flags = AMD_PG_SUPPORT_VCN | 868 AMD_PG_SUPPORT_JPEG | 869 AMD_PG_SUPPORT_VCN_DPG; 870 adev->external_rev_id = adev->rev_id + 20; 871 break; 872 case CHIP_NAVI12: 873 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 874 AMD_CG_SUPPORT_GFX_MGLS | 875 AMD_CG_SUPPORT_GFX_CGCG | 876 AMD_CG_SUPPORT_GFX_CP_LS | 877 AMD_CG_SUPPORT_GFX_RLC_LS | 878 AMD_CG_SUPPORT_IH_CG | 879 AMD_CG_SUPPORT_HDP_MGCG | 880 AMD_CG_SUPPORT_HDP_LS | 881 AMD_CG_SUPPORT_SDMA_MGCG | 882 AMD_CG_SUPPORT_SDMA_LS | 883 AMD_CG_SUPPORT_MC_MGCG | 884 AMD_CG_SUPPORT_MC_LS | 885 AMD_CG_SUPPORT_ATHUB_MGCG | 886 AMD_CG_SUPPORT_ATHUB_LS | 887 AMD_CG_SUPPORT_VCN_MGCG | 888 AMD_CG_SUPPORT_JPEG_MGCG; 889 adev->pg_flags = AMD_PG_SUPPORT_VCN | 890 AMD_PG_SUPPORT_VCN_DPG | 891 AMD_PG_SUPPORT_JPEG | 892 AMD_PG_SUPPORT_ATHUB; 893 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 894 * as a consequence, the rev_id and external_rev_id are wrong. 895 * workaround it by hardcoding rev_id to 0 (default value). 896 */ 897 if (amdgpu_sriov_vf(adev)) 898 adev->rev_id = 0; 899 adev->external_rev_id = adev->rev_id + 0xa; 900 break; 901 case CHIP_SIENNA_CICHLID: 902 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 903 AMD_CG_SUPPORT_GFX_CGCG | 904 AMD_CG_SUPPORT_GFX_3D_CGCG | 905 AMD_CG_SUPPORT_MC_MGCG | 906 AMD_CG_SUPPORT_VCN_MGCG | 907 AMD_CG_SUPPORT_JPEG_MGCG | 908 AMD_CG_SUPPORT_HDP_MGCG | 909 AMD_CG_SUPPORT_HDP_LS | 910 AMD_CG_SUPPORT_IH_CG | 911 AMD_CG_SUPPORT_MC_LS; 912 adev->pg_flags = AMD_PG_SUPPORT_VCN | 913 AMD_PG_SUPPORT_VCN_DPG | 914 AMD_PG_SUPPORT_JPEG | 915 AMD_PG_SUPPORT_ATHUB | 916 AMD_PG_SUPPORT_MMHUB; 917 if (amdgpu_sriov_vf(adev)) { 918 /* hypervisor control CG and PG enablement */ 919 adev->cg_flags = 0; 920 adev->pg_flags = 0; 921 } 922 adev->external_rev_id = adev->rev_id + 0x28; 923 break; 924 case CHIP_NAVY_FLOUNDER: 925 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 926 AMD_CG_SUPPORT_GFX_CGCG | 927 AMD_CG_SUPPORT_GFX_3D_CGCG | 928 AMD_CG_SUPPORT_VCN_MGCG | 929 AMD_CG_SUPPORT_JPEG_MGCG | 930 AMD_CG_SUPPORT_MC_MGCG | 931 AMD_CG_SUPPORT_MC_LS | 932 AMD_CG_SUPPORT_HDP_MGCG | 933 AMD_CG_SUPPORT_HDP_LS | 934 AMD_CG_SUPPORT_IH_CG; 935 adev->pg_flags = AMD_PG_SUPPORT_VCN | 936 AMD_PG_SUPPORT_VCN_DPG | 937 AMD_PG_SUPPORT_JPEG | 938 AMD_PG_SUPPORT_ATHUB | 939 AMD_PG_SUPPORT_MMHUB; 940 adev->external_rev_id = adev->rev_id + 0x32; 941 break; 942 943 case CHIP_VANGOGH: 944 adev->apu_flags |= AMD_APU_IS_VANGOGH; 945 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 946 AMD_CG_SUPPORT_GFX_MGLS | 947 AMD_CG_SUPPORT_GFX_CP_LS | 948 AMD_CG_SUPPORT_GFX_RLC_LS | 949 AMD_CG_SUPPORT_GFX_CGCG | 950 AMD_CG_SUPPORT_GFX_CGLS | 951 AMD_CG_SUPPORT_GFX_3D_CGCG | 952 AMD_CG_SUPPORT_GFX_3D_CGLS | 953 AMD_CG_SUPPORT_MC_MGCG | 954 AMD_CG_SUPPORT_MC_LS | 955 AMD_CG_SUPPORT_GFX_FGCG | 956 AMD_CG_SUPPORT_VCN_MGCG | 957 AMD_CG_SUPPORT_JPEG_MGCG; 958 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 959 AMD_PG_SUPPORT_VCN | 960 AMD_PG_SUPPORT_VCN_DPG | 961 AMD_PG_SUPPORT_JPEG; 962 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 963 adev->external_rev_id = adev->rev_id + 0x01; 964 break; 965 case CHIP_DIMGREY_CAVEFISH: 966 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 967 AMD_CG_SUPPORT_GFX_CGCG | 968 AMD_CG_SUPPORT_GFX_3D_CGCG | 969 AMD_CG_SUPPORT_VCN_MGCG | 970 AMD_CG_SUPPORT_JPEG_MGCG | 971 AMD_CG_SUPPORT_MC_MGCG | 972 AMD_CG_SUPPORT_MC_LS | 973 AMD_CG_SUPPORT_HDP_MGCG | 974 AMD_CG_SUPPORT_HDP_LS | 975 AMD_CG_SUPPORT_IH_CG; 976 adev->pg_flags = AMD_PG_SUPPORT_VCN | 977 AMD_PG_SUPPORT_VCN_DPG | 978 AMD_PG_SUPPORT_JPEG | 979 AMD_PG_SUPPORT_ATHUB | 980 AMD_PG_SUPPORT_MMHUB; 981 adev->external_rev_id = adev->rev_id + 0x3c; 982 break; 983 default: 984 /* FIXME: not supported yet */ 985 return -EINVAL; 986 } 987 988 if (amdgpu_sriov_vf(adev)) { 989 amdgpu_virt_init_setting(adev); 990 xgpu_nv_mailbox_set_irq_funcs(adev); 991 } 992 993 return 0; 994 } 995 996 static int nv_common_late_init(void *handle) 997 { 998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 999 1000 if (amdgpu_sriov_vf(adev)) 1001 xgpu_nv_mailbox_get_irq(adev); 1002 1003 return 0; 1004 } 1005 1006 static int nv_common_sw_init(void *handle) 1007 { 1008 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1009 1010 if (amdgpu_sriov_vf(adev)) 1011 xgpu_nv_mailbox_add_irq_id(adev); 1012 1013 return 0; 1014 } 1015 1016 static int nv_common_sw_fini(void *handle) 1017 { 1018 return 0; 1019 } 1020 1021 static int nv_common_hw_init(void *handle) 1022 { 1023 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1024 1025 /* enable pcie gen2/3 link */ 1026 nv_pcie_gen3_enable(adev); 1027 /* enable aspm */ 1028 nv_program_aspm(adev); 1029 /* setup nbio registers */ 1030 adev->nbio.funcs->init_registers(adev); 1031 /* remap HDP registers to a hole in mmio space, 1032 * for the purpose of expose those registers 1033 * to process space 1034 */ 1035 if (adev->nbio.funcs->remap_hdp_registers) 1036 adev->nbio.funcs->remap_hdp_registers(adev); 1037 /* enable the doorbell aperture */ 1038 nv_enable_doorbell_aperture(adev, true); 1039 1040 return 0; 1041 } 1042 1043 static int nv_common_hw_fini(void *handle) 1044 { 1045 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1046 1047 /* disable the doorbell aperture */ 1048 nv_enable_doorbell_aperture(adev, false); 1049 1050 return 0; 1051 } 1052 1053 static int nv_common_suspend(void *handle) 1054 { 1055 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1056 1057 return nv_common_hw_fini(adev); 1058 } 1059 1060 static int nv_common_resume(void *handle) 1061 { 1062 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1063 1064 return nv_common_hw_init(adev); 1065 } 1066 1067 static bool nv_common_is_idle(void *handle) 1068 { 1069 return true; 1070 } 1071 1072 static int nv_common_wait_for_idle(void *handle) 1073 { 1074 return 0; 1075 } 1076 1077 static int nv_common_soft_reset(void *handle) 1078 { 1079 return 0; 1080 } 1081 1082 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 1083 bool enable) 1084 { 1085 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 1086 uint32_t hdp_mem_pwr_cntl; 1087 1088 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 1089 AMD_CG_SUPPORT_HDP_DS | 1090 AMD_CG_SUPPORT_HDP_SD))) 1091 return; 1092 1093 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1094 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1095 1096 /* Before doing clock/power mode switch, 1097 * forced on IPH & RC clock */ 1098 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 1099 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 1100 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 1101 RC_MEM_CLK_SOFT_OVERRIDE, 1); 1102 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1103 1104 /* HDP 5.0 doesn't support dynamic power mode switch, 1105 * disable clock and power gating before any changing */ 1106 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1107 IPH_MEM_POWER_CTRL_EN, 0); 1108 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1109 IPH_MEM_POWER_LS_EN, 0); 1110 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1111 IPH_MEM_POWER_DS_EN, 0); 1112 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1113 IPH_MEM_POWER_SD_EN, 0); 1114 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1115 RC_MEM_POWER_CTRL_EN, 0); 1116 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1117 RC_MEM_POWER_LS_EN, 0); 1118 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1119 RC_MEM_POWER_DS_EN, 0); 1120 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1121 RC_MEM_POWER_SD_EN, 0); 1122 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1123 1124 /* only one clock gating mode (LS/DS/SD) can be enabled */ 1125 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1126 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1127 HDP_MEM_POWER_CTRL, 1128 IPH_MEM_POWER_LS_EN, enable); 1129 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1130 HDP_MEM_POWER_CTRL, 1131 RC_MEM_POWER_LS_EN, enable); 1132 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 1133 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1134 HDP_MEM_POWER_CTRL, 1135 IPH_MEM_POWER_DS_EN, enable); 1136 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1137 HDP_MEM_POWER_CTRL, 1138 RC_MEM_POWER_DS_EN, enable); 1139 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 1140 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1141 HDP_MEM_POWER_CTRL, 1142 IPH_MEM_POWER_SD_EN, enable); 1143 /* RC should not use shut down mode, fallback to ds */ 1144 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1145 HDP_MEM_POWER_CTRL, 1146 RC_MEM_POWER_DS_EN, enable); 1147 } 1148 1149 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 1150 * be set for SRAM LS/DS/SD */ 1151 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 1152 AMD_CG_SUPPORT_HDP_SD)) { 1153 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1154 IPH_MEM_POWER_CTRL_EN, 1); 1155 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1156 RC_MEM_POWER_CTRL_EN, 1); 1157 } 1158 1159 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1160 1161 /* restore IPH & RC clock override after clock/power mode changing */ 1162 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 1163 } 1164 1165 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 1166 bool enable) 1167 { 1168 uint32_t hdp_clk_cntl; 1169 1170 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1171 return; 1172 1173 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1174 1175 if (enable) { 1176 hdp_clk_cntl &= 1177 ~(uint32_t) 1178 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1179 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1180 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1181 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1182 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1183 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 1184 } else { 1185 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1186 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1187 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1188 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1189 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1190 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 1191 } 1192 1193 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1194 } 1195 1196 static int nv_common_set_clockgating_state(void *handle, 1197 enum amd_clockgating_state state) 1198 { 1199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1200 1201 if (amdgpu_sriov_vf(adev)) 1202 return 0; 1203 1204 switch (adev->asic_type) { 1205 case CHIP_NAVI10: 1206 case CHIP_NAVI14: 1207 case CHIP_NAVI12: 1208 case CHIP_SIENNA_CICHLID: 1209 case CHIP_NAVY_FLOUNDER: 1210 case CHIP_DIMGREY_CAVEFISH: 1211 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1212 state == AMD_CG_STATE_GATE); 1213 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1214 state == AMD_CG_STATE_GATE); 1215 nv_update_hdp_mem_power_gating(adev, 1216 state == AMD_CG_STATE_GATE); 1217 nv_update_hdp_clock_gating(adev, 1218 state == AMD_CG_STATE_GATE); 1219 break; 1220 default: 1221 break; 1222 } 1223 return 0; 1224 } 1225 1226 static int nv_common_set_powergating_state(void *handle, 1227 enum amd_powergating_state state) 1228 { 1229 /* TODO */ 1230 return 0; 1231 } 1232 1233 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1234 { 1235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1236 uint32_t tmp; 1237 1238 if (amdgpu_sriov_vf(adev)) 1239 *flags = 0; 1240 1241 adev->nbio.funcs->get_clockgating_state(adev, flags); 1242 1243 /* AMD_CG_SUPPORT_HDP_MGCG */ 1244 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1245 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1246 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1247 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1248 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1249 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1250 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 1251 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1252 1253 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 1254 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1255 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 1256 *flags |= AMD_CG_SUPPORT_HDP_LS; 1257 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1258 *flags |= AMD_CG_SUPPORT_HDP_DS; 1259 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1260 *flags |= AMD_CG_SUPPORT_HDP_SD; 1261 1262 return; 1263 } 1264 1265 static const struct amd_ip_funcs nv_common_ip_funcs = { 1266 .name = "nv_common", 1267 .early_init = nv_common_early_init, 1268 .late_init = nv_common_late_init, 1269 .sw_init = nv_common_sw_init, 1270 .sw_fini = nv_common_sw_fini, 1271 .hw_init = nv_common_hw_init, 1272 .hw_fini = nv_common_hw_fini, 1273 .suspend = nv_common_suspend, 1274 .resume = nv_common_resume, 1275 .is_idle = nv_common_is_idle, 1276 .wait_for_idle = nv_common_wait_for_idle, 1277 .soft_reset = nv_common_soft_reset, 1278 .set_clockgating_state = nv_common_set_clockgating_state, 1279 .set_powergating_state = nv_common_set_powergating_state, 1280 .get_clockgating_state = nv_common_get_clockgating_state, 1281 }; 1282