1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 74 }; 75 76 static const struct amdgpu_video_codecs nv_video_codecs_encode = 77 { 78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 79 .codec_array = nv_video_codecs_encode_array, 80 }; 81 82 /* Navi1x */ 83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 92 }; 93 94 static const struct amdgpu_video_codecs nv_video_codecs_decode = 95 { 96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 97 .codec_array = nv_video_codecs_decode_array, 98 }; 99 100 /* Sienna Cichlid */ 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = 102 { 103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 104 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 111 }; 112 113 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = 114 { 115 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 116 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 117 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 118 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 119 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 122 }; 123 124 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = 125 { 126 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0), 127 .codec_array = sc_video_codecs_decode_array_vcn0, 128 }; 129 130 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = 131 { 132 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1), 133 .codec_array = sc_video_codecs_decode_array_vcn1, 134 }; 135 136 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 137 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 138 { 139 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 141 }; 142 143 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = 144 { 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 148 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 149 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 150 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 151 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 153 }; 154 155 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = 156 { 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 162 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 163 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 164 }; 165 166 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 167 { 168 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 169 .codec_array = sriov_sc_video_codecs_encode_array, 170 }; 171 172 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = 173 { 174 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0), 175 .codec_array = sriov_sc_video_codecs_decode_array_vcn0, 176 }; 177 178 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = 179 { 180 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1), 181 .codec_array = sriov_sc_video_codecs_decode_array_vcn1, 182 }; 183 184 /* Beige Goby*/ 185 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 186 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 187 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 188 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 189 }; 190 191 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 192 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 193 .codec_array = bg_video_codecs_decode_array, 194 }; 195 196 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 197 .codec_count = 0, 198 .codec_array = NULL, 199 }; 200 201 /* Yellow Carp*/ 202 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 203 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 204 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 205 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 206 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 207 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 208 }; 209 210 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 211 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 212 .codec_array = yc_video_codecs_decode_array, 213 }; 214 215 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 216 const struct amdgpu_video_codecs **codecs) 217 { 218 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 219 return -EINVAL; 220 221 switch (adev->ip_versions[UVD_HWIP][0]) { 222 case IP_VERSION(3, 0, 0): 223 case IP_VERSION(3, 0, 64): 224 case IP_VERSION(3, 0, 192): 225 if (amdgpu_sriov_vf(adev)) { 226 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 227 if (encode) 228 *codecs = &sriov_sc_video_codecs_encode; 229 else 230 *codecs = &sriov_sc_video_codecs_decode_vcn1; 231 } else { 232 if (encode) 233 *codecs = &sriov_sc_video_codecs_encode; 234 else 235 *codecs = &sriov_sc_video_codecs_decode_vcn0; 236 } 237 } else { 238 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 239 if (encode) 240 *codecs = &nv_video_codecs_encode; 241 else 242 *codecs = &sc_video_codecs_decode_vcn1; 243 } else { 244 if (encode) 245 *codecs = &nv_video_codecs_encode; 246 else 247 *codecs = &sc_video_codecs_decode_vcn0; 248 } 249 } 250 return 0; 251 case IP_VERSION(3, 0, 16): 252 case IP_VERSION(3, 0, 2): 253 if (encode) 254 *codecs = &nv_video_codecs_encode; 255 else 256 *codecs = &sc_video_codecs_decode_vcn0; 257 return 0; 258 case IP_VERSION(3, 1, 1): 259 case IP_VERSION(3, 1, 2): 260 if (encode) 261 *codecs = &nv_video_codecs_encode; 262 else 263 *codecs = &yc_video_codecs_decode; 264 return 0; 265 case IP_VERSION(3, 0, 33): 266 if (encode) 267 *codecs = &bg_video_codecs_encode; 268 else 269 *codecs = &bg_video_codecs_decode; 270 return 0; 271 case IP_VERSION(2, 0, 0): 272 case IP_VERSION(2, 0, 2): 273 if (encode) 274 *codecs = &nv_video_codecs_encode; 275 else 276 *codecs = &nv_video_codecs_decode; 277 return 0; 278 default: 279 return -EINVAL; 280 } 281 } 282 283 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 284 { 285 unsigned long flags, address, data; 286 u32 r; 287 288 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 289 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 290 291 spin_lock_irqsave(&adev->didt_idx_lock, flags); 292 WREG32(address, (reg)); 293 r = RREG32(data); 294 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 295 return r; 296 } 297 298 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 299 { 300 unsigned long flags, address, data; 301 302 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 303 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 304 305 spin_lock_irqsave(&adev->didt_idx_lock, flags); 306 WREG32(address, (reg)); 307 WREG32(data, (v)); 308 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 309 } 310 311 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 312 { 313 return adev->nbio.funcs->get_memsize(adev); 314 } 315 316 static u32 nv_get_xclk(struct amdgpu_device *adev) 317 { 318 return adev->clock.spll.reference_freq; 319 } 320 321 322 void nv_grbm_select(struct amdgpu_device *adev, 323 u32 me, u32 pipe, u32 queue, u32 vmid) 324 { 325 u32 grbm_gfx_cntl = 0; 326 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 327 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 328 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 329 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 330 331 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 332 } 333 334 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 335 { 336 /* todo */ 337 } 338 339 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 340 { 341 /* todo */ 342 return false; 343 } 344 345 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 346 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 347 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 348 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 349 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 350 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 351 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 352 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 353 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 354 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 355 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 356 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 357 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 358 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 359 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 360 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 361 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 362 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 363 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 364 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 365 }; 366 367 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 368 u32 sh_num, u32 reg_offset) 369 { 370 uint32_t val; 371 372 mutex_lock(&adev->grbm_idx_mutex); 373 if (se_num != 0xffffffff || sh_num != 0xffffffff) 374 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 375 376 val = RREG32(reg_offset); 377 378 if (se_num != 0xffffffff || sh_num != 0xffffffff) 379 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 380 mutex_unlock(&adev->grbm_idx_mutex); 381 return val; 382 } 383 384 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 385 bool indexed, u32 se_num, 386 u32 sh_num, u32 reg_offset) 387 { 388 if (indexed) { 389 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 390 } else { 391 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 392 return adev->gfx.config.gb_addr_config; 393 return RREG32(reg_offset); 394 } 395 } 396 397 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 398 u32 sh_num, u32 reg_offset, u32 *value) 399 { 400 uint32_t i; 401 struct soc15_allowed_register_entry *en; 402 403 *value = 0; 404 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 405 en = &nv_allowed_read_registers[i]; 406 if (!adev->reg_offset[en->hwip][en->inst]) 407 continue; 408 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 409 + en->reg_offset)) 410 continue; 411 412 *value = nv_get_register_value(adev, 413 nv_allowed_read_registers[i].grbm_indexed, 414 se_num, sh_num, reg_offset); 415 return 0; 416 } 417 return -EINVAL; 418 } 419 420 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 421 { 422 u32 i; 423 int ret = 0; 424 425 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 426 427 /* disable BM */ 428 pci_clear_master(adev->pdev); 429 430 amdgpu_device_cache_pci_state(adev->pdev); 431 432 ret = amdgpu_dpm_mode2_reset(adev); 433 if (ret) 434 dev_err(adev->dev, "GPU mode2 reset failed\n"); 435 436 amdgpu_device_load_pci_state(adev->pdev); 437 438 /* wait for asic to come out of reset */ 439 for (i = 0; i < adev->usec_timeout; i++) { 440 u32 memsize = adev->nbio.funcs->get_memsize(adev); 441 442 if (memsize != 0xffffffff) 443 break; 444 udelay(1); 445 } 446 447 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 448 449 return ret; 450 } 451 452 static enum amd_reset_method 453 nv_asic_reset_method(struct amdgpu_device *adev) 454 { 455 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 456 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 457 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 458 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 459 return amdgpu_reset_method; 460 461 if (amdgpu_reset_method != -1) 462 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 463 amdgpu_reset_method); 464 465 switch (adev->ip_versions[MP1_HWIP][0]) { 466 case IP_VERSION(11, 5, 0): 467 case IP_VERSION(13, 0, 1): 468 case IP_VERSION(13, 0, 3): 469 case IP_VERSION(13, 0, 5): 470 case IP_VERSION(13, 0, 8): 471 return AMD_RESET_METHOD_MODE2; 472 case IP_VERSION(11, 0, 7): 473 case IP_VERSION(11, 0, 11): 474 case IP_VERSION(11, 0, 12): 475 case IP_VERSION(11, 0, 13): 476 return AMD_RESET_METHOD_MODE1; 477 default: 478 if (amdgpu_dpm_is_baco_supported(adev)) 479 return AMD_RESET_METHOD_BACO; 480 else 481 return AMD_RESET_METHOD_MODE1; 482 } 483 } 484 485 static int nv_asic_reset(struct amdgpu_device *adev) 486 { 487 int ret = 0; 488 489 switch (nv_asic_reset_method(adev)) { 490 case AMD_RESET_METHOD_PCI: 491 dev_info(adev->dev, "PCI reset\n"); 492 ret = amdgpu_device_pci_reset(adev); 493 break; 494 case AMD_RESET_METHOD_BACO: 495 dev_info(adev->dev, "BACO reset\n"); 496 ret = amdgpu_dpm_baco_reset(adev); 497 break; 498 case AMD_RESET_METHOD_MODE2: 499 dev_info(adev->dev, "MODE2 reset\n"); 500 ret = nv_asic_mode2_reset(adev); 501 break; 502 default: 503 dev_info(adev->dev, "MODE1 reset\n"); 504 ret = amdgpu_device_mode1_reset(adev); 505 break; 506 } 507 508 return ret; 509 } 510 511 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 512 { 513 /* todo */ 514 return 0; 515 } 516 517 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 518 { 519 /* todo */ 520 return 0; 521 } 522 523 static void nv_program_aspm(struct amdgpu_device *adev) 524 { 525 if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_aspm_support_quirk()) 526 return; 527 528 if (!(adev->flags & AMD_IS_APU) && 529 (adev->nbio.funcs->program_aspm)) 530 adev->nbio.funcs->program_aspm(adev); 531 532 } 533 534 const struct amdgpu_ip_block_version nv_common_ip_block = 535 { 536 .type = AMD_IP_BLOCK_TYPE_COMMON, 537 .major = 1, 538 .minor = 0, 539 .rev = 0, 540 .funcs = &nv_common_ip_funcs, 541 }; 542 543 void nv_set_virt_ops(struct amdgpu_device *adev) 544 { 545 adev->virt.ops = &xgpu_nv_virt_ops; 546 } 547 548 static bool nv_need_full_reset(struct amdgpu_device *adev) 549 { 550 return true; 551 } 552 553 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 554 { 555 u32 sol_reg; 556 557 if (adev->flags & AMD_IS_APU) 558 return false; 559 560 /* Check sOS sign of life register to confirm sys driver and sOS 561 * are already been loaded. 562 */ 563 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 564 if (sol_reg) 565 return true; 566 567 return false; 568 } 569 570 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 571 { 572 573 /* TODO 574 * dummy implement for pcie_replay_count sysfs interface 575 * */ 576 577 return 0; 578 } 579 580 static void nv_init_doorbell_index(struct amdgpu_device *adev) 581 { 582 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 583 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 584 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 585 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 586 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 587 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 588 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 589 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 590 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 591 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 592 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 593 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 594 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 595 adev->doorbell_index.gfx_userqueue_start = 596 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 597 adev->doorbell_index.gfx_userqueue_end = 598 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 599 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 600 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 601 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 602 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 603 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 604 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 605 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 606 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 607 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 608 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 609 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 610 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 611 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 612 613 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 614 adev->doorbell_index.sdma_doorbell_range = 20; 615 } 616 617 static void nv_pre_asic_init(struct amdgpu_device *adev) 618 { 619 } 620 621 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 622 bool enter) 623 { 624 if (enter) 625 amdgpu_gfx_rlc_enter_safe_mode(adev); 626 else 627 amdgpu_gfx_rlc_exit_safe_mode(adev); 628 629 if (adev->gfx.funcs->update_perfmon_mgcg) 630 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 631 632 if (!(adev->flags & AMD_IS_APU) && 633 (adev->nbio.funcs->enable_aspm) && 634 amdgpu_device_should_use_aspm(adev)) 635 adev->nbio.funcs->enable_aspm(adev, !enter); 636 637 return 0; 638 } 639 640 static const struct amdgpu_asic_funcs nv_asic_funcs = 641 { 642 .read_disabled_bios = &nv_read_disabled_bios, 643 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 644 .read_register = &nv_read_register, 645 .reset = &nv_asic_reset, 646 .reset_method = &nv_asic_reset_method, 647 .set_vga_state = &nv_vga_set_state, 648 .get_xclk = &nv_get_xclk, 649 .set_uvd_clocks = &nv_set_uvd_clocks, 650 .set_vce_clocks = &nv_set_vce_clocks, 651 .get_config_memsize = &nv_get_config_memsize, 652 .init_doorbell_index = &nv_init_doorbell_index, 653 .need_full_reset = &nv_need_full_reset, 654 .need_reset_on_init = &nv_need_reset_on_init, 655 .get_pcie_replay_count = &nv_get_pcie_replay_count, 656 .supports_baco = &amdgpu_dpm_is_baco_supported, 657 .pre_asic_init = &nv_pre_asic_init, 658 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 659 .query_video_codecs = &nv_query_video_codecs, 660 }; 661 662 static int nv_common_early_init(void *handle) 663 { 664 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 665 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 666 667 if (!amdgpu_sriov_vf(adev)) { 668 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 669 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 670 } 671 adev->smc_rreg = NULL; 672 adev->smc_wreg = NULL; 673 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 674 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 675 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 676 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 677 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 678 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 679 680 /* TODO: will add them during VCN v2 implementation */ 681 adev->uvd_ctx_rreg = NULL; 682 adev->uvd_ctx_wreg = NULL; 683 684 adev->didt_rreg = &nv_didt_rreg; 685 adev->didt_wreg = &nv_didt_wreg; 686 687 adev->asic_funcs = &nv_asic_funcs; 688 689 adev->rev_id = amdgpu_device_get_rev_id(adev); 690 adev->external_rev_id = 0xff; 691 /* TODO: split the GC and PG flags based on the relevant IP version for which 692 * they are relevant. 693 */ 694 switch (adev->ip_versions[GC_HWIP][0]) { 695 case IP_VERSION(10, 1, 10): 696 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 697 AMD_CG_SUPPORT_GFX_CGCG | 698 AMD_CG_SUPPORT_IH_CG | 699 AMD_CG_SUPPORT_HDP_MGCG | 700 AMD_CG_SUPPORT_HDP_LS | 701 AMD_CG_SUPPORT_SDMA_MGCG | 702 AMD_CG_SUPPORT_SDMA_LS | 703 AMD_CG_SUPPORT_MC_MGCG | 704 AMD_CG_SUPPORT_MC_LS | 705 AMD_CG_SUPPORT_ATHUB_MGCG | 706 AMD_CG_SUPPORT_ATHUB_LS | 707 AMD_CG_SUPPORT_VCN_MGCG | 708 AMD_CG_SUPPORT_JPEG_MGCG | 709 AMD_CG_SUPPORT_BIF_MGCG | 710 AMD_CG_SUPPORT_BIF_LS; 711 adev->pg_flags = AMD_PG_SUPPORT_VCN | 712 AMD_PG_SUPPORT_VCN_DPG | 713 AMD_PG_SUPPORT_JPEG | 714 AMD_PG_SUPPORT_ATHUB; 715 adev->external_rev_id = adev->rev_id + 0x1; 716 break; 717 case IP_VERSION(10, 1, 1): 718 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 719 AMD_CG_SUPPORT_GFX_CGCG | 720 AMD_CG_SUPPORT_IH_CG | 721 AMD_CG_SUPPORT_HDP_MGCG | 722 AMD_CG_SUPPORT_HDP_LS | 723 AMD_CG_SUPPORT_SDMA_MGCG | 724 AMD_CG_SUPPORT_SDMA_LS | 725 AMD_CG_SUPPORT_MC_MGCG | 726 AMD_CG_SUPPORT_MC_LS | 727 AMD_CG_SUPPORT_ATHUB_MGCG | 728 AMD_CG_SUPPORT_ATHUB_LS | 729 AMD_CG_SUPPORT_VCN_MGCG | 730 AMD_CG_SUPPORT_JPEG_MGCG | 731 AMD_CG_SUPPORT_BIF_MGCG | 732 AMD_CG_SUPPORT_BIF_LS; 733 adev->pg_flags = AMD_PG_SUPPORT_VCN | 734 AMD_PG_SUPPORT_JPEG | 735 AMD_PG_SUPPORT_VCN_DPG; 736 adev->external_rev_id = adev->rev_id + 20; 737 break; 738 case IP_VERSION(10, 1, 2): 739 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 740 AMD_CG_SUPPORT_GFX_MGLS | 741 AMD_CG_SUPPORT_GFX_CGCG | 742 AMD_CG_SUPPORT_GFX_CP_LS | 743 AMD_CG_SUPPORT_GFX_RLC_LS | 744 AMD_CG_SUPPORT_IH_CG | 745 AMD_CG_SUPPORT_HDP_MGCG | 746 AMD_CG_SUPPORT_HDP_LS | 747 AMD_CG_SUPPORT_SDMA_MGCG | 748 AMD_CG_SUPPORT_SDMA_LS | 749 AMD_CG_SUPPORT_MC_MGCG | 750 AMD_CG_SUPPORT_MC_LS | 751 AMD_CG_SUPPORT_ATHUB_MGCG | 752 AMD_CG_SUPPORT_ATHUB_LS | 753 AMD_CG_SUPPORT_VCN_MGCG | 754 AMD_CG_SUPPORT_JPEG_MGCG; 755 adev->pg_flags = AMD_PG_SUPPORT_VCN | 756 AMD_PG_SUPPORT_VCN_DPG | 757 AMD_PG_SUPPORT_JPEG | 758 AMD_PG_SUPPORT_ATHUB; 759 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 760 * as a consequence, the rev_id and external_rev_id are wrong. 761 * workaround it by hardcoding rev_id to 0 (default value). 762 */ 763 if (amdgpu_sriov_vf(adev)) 764 adev->rev_id = 0; 765 adev->external_rev_id = adev->rev_id + 0xa; 766 break; 767 case IP_VERSION(10, 3, 0): 768 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 769 AMD_CG_SUPPORT_GFX_CGCG | 770 AMD_CG_SUPPORT_GFX_CGLS | 771 AMD_CG_SUPPORT_GFX_3D_CGCG | 772 AMD_CG_SUPPORT_MC_MGCG | 773 AMD_CG_SUPPORT_VCN_MGCG | 774 AMD_CG_SUPPORT_JPEG_MGCG | 775 AMD_CG_SUPPORT_HDP_MGCG | 776 AMD_CG_SUPPORT_HDP_LS | 777 AMD_CG_SUPPORT_IH_CG | 778 AMD_CG_SUPPORT_MC_LS; 779 adev->pg_flags = AMD_PG_SUPPORT_VCN | 780 AMD_PG_SUPPORT_VCN_DPG | 781 AMD_PG_SUPPORT_JPEG | 782 AMD_PG_SUPPORT_ATHUB | 783 AMD_PG_SUPPORT_MMHUB; 784 if (amdgpu_sriov_vf(adev)) { 785 /* hypervisor control CG and PG enablement */ 786 adev->cg_flags = 0; 787 adev->pg_flags = 0; 788 } 789 adev->external_rev_id = adev->rev_id + 0x28; 790 break; 791 case IP_VERSION(10, 3, 2): 792 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 793 AMD_CG_SUPPORT_GFX_CGCG | 794 AMD_CG_SUPPORT_GFX_CGLS | 795 AMD_CG_SUPPORT_GFX_3D_CGCG | 796 AMD_CG_SUPPORT_VCN_MGCG | 797 AMD_CG_SUPPORT_JPEG_MGCG | 798 AMD_CG_SUPPORT_MC_MGCG | 799 AMD_CG_SUPPORT_MC_LS | 800 AMD_CG_SUPPORT_HDP_MGCG | 801 AMD_CG_SUPPORT_HDP_LS | 802 AMD_CG_SUPPORT_IH_CG; 803 adev->pg_flags = AMD_PG_SUPPORT_VCN | 804 AMD_PG_SUPPORT_VCN_DPG | 805 AMD_PG_SUPPORT_JPEG | 806 AMD_PG_SUPPORT_ATHUB | 807 AMD_PG_SUPPORT_MMHUB; 808 adev->external_rev_id = adev->rev_id + 0x32; 809 break; 810 case IP_VERSION(10, 3, 1): 811 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 812 AMD_CG_SUPPORT_GFX_MGLS | 813 AMD_CG_SUPPORT_GFX_CP_LS | 814 AMD_CG_SUPPORT_GFX_RLC_LS | 815 AMD_CG_SUPPORT_GFX_CGCG | 816 AMD_CG_SUPPORT_GFX_CGLS | 817 AMD_CG_SUPPORT_GFX_3D_CGCG | 818 AMD_CG_SUPPORT_GFX_3D_CGLS | 819 AMD_CG_SUPPORT_MC_MGCG | 820 AMD_CG_SUPPORT_MC_LS | 821 AMD_CG_SUPPORT_GFX_FGCG | 822 AMD_CG_SUPPORT_VCN_MGCG | 823 AMD_CG_SUPPORT_SDMA_MGCG | 824 AMD_CG_SUPPORT_SDMA_LS | 825 AMD_CG_SUPPORT_JPEG_MGCG; 826 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 827 AMD_PG_SUPPORT_VCN | 828 AMD_PG_SUPPORT_VCN_DPG | 829 AMD_PG_SUPPORT_JPEG; 830 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 831 adev->external_rev_id = adev->rev_id + 0x01; 832 break; 833 case IP_VERSION(10, 3, 4): 834 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 835 AMD_CG_SUPPORT_GFX_CGCG | 836 AMD_CG_SUPPORT_GFX_CGLS | 837 AMD_CG_SUPPORT_GFX_3D_CGCG | 838 AMD_CG_SUPPORT_VCN_MGCG | 839 AMD_CG_SUPPORT_JPEG_MGCG | 840 AMD_CG_SUPPORT_MC_MGCG | 841 AMD_CG_SUPPORT_MC_LS | 842 AMD_CG_SUPPORT_HDP_MGCG | 843 AMD_CG_SUPPORT_HDP_LS | 844 AMD_CG_SUPPORT_IH_CG; 845 adev->pg_flags = AMD_PG_SUPPORT_VCN | 846 AMD_PG_SUPPORT_VCN_DPG | 847 AMD_PG_SUPPORT_JPEG | 848 AMD_PG_SUPPORT_ATHUB | 849 AMD_PG_SUPPORT_MMHUB; 850 adev->external_rev_id = adev->rev_id + 0x3c; 851 break; 852 case IP_VERSION(10, 3, 5): 853 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 854 AMD_CG_SUPPORT_GFX_CGCG | 855 AMD_CG_SUPPORT_GFX_CGLS | 856 AMD_CG_SUPPORT_GFX_3D_CGCG | 857 AMD_CG_SUPPORT_MC_MGCG | 858 AMD_CG_SUPPORT_MC_LS | 859 AMD_CG_SUPPORT_HDP_MGCG | 860 AMD_CG_SUPPORT_HDP_LS | 861 AMD_CG_SUPPORT_IH_CG | 862 AMD_CG_SUPPORT_VCN_MGCG; 863 adev->pg_flags = AMD_PG_SUPPORT_VCN | 864 AMD_PG_SUPPORT_VCN_DPG | 865 AMD_PG_SUPPORT_ATHUB | 866 AMD_PG_SUPPORT_MMHUB; 867 adev->external_rev_id = adev->rev_id + 0x46; 868 break; 869 case IP_VERSION(10, 3, 3): 870 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 871 AMD_CG_SUPPORT_GFX_MGLS | 872 AMD_CG_SUPPORT_GFX_CGCG | 873 AMD_CG_SUPPORT_GFX_CGLS | 874 AMD_CG_SUPPORT_GFX_3D_CGCG | 875 AMD_CG_SUPPORT_GFX_3D_CGLS | 876 AMD_CG_SUPPORT_GFX_RLC_LS | 877 AMD_CG_SUPPORT_GFX_CP_LS | 878 AMD_CG_SUPPORT_GFX_FGCG | 879 AMD_CG_SUPPORT_MC_MGCG | 880 AMD_CG_SUPPORT_MC_LS | 881 AMD_CG_SUPPORT_SDMA_LS | 882 AMD_CG_SUPPORT_HDP_MGCG | 883 AMD_CG_SUPPORT_HDP_LS | 884 AMD_CG_SUPPORT_ATHUB_MGCG | 885 AMD_CG_SUPPORT_ATHUB_LS | 886 AMD_CG_SUPPORT_IH_CG | 887 AMD_CG_SUPPORT_VCN_MGCG | 888 AMD_CG_SUPPORT_JPEG_MGCG; 889 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 890 AMD_PG_SUPPORT_VCN | 891 AMD_PG_SUPPORT_VCN_DPG | 892 AMD_PG_SUPPORT_JPEG; 893 if (adev->pdev->device == 0x1681) 894 adev->external_rev_id = 0x20; 895 else 896 adev->external_rev_id = adev->rev_id + 0x01; 897 break; 898 case IP_VERSION(10, 1, 3): 899 case IP_VERSION(10, 1, 4): 900 adev->cg_flags = 0; 901 adev->pg_flags = 0; 902 adev->external_rev_id = adev->rev_id + 0x82; 903 break; 904 case IP_VERSION(10, 3, 6): 905 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 906 AMD_CG_SUPPORT_GFX_MGLS | 907 AMD_CG_SUPPORT_GFX_CGCG | 908 AMD_CG_SUPPORT_GFX_CGLS | 909 AMD_CG_SUPPORT_GFX_3D_CGCG | 910 AMD_CG_SUPPORT_GFX_3D_CGLS | 911 AMD_CG_SUPPORT_GFX_RLC_LS | 912 AMD_CG_SUPPORT_GFX_CP_LS | 913 AMD_CG_SUPPORT_GFX_FGCG | 914 AMD_CG_SUPPORT_MC_MGCG | 915 AMD_CG_SUPPORT_MC_LS | 916 AMD_CG_SUPPORT_SDMA_LS | 917 AMD_CG_SUPPORT_HDP_MGCG | 918 AMD_CG_SUPPORT_HDP_LS | 919 AMD_CG_SUPPORT_ATHUB_MGCG | 920 AMD_CG_SUPPORT_ATHUB_LS | 921 AMD_CG_SUPPORT_IH_CG | 922 AMD_CG_SUPPORT_VCN_MGCG | 923 AMD_CG_SUPPORT_JPEG_MGCG; 924 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 925 AMD_PG_SUPPORT_VCN | 926 AMD_PG_SUPPORT_VCN_DPG | 927 AMD_PG_SUPPORT_JPEG; 928 adev->external_rev_id = adev->rev_id + 0x01; 929 break; 930 case IP_VERSION(10, 3, 7): 931 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 932 AMD_CG_SUPPORT_GFX_MGLS | 933 AMD_CG_SUPPORT_GFX_CGCG | 934 AMD_CG_SUPPORT_GFX_CGLS | 935 AMD_CG_SUPPORT_GFX_3D_CGCG | 936 AMD_CG_SUPPORT_GFX_3D_CGLS | 937 AMD_CG_SUPPORT_GFX_RLC_LS | 938 AMD_CG_SUPPORT_GFX_CP_LS | 939 AMD_CG_SUPPORT_GFX_FGCG | 940 AMD_CG_SUPPORT_MC_MGCG | 941 AMD_CG_SUPPORT_MC_LS | 942 AMD_CG_SUPPORT_SDMA_LS | 943 AMD_CG_SUPPORT_HDP_MGCG | 944 AMD_CG_SUPPORT_HDP_LS | 945 AMD_CG_SUPPORT_ATHUB_MGCG | 946 AMD_CG_SUPPORT_ATHUB_LS | 947 AMD_CG_SUPPORT_IH_CG | 948 AMD_CG_SUPPORT_VCN_MGCG | 949 AMD_CG_SUPPORT_JPEG_MGCG; 950 adev->pg_flags = AMD_PG_SUPPORT_VCN | 951 AMD_PG_SUPPORT_VCN_DPG | 952 AMD_PG_SUPPORT_JPEG | 953 AMD_PG_SUPPORT_GFX_PG; 954 adev->external_rev_id = adev->rev_id + 0x01; 955 break; 956 default: 957 /* FIXME: not supported yet */ 958 return -EINVAL; 959 } 960 961 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 962 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 963 AMD_PG_SUPPORT_VCN_DPG | 964 AMD_PG_SUPPORT_JPEG); 965 966 if (amdgpu_sriov_vf(adev)) { 967 amdgpu_virt_init_setting(adev); 968 xgpu_nv_mailbox_set_irq_funcs(adev); 969 } 970 971 return 0; 972 } 973 974 static int nv_common_late_init(void *handle) 975 { 976 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 977 978 if (amdgpu_sriov_vf(adev)) { 979 xgpu_nv_mailbox_get_irq(adev); 980 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 981 amdgpu_virt_update_sriov_video_codec(adev, 982 sriov_sc_video_codecs_encode_array, 983 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 984 sriov_sc_video_codecs_decode_array_vcn1, 985 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1)); 986 } else { 987 amdgpu_virt_update_sriov_video_codec(adev, 988 sriov_sc_video_codecs_encode_array, 989 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 990 sriov_sc_video_codecs_decode_array_vcn0, 991 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0)); 992 } 993 } 994 995 /* Enable selfring doorbell aperture late because doorbell BAR 996 * aperture will change if resize BAR successfully in gmc sw_init. 997 */ 998 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 999 1000 return 0; 1001 } 1002 1003 static int nv_common_sw_init(void *handle) 1004 { 1005 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1006 1007 if (amdgpu_sriov_vf(adev)) 1008 xgpu_nv_mailbox_add_irq_id(adev); 1009 1010 return 0; 1011 } 1012 1013 static int nv_common_sw_fini(void *handle) 1014 { 1015 return 0; 1016 } 1017 1018 static int nv_common_hw_init(void *handle) 1019 { 1020 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1021 1022 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 1023 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 1024 1025 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1026 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1027 1028 /* enable aspm */ 1029 nv_program_aspm(adev); 1030 /* setup nbio registers */ 1031 adev->nbio.funcs->init_registers(adev); 1032 /* remap HDP registers to a hole in mmio space, 1033 * for the purpose of expose those registers 1034 * to process space 1035 */ 1036 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1037 adev->nbio.funcs->remap_hdp_registers(adev); 1038 /* enable the doorbell aperture */ 1039 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1040 1041 return 0; 1042 } 1043 1044 static int nv_common_hw_fini(void *handle) 1045 { 1046 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1047 1048 /* Disable the doorbell aperture and selfring doorbell aperture 1049 * separately in hw_fini because nv_enable_doorbell_aperture 1050 * has been removed and there is no need to delay disabling 1051 * selfring doorbell. 1052 */ 1053 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1054 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1055 1056 return 0; 1057 } 1058 1059 static int nv_common_suspend(void *handle) 1060 { 1061 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1062 1063 return nv_common_hw_fini(adev); 1064 } 1065 1066 static int nv_common_resume(void *handle) 1067 { 1068 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1069 1070 return nv_common_hw_init(adev); 1071 } 1072 1073 static bool nv_common_is_idle(void *handle) 1074 { 1075 return true; 1076 } 1077 1078 static int nv_common_wait_for_idle(void *handle) 1079 { 1080 return 0; 1081 } 1082 1083 static int nv_common_soft_reset(void *handle) 1084 { 1085 return 0; 1086 } 1087 1088 static int nv_common_set_clockgating_state(void *handle, 1089 enum amd_clockgating_state state) 1090 { 1091 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1092 1093 if (amdgpu_sriov_vf(adev)) 1094 return 0; 1095 1096 switch (adev->ip_versions[NBIO_HWIP][0]) { 1097 case IP_VERSION(2, 3, 0): 1098 case IP_VERSION(2, 3, 1): 1099 case IP_VERSION(2, 3, 2): 1100 case IP_VERSION(3, 3, 0): 1101 case IP_VERSION(3, 3, 1): 1102 case IP_VERSION(3, 3, 2): 1103 case IP_VERSION(3, 3, 3): 1104 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1105 state == AMD_CG_STATE_GATE); 1106 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1107 state == AMD_CG_STATE_GATE); 1108 adev->hdp.funcs->update_clock_gating(adev, 1109 state == AMD_CG_STATE_GATE); 1110 adev->smuio.funcs->update_rom_clock_gating(adev, 1111 state == AMD_CG_STATE_GATE); 1112 break; 1113 default: 1114 break; 1115 } 1116 return 0; 1117 } 1118 1119 static int nv_common_set_powergating_state(void *handle, 1120 enum amd_powergating_state state) 1121 { 1122 /* TODO */ 1123 return 0; 1124 } 1125 1126 static void nv_common_get_clockgating_state(void *handle, u64 *flags) 1127 { 1128 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1129 1130 if (amdgpu_sriov_vf(adev)) 1131 *flags = 0; 1132 1133 adev->nbio.funcs->get_clockgating_state(adev, flags); 1134 1135 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1136 1137 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1138 1139 return; 1140 } 1141 1142 static const struct amd_ip_funcs nv_common_ip_funcs = { 1143 .name = "nv_common", 1144 .early_init = nv_common_early_init, 1145 .late_init = nv_common_late_init, 1146 .sw_init = nv_common_sw_init, 1147 .sw_fini = nv_common_sw_fini, 1148 .hw_init = nv_common_hw_init, 1149 .hw_fini = nv_common_hw_fini, 1150 .suspend = nv_common_suspend, 1151 .resume = nv_common_resume, 1152 .is_idle = nv_common_is_idle, 1153 .wait_for_idle = nv_common_wait_for_idle, 1154 .soft_reset = nv_common_soft_reset, 1155 .set_clockgating_state = nv_common_set_clockgating_state, 1156 .set_powergating_state = nv_common_set_powergating_state, 1157 .get_clockgating_state = nv_common_get_clockgating_state, 1158 }; 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