1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "smuio/smuio_11_0_0_offset.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "dce_virtual.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 65 static const struct amd_ip_funcs nv_common_ip_funcs; 66 67 /* 68 * Indirect registers accessor 69 */ 70 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 71 { 72 unsigned long address, data; 73 address = adev->nbio.funcs->get_pcie_index_offset(adev); 74 data = adev->nbio.funcs->get_pcie_data_offset(adev); 75 76 return amdgpu_device_indirect_rreg(adev, address, data, reg); 77 } 78 79 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 80 { 81 unsigned long address, data; 82 83 address = adev->nbio.funcs->get_pcie_index_offset(adev); 84 data = adev->nbio.funcs->get_pcie_data_offset(adev); 85 86 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 87 } 88 89 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 90 { 91 unsigned long address, data; 92 address = adev->nbio.funcs->get_pcie_index_offset(adev); 93 data = adev->nbio.funcs->get_pcie_data_offset(adev); 94 95 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 96 } 97 98 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 99 { 100 unsigned long flags, address, data; 101 u32 r; 102 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 103 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 104 105 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 106 WREG32(address, reg * 4); 107 (void)RREG32(address); 108 r = RREG32(data); 109 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 110 return r; 111 } 112 113 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 114 { 115 unsigned long address, data; 116 117 address = adev->nbio.funcs->get_pcie_index_offset(adev); 118 data = adev->nbio.funcs->get_pcie_data_offset(adev); 119 120 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 121 } 122 123 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 124 { 125 unsigned long flags, address, data; 126 127 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 128 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 129 130 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 131 WREG32(address, reg * 4); 132 (void)RREG32(address); 133 WREG32(data, v); 134 (void)RREG32(data); 135 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 136 } 137 138 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 139 { 140 unsigned long flags, address, data; 141 u32 r; 142 143 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 144 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 145 146 spin_lock_irqsave(&adev->didt_idx_lock, flags); 147 WREG32(address, (reg)); 148 r = RREG32(data); 149 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 150 return r; 151 } 152 153 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 154 { 155 unsigned long flags, address, data; 156 157 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 158 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 159 160 spin_lock_irqsave(&adev->didt_idx_lock, flags); 161 WREG32(address, (reg)); 162 WREG32(data, (v)); 163 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 164 } 165 166 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 167 { 168 return adev->nbio.funcs->get_memsize(adev); 169 } 170 171 static u32 nv_get_xclk(struct amdgpu_device *adev) 172 { 173 return adev->clock.spll.reference_freq; 174 } 175 176 177 void nv_grbm_select(struct amdgpu_device *adev, 178 u32 me, u32 pipe, u32 queue, u32 vmid) 179 { 180 u32 grbm_gfx_cntl = 0; 181 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 182 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 183 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 184 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 185 186 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 187 } 188 189 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 190 { 191 /* todo */ 192 } 193 194 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 195 { 196 /* todo */ 197 return false; 198 } 199 200 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 201 u8 *bios, u32 length_bytes) 202 { 203 u32 *dw_ptr; 204 u32 i, length_dw; 205 206 if (bios == NULL) 207 return false; 208 if (length_bytes == 0) 209 return false; 210 /* APU vbios image is part of sbios image */ 211 if (adev->flags & AMD_IS_APU) 212 return false; 213 214 dw_ptr = (u32 *)bios; 215 length_dw = ALIGN(length_bytes, 4) / 4; 216 217 /* set rom index to 0 */ 218 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 219 /* read out the rom data */ 220 for (i = 0; i < length_dw; i++) 221 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 222 223 return true; 224 } 225 226 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 227 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 228 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 229 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 230 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 231 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 232 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 233 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 234 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 235 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 236 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 237 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 238 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 239 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 240 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 241 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 242 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 243 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 244 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 245 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 246 }; 247 248 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 249 u32 sh_num, u32 reg_offset) 250 { 251 uint32_t val; 252 253 mutex_lock(&adev->grbm_idx_mutex); 254 if (se_num != 0xffffffff || sh_num != 0xffffffff) 255 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 256 257 val = RREG32(reg_offset); 258 259 if (se_num != 0xffffffff || sh_num != 0xffffffff) 260 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 261 mutex_unlock(&adev->grbm_idx_mutex); 262 return val; 263 } 264 265 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 266 bool indexed, u32 se_num, 267 u32 sh_num, u32 reg_offset) 268 { 269 if (indexed) { 270 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 271 } else { 272 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 273 return adev->gfx.config.gb_addr_config; 274 return RREG32(reg_offset); 275 } 276 } 277 278 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 279 u32 sh_num, u32 reg_offset, u32 *value) 280 { 281 uint32_t i; 282 struct soc15_allowed_register_entry *en; 283 284 *value = 0; 285 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 286 en = &nv_allowed_read_registers[i]; 287 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 288 reg_offset != 289 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 290 continue; 291 292 *value = nv_get_register_value(adev, 293 nv_allowed_read_registers[i].grbm_indexed, 294 se_num, sh_num, reg_offset); 295 return 0; 296 } 297 return -EINVAL; 298 } 299 300 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 301 { 302 u32 i; 303 int ret = 0; 304 305 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 306 307 /* disable BM */ 308 pci_clear_master(adev->pdev); 309 310 amdgpu_device_cache_pci_state(adev->pdev); 311 312 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 313 dev_info(adev->dev, "GPU smu mode1 reset\n"); 314 ret = amdgpu_dpm_mode1_reset(adev); 315 } else { 316 dev_info(adev->dev, "GPU psp mode1 reset\n"); 317 ret = psp_gpu_reset(adev); 318 } 319 320 if (ret) 321 dev_err(adev->dev, "GPU mode1 reset failed\n"); 322 amdgpu_device_load_pci_state(adev->pdev); 323 324 /* wait for asic to come out of reset */ 325 for (i = 0; i < adev->usec_timeout; i++) { 326 u32 memsize = adev->nbio.funcs->get_memsize(adev); 327 328 if (memsize != 0xffffffff) 329 break; 330 udelay(1); 331 } 332 333 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 334 335 return ret; 336 } 337 338 static bool nv_asic_supports_baco(struct amdgpu_device *adev) 339 { 340 struct smu_context *smu = &adev->smu; 341 342 if (smu_baco_is_support(smu)) 343 return true; 344 else 345 return false; 346 } 347 348 static enum amd_reset_method 349 nv_asic_reset_method(struct amdgpu_device *adev) 350 { 351 struct smu_context *smu = &adev->smu; 352 353 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 354 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 355 return amdgpu_reset_method; 356 357 if (amdgpu_reset_method != -1) 358 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 359 amdgpu_reset_method); 360 361 switch (adev->asic_type) { 362 case CHIP_SIENNA_CICHLID: 363 case CHIP_NAVY_FLOUNDER: 364 case CHIP_DIMGREY_CAVEFISH: 365 return AMD_RESET_METHOD_MODE1; 366 default: 367 if (smu_baco_is_support(smu)) 368 return AMD_RESET_METHOD_BACO; 369 else 370 return AMD_RESET_METHOD_MODE1; 371 } 372 } 373 374 static int nv_asic_reset(struct amdgpu_device *adev) 375 { 376 int ret = 0; 377 struct smu_context *smu = &adev->smu; 378 379 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 380 dev_info(adev->dev, "BACO reset\n"); 381 382 ret = smu_baco_enter(smu); 383 if (ret) 384 return ret; 385 ret = smu_baco_exit(smu); 386 if (ret) 387 return ret; 388 } else { 389 dev_info(adev->dev, "MODE1 reset\n"); 390 ret = nv_asic_mode1_reset(adev); 391 } 392 393 return ret; 394 } 395 396 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 397 { 398 /* todo */ 399 return 0; 400 } 401 402 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 403 { 404 /* todo */ 405 return 0; 406 } 407 408 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 409 { 410 if (pci_is_root_bus(adev->pdev->bus)) 411 return; 412 413 if (amdgpu_pcie_gen2 == 0) 414 return; 415 416 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 417 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 418 return; 419 420 /* todo */ 421 } 422 423 static void nv_program_aspm(struct amdgpu_device *adev) 424 { 425 426 if (amdgpu_aspm == 0) 427 return; 428 429 /* todo */ 430 } 431 432 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 433 bool enable) 434 { 435 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 436 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 437 } 438 439 static const struct amdgpu_ip_block_version nv_common_ip_block = 440 { 441 .type = AMD_IP_BLOCK_TYPE_COMMON, 442 .major = 1, 443 .minor = 0, 444 .rev = 0, 445 .funcs = &nv_common_ip_funcs, 446 }; 447 448 static int nv_reg_base_init(struct amdgpu_device *adev) 449 { 450 int r; 451 452 if (amdgpu_discovery) { 453 r = amdgpu_discovery_reg_base_init(adev); 454 if (r) { 455 DRM_WARN("failed to init reg base from ip discovery table, " 456 "fallback to legacy init method\n"); 457 goto legacy_init; 458 } 459 460 return 0; 461 } 462 463 legacy_init: 464 switch (adev->asic_type) { 465 case CHIP_NAVI10: 466 navi10_reg_base_init(adev); 467 break; 468 case CHIP_NAVI14: 469 navi14_reg_base_init(adev); 470 break; 471 case CHIP_NAVI12: 472 navi12_reg_base_init(adev); 473 break; 474 case CHIP_SIENNA_CICHLID: 475 case CHIP_NAVY_FLOUNDER: 476 sienna_cichlid_reg_base_init(adev); 477 break; 478 case CHIP_VANGOGH: 479 vangogh_reg_base_init(adev); 480 break; 481 case CHIP_DIMGREY_CAVEFISH: 482 dimgrey_cavefish_reg_base_init(adev); 483 break; 484 default: 485 return -EINVAL; 486 } 487 488 return 0; 489 } 490 491 void nv_set_virt_ops(struct amdgpu_device *adev) 492 { 493 adev->virt.ops = &xgpu_nv_virt_ops; 494 } 495 496 static bool nv_is_headless_sku(struct pci_dev *pdev) 497 { 498 if ((pdev->device == 0x731E && 499 (pdev->revision == 0xC6 || pdev->revision == 0xC7)) || 500 (pdev->device == 0x7340 && pdev->revision == 0xC9)) 501 return true; 502 return false; 503 } 504 505 int nv_set_ip_blocks(struct amdgpu_device *adev) 506 { 507 int r; 508 509 if (adev->flags & AMD_IS_APU) { 510 adev->nbio.funcs = &nbio_v7_2_funcs; 511 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 512 } else { 513 adev->nbio.funcs = &nbio_v2_3_funcs; 514 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 515 } 516 adev->hdp.funcs = &hdp_v5_0_funcs; 517 518 if (adev->asic_type == CHIP_SIENNA_CICHLID) 519 adev->gmc.xgmi.supported = true; 520 521 /* Set IP register base before any HW register access */ 522 r = nv_reg_base_init(adev); 523 if (r) 524 return r; 525 526 switch (adev->asic_type) { 527 case CHIP_NAVI10: 528 case CHIP_NAVI14: 529 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 530 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 531 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 532 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 533 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 534 !amdgpu_sriov_vf(adev)) 535 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 536 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 537 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 538 #if defined(CONFIG_DRM_AMD_DC) 539 else if (amdgpu_device_has_dc_support(adev)) 540 amdgpu_device_ip_block_add(adev, &dm_ip_block); 541 #endif 542 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 543 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 544 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 545 !amdgpu_sriov_vf(adev)) 546 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 547 if (!nv_is_headless_sku(adev->pdev)) 548 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 549 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 550 if (adev->enable_mes) 551 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 552 break; 553 case CHIP_NAVI12: 554 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 555 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 556 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 557 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 558 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 559 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 560 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 561 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 562 #if defined(CONFIG_DRM_AMD_DC) 563 else if (amdgpu_device_has_dc_support(adev)) 564 amdgpu_device_ip_block_add(adev, &dm_ip_block); 565 #endif 566 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 567 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 568 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 569 !amdgpu_sriov_vf(adev)) 570 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 571 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 572 if (!amdgpu_sriov_vf(adev)) 573 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 574 break; 575 case CHIP_SIENNA_CICHLID: 576 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 577 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 578 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 579 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 580 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 581 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 582 is_support_sw_smu(adev)) 583 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 584 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 585 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 586 #if defined(CONFIG_DRM_AMD_DC) 587 else if (amdgpu_device_has_dc_support(adev)) 588 amdgpu_device_ip_block_add(adev, &dm_ip_block); 589 #endif 590 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 591 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 592 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 593 if (!amdgpu_sriov_vf(adev)) 594 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 595 596 if (adev->enable_mes) 597 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 598 break; 599 case CHIP_NAVY_FLOUNDER: 600 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 601 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 602 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 603 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 604 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 605 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 606 is_support_sw_smu(adev)) 607 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 608 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 609 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 610 #if defined(CONFIG_DRM_AMD_DC) 611 else if (amdgpu_device_has_dc_support(adev)) 612 amdgpu_device_ip_block_add(adev, &dm_ip_block); 613 #endif 614 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 615 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 616 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 617 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 618 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 619 is_support_sw_smu(adev)) 620 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 621 break; 622 case CHIP_VANGOGH: 623 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 624 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 625 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 626 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 627 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 628 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 629 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 630 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 631 #if defined(CONFIG_DRM_AMD_DC) 632 else if (amdgpu_device_has_dc_support(adev)) 633 amdgpu_device_ip_block_add(adev, &dm_ip_block); 634 #endif 635 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 636 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 637 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 638 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 639 break; 640 case CHIP_DIMGREY_CAVEFISH: 641 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 642 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 643 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 644 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 645 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 646 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 647 is_support_sw_smu(adev)) 648 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 649 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 650 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 651 #if defined(CONFIG_DRM_AMD_DC) 652 else if (amdgpu_device_has_dc_support(adev)) 653 amdgpu_device_ip_block_add(adev, &dm_ip_block); 654 #endif 655 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 656 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 657 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 658 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 659 break; 660 default: 661 return -EINVAL; 662 } 663 664 return 0; 665 } 666 667 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 668 { 669 return adev->nbio.funcs->get_rev_id(adev); 670 } 671 672 static bool nv_need_full_reset(struct amdgpu_device *adev) 673 { 674 return true; 675 } 676 677 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 678 { 679 u32 sol_reg; 680 681 if (adev->flags & AMD_IS_APU) 682 return false; 683 684 /* Check sOS sign of life register to confirm sys driver and sOS 685 * are already been loaded. 686 */ 687 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 688 if (sol_reg) 689 return true; 690 691 return false; 692 } 693 694 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 695 { 696 697 /* TODO 698 * dummy implement for pcie_replay_count sysfs interface 699 * */ 700 701 return 0; 702 } 703 704 static void nv_init_doorbell_index(struct amdgpu_device *adev) 705 { 706 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 707 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 708 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 709 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 710 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 711 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 712 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 713 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 714 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 715 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 716 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 717 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 718 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 719 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 720 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 721 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 722 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 723 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 724 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 725 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 726 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 727 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 728 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 729 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 730 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 731 732 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 733 adev->doorbell_index.sdma_doorbell_range = 20; 734 } 735 736 static void nv_pre_asic_init(struct amdgpu_device *adev) 737 { 738 } 739 740 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 741 bool enter) 742 { 743 if (enter) 744 amdgpu_gfx_rlc_enter_safe_mode(adev); 745 else 746 amdgpu_gfx_rlc_exit_safe_mode(adev); 747 748 if (adev->gfx.funcs->update_perfmon_mgcg) 749 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 750 751 /* 752 * The ASPM function is not fully enabled and verified on 753 * Navi yet. Temporarily skip this until ASPM enabled. 754 */ 755 #if 0 756 if (adev->nbio.funcs->enable_aspm) 757 adev->nbio.funcs->enable_aspm(adev, !enter); 758 #endif 759 760 return 0; 761 } 762 763 static const struct amdgpu_asic_funcs nv_asic_funcs = 764 { 765 .read_disabled_bios = &nv_read_disabled_bios, 766 .read_bios_from_rom = &nv_read_bios_from_rom, 767 .read_register = &nv_read_register, 768 .reset = &nv_asic_reset, 769 .reset_method = &nv_asic_reset_method, 770 .set_vga_state = &nv_vga_set_state, 771 .get_xclk = &nv_get_xclk, 772 .set_uvd_clocks = &nv_set_uvd_clocks, 773 .set_vce_clocks = &nv_set_vce_clocks, 774 .get_config_memsize = &nv_get_config_memsize, 775 .init_doorbell_index = &nv_init_doorbell_index, 776 .need_full_reset = &nv_need_full_reset, 777 .need_reset_on_init = &nv_need_reset_on_init, 778 .get_pcie_replay_count = &nv_get_pcie_replay_count, 779 .supports_baco = &nv_asic_supports_baco, 780 .pre_asic_init = &nv_pre_asic_init, 781 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 782 }; 783 784 static int nv_common_early_init(void *handle) 785 { 786 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 787 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 788 789 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 790 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 791 adev->smc_rreg = NULL; 792 adev->smc_wreg = NULL; 793 adev->pcie_rreg = &nv_pcie_rreg; 794 adev->pcie_wreg = &nv_pcie_wreg; 795 adev->pcie_rreg64 = &nv_pcie_rreg64; 796 adev->pcie_wreg64 = &nv_pcie_wreg64; 797 adev->pciep_rreg = &nv_pcie_port_rreg; 798 adev->pciep_wreg = &nv_pcie_port_wreg; 799 800 /* TODO: will add them during VCN v2 implementation */ 801 adev->uvd_ctx_rreg = NULL; 802 adev->uvd_ctx_wreg = NULL; 803 804 adev->didt_rreg = &nv_didt_rreg; 805 adev->didt_wreg = &nv_didt_wreg; 806 807 adev->asic_funcs = &nv_asic_funcs; 808 809 adev->rev_id = nv_get_rev_id(adev); 810 adev->external_rev_id = 0xff; 811 switch (adev->asic_type) { 812 case CHIP_NAVI10: 813 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 814 AMD_CG_SUPPORT_GFX_CGCG | 815 AMD_CG_SUPPORT_IH_CG | 816 AMD_CG_SUPPORT_HDP_MGCG | 817 AMD_CG_SUPPORT_HDP_LS | 818 AMD_CG_SUPPORT_SDMA_MGCG | 819 AMD_CG_SUPPORT_SDMA_LS | 820 AMD_CG_SUPPORT_MC_MGCG | 821 AMD_CG_SUPPORT_MC_LS | 822 AMD_CG_SUPPORT_ATHUB_MGCG | 823 AMD_CG_SUPPORT_ATHUB_LS | 824 AMD_CG_SUPPORT_VCN_MGCG | 825 AMD_CG_SUPPORT_JPEG_MGCG | 826 AMD_CG_SUPPORT_BIF_MGCG | 827 AMD_CG_SUPPORT_BIF_LS; 828 adev->pg_flags = AMD_PG_SUPPORT_VCN | 829 AMD_PG_SUPPORT_VCN_DPG | 830 AMD_PG_SUPPORT_JPEG | 831 AMD_PG_SUPPORT_ATHUB; 832 adev->external_rev_id = adev->rev_id + 0x1; 833 break; 834 case CHIP_NAVI14: 835 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 836 AMD_CG_SUPPORT_GFX_CGCG | 837 AMD_CG_SUPPORT_IH_CG | 838 AMD_CG_SUPPORT_HDP_MGCG | 839 AMD_CG_SUPPORT_HDP_LS | 840 AMD_CG_SUPPORT_SDMA_MGCG | 841 AMD_CG_SUPPORT_SDMA_LS | 842 AMD_CG_SUPPORT_MC_MGCG | 843 AMD_CG_SUPPORT_MC_LS | 844 AMD_CG_SUPPORT_ATHUB_MGCG | 845 AMD_CG_SUPPORT_ATHUB_LS | 846 AMD_CG_SUPPORT_VCN_MGCG | 847 AMD_CG_SUPPORT_JPEG_MGCG | 848 AMD_CG_SUPPORT_BIF_MGCG | 849 AMD_CG_SUPPORT_BIF_LS; 850 adev->pg_flags = AMD_PG_SUPPORT_VCN | 851 AMD_PG_SUPPORT_JPEG | 852 AMD_PG_SUPPORT_VCN_DPG; 853 adev->external_rev_id = adev->rev_id + 20; 854 break; 855 case CHIP_NAVI12: 856 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 857 AMD_CG_SUPPORT_GFX_MGLS | 858 AMD_CG_SUPPORT_GFX_CGCG | 859 AMD_CG_SUPPORT_GFX_CP_LS | 860 AMD_CG_SUPPORT_GFX_RLC_LS | 861 AMD_CG_SUPPORT_IH_CG | 862 AMD_CG_SUPPORT_HDP_MGCG | 863 AMD_CG_SUPPORT_HDP_LS | 864 AMD_CG_SUPPORT_SDMA_MGCG | 865 AMD_CG_SUPPORT_SDMA_LS | 866 AMD_CG_SUPPORT_MC_MGCG | 867 AMD_CG_SUPPORT_MC_LS | 868 AMD_CG_SUPPORT_ATHUB_MGCG | 869 AMD_CG_SUPPORT_ATHUB_LS | 870 AMD_CG_SUPPORT_VCN_MGCG | 871 AMD_CG_SUPPORT_JPEG_MGCG; 872 adev->pg_flags = AMD_PG_SUPPORT_VCN | 873 AMD_PG_SUPPORT_VCN_DPG | 874 AMD_PG_SUPPORT_JPEG | 875 AMD_PG_SUPPORT_ATHUB; 876 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 877 * as a consequence, the rev_id and external_rev_id are wrong. 878 * workaround it by hardcoding rev_id to 0 (default value). 879 */ 880 if (amdgpu_sriov_vf(adev)) 881 adev->rev_id = 0; 882 adev->external_rev_id = adev->rev_id + 0xa; 883 break; 884 case CHIP_SIENNA_CICHLID: 885 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 886 AMD_CG_SUPPORT_GFX_CGCG | 887 AMD_CG_SUPPORT_GFX_3D_CGCG | 888 AMD_CG_SUPPORT_MC_MGCG | 889 AMD_CG_SUPPORT_VCN_MGCG | 890 AMD_CG_SUPPORT_JPEG_MGCG | 891 AMD_CG_SUPPORT_HDP_MGCG | 892 AMD_CG_SUPPORT_HDP_LS | 893 AMD_CG_SUPPORT_IH_CG | 894 AMD_CG_SUPPORT_MC_LS; 895 adev->pg_flags = AMD_PG_SUPPORT_VCN | 896 AMD_PG_SUPPORT_VCN_DPG | 897 AMD_PG_SUPPORT_JPEG | 898 AMD_PG_SUPPORT_ATHUB | 899 AMD_PG_SUPPORT_MMHUB; 900 if (amdgpu_sriov_vf(adev)) { 901 /* hypervisor control CG and PG enablement */ 902 adev->cg_flags = 0; 903 adev->pg_flags = 0; 904 } 905 adev->external_rev_id = adev->rev_id + 0x28; 906 break; 907 case CHIP_NAVY_FLOUNDER: 908 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 909 AMD_CG_SUPPORT_GFX_CGCG | 910 AMD_CG_SUPPORT_GFX_3D_CGCG | 911 AMD_CG_SUPPORT_VCN_MGCG | 912 AMD_CG_SUPPORT_JPEG_MGCG | 913 AMD_CG_SUPPORT_MC_MGCG | 914 AMD_CG_SUPPORT_MC_LS | 915 AMD_CG_SUPPORT_HDP_MGCG | 916 AMD_CG_SUPPORT_HDP_LS | 917 AMD_CG_SUPPORT_IH_CG; 918 adev->pg_flags = AMD_PG_SUPPORT_VCN | 919 AMD_PG_SUPPORT_VCN_DPG | 920 AMD_PG_SUPPORT_JPEG | 921 AMD_PG_SUPPORT_ATHUB | 922 AMD_PG_SUPPORT_MMHUB; 923 adev->external_rev_id = adev->rev_id + 0x32; 924 break; 925 926 case CHIP_VANGOGH: 927 adev->apu_flags |= AMD_APU_IS_VANGOGH; 928 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 929 AMD_CG_SUPPORT_GFX_MGLS | 930 AMD_CG_SUPPORT_GFX_CP_LS | 931 AMD_CG_SUPPORT_GFX_RLC_LS | 932 AMD_CG_SUPPORT_GFX_CGCG | 933 AMD_CG_SUPPORT_GFX_CGLS | 934 AMD_CG_SUPPORT_GFX_3D_CGCG | 935 AMD_CG_SUPPORT_GFX_3D_CGLS | 936 AMD_CG_SUPPORT_MC_MGCG | 937 AMD_CG_SUPPORT_MC_LS | 938 AMD_CG_SUPPORT_GFX_FGCG | 939 AMD_CG_SUPPORT_VCN_MGCG | 940 AMD_CG_SUPPORT_JPEG_MGCG; 941 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 942 AMD_PG_SUPPORT_VCN | 943 AMD_PG_SUPPORT_VCN_DPG | 944 AMD_PG_SUPPORT_JPEG; 945 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 946 adev->external_rev_id = adev->rev_id + 0x01; 947 break; 948 case CHIP_DIMGREY_CAVEFISH: 949 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 950 AMD_CG_SUPPORT_GFX_CGCG | 951 AMD_CG_SUPPORT_GFX_3D_CGCG | 952 AMD_CG_SUPPORT_VCN_MGCG | 953 AMD_CG_SUPPORT_JPEG_MGCG | 954 AMD_CG_SUPPORT_MC_MGCG | 955 AMD_CG_SUPPORT_MC_LS | 956 AMD_CG_SUPPORT_HDP_MGCG | 957 AMD_CG_SUPPORT_HDP_LS | 958 AMD_CG_SUPPORT_IH_CG; 959 adev->pg_flags = AMD_PG_SUPPORT_VCN | 960 AMD_PG_SUPPORT_VCN_DPG | 961 AMD_PG_SUPPORT_JPEG | 962 AMD_PG_SUPPORT_ATHUB | 963 AMD_PG_SUPPORT_MMHUB; 964 adev->external_rev_id = adev->rev_id + 0x3c; 965 break; 966 default: 967 /* FIXME: not supported yet */ 968 return -EINVAL; 969 } 970 971 if (amdgpu_sriov_vf(adev)) { 972 amdgpu_virt_init_setting(adev); 973 xgpu_nv_mailbox_set_irq_funcs(adev); 974 } 975 976 return 0; 977 } 978 979 static int nv_common_late_init(void *handle) 980 { 981 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 982 983 if (amdgpu_sriov_vf(adev)) 984 xgpu_nv_mailbox_get_irq(adev); 985 986 return 0; 987 } 988 989 static int nv_common_sw_init(void *handle) 990 { 991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 992 993 if (amdgpu_sriov_vf(adev)) 994 xgpu_nv_mailbox_add_irq_id(adev); 995 996 return 0; 997 } 998 999 static int nv_common_sw_fini(void *handle) 1000 { 1001 return 0; 1002 } 1003 1004 static int nv_common_hw_init(void *handle) 1005 { 1006 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1007 1008 /* enable pcie gen2/3 link */ 1009 nv_pcie_gen3_enable(adev); 1010 /* enable aspm */ 1011 nv_program_aspm(adev); 1012 /* setup nbio registers */ 1013 adev->nbio.funcs->init_registers(adev); 1014 /* remap HDP registers to a hole in mmio space, 1015 * for the purpose of expose those registers 1016 * to process space 1017 */ 1018 if (adev->nbio.funcs->remap_hdp_registers) 1019 adev->nbio.funcs->remap_hdp_registers(adev); 1020 /* enable the doorbell aperture */ 1021 nv_enable_doorbell_aperture(adev, true); 1022 1023 return 0; 1024 } 1025 1026 static int nv_common_hw_fini(void *handle) 1027 { 1028 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1029 1030 /* disable the doorbell aperture */ 1031 nv_enable_doorbell_aperture(adev, false); 1032 1033 return 0; 1034 } 1035 1036 static int nv_common_suspend(void *handle) 1037 { 1038 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1039 1040 return nv_common_hw_fini(adev); 1041 } 1042 1043 static int nv_common_resume(void *handle) 1044 { 1045 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1046 1047 return nv_common_hw_init(adev); 1048 } 1049 1050 static bool nv_common_is_idle(void *handle) 1051 { 1052 return true; 1053 } 1054 1055 static int nv_common_wait_for_idle(void *handle) 1056 { 1057 return 0; 1058 } 1059 1060 static int nv_common_soft_reset(void *handle) 1061 { 1062 return 0; 1063 } 1064 1065 static int nv_common_set_clockgating_state(void *handle, 1066 enum amd_clockgating_state state) 1067 { 1068 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1069 1070 if (amdgpu_sriov_vf(adev)) 1071 return 0; 1072 1073 switch (adev->asic_type) { 1074 case CHIP_NAVI10: 1075 case CHIP_NAVI14: 1076 case CHIP_NAVI12: 1077 case CHIP_SIENNA_CICHLID: 1078 case CHIP_NAVY_FLOUNDER: 1079 case CHIP_DIMGREY_CAVEFISH: 1080 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1081 state == AMD_CG_STATE_GATE); 1082 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1083 state == AMD_CG_STATE_GATE); 1084 adev->hdp.funcs->update_clock_gating(adev, 1085 state == AMD_CG_STATE_GATE); 1086 break; 1087 default: 1088 break; 1089 } 1090 return 0; 1091 } 1092 1093 static int nv_common_set_powergating_state(void *handle, 1094 enum amd_powergating_state state) 1095 { 1096 /* TODO */ 1097 return 0; 1098 } 1099 1100 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1101 { 1102 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1103 1104 if (amdgpu_sriov_vf(adev)) 1105 *flags = 0; 1106 1107 adev->nbio.funcs->get_clockgating_state(adev, flags); 1108 1109 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1110 1111 return; 1112 } 1113 1114 static const struct amd_ip_funcs nv_common_ip_funcs = { 1115 .name = "nv_common", 1116 .early_init = nv_common_early_init, 1117 .late_init = nv_common_late_init, 1118 .sw_init = nv_common_sw_init, 1119 .sw_fini = nv_common_sw_fini, 1120 .hw_init = nv_common_hw_init, 1121 .hw_fini = nv_common_hw_fini, 1122 .suspend = nv_common_suspend, 1123 .resume = nv_common_resume, 1124 .is_idle = nv_common_is_idle, 1125 .wait_for_idle = nv_common_wait_for_idle, 1126 .soft_reset = nv_common_soft_reset, 1127 .set_clockgating_state = nv_common_set_clockgating_state, 1128 .set_powergating_state = nv_common_set_powergating_state, 1129 .get_clockgating_state = nv_common_get_clockgating_state, 1130 }; 1131