1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 74 }; 75 76 static const struct amdgpu_video_codecs nv_video_codecs_encode = 77 { 78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 79 .codec_array = nv_video_codecs_encode_array, 80 }; 81 82 /* Navi1x */ 83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 92 }; 93 94 static const struct amdgpu_video_codecs nv_video_codecs_decode = 95 { 96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 97 .codec_array = nv_video_codecs_decode_array, 98 }; 99 100 /* Sienna Cichlid */ 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 102 { 103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 104 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 111 }; 112 113 static const struct amdgpu_video_codecs sc_video_codecs_decode = 114 { 115 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 116 .codec_array = sc_video_codecs_decode_array, 117 }; 118 119 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 120 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 121 { 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 124 }; 125 126 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = 127 { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136 }; 137 138 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 139 { 140 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 141 .codec_array = sriov_sc_video_codecs_encode_array, 142 }; 143 144 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = 145 { 146 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), 147 .codec_array = sriov_sc_video_codecs_decode_array, 148 }; 149 150 /* Beige Goby*/ 151 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 153 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 154 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 155 }; 156 157 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 158 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 159 .codec_array = bg_video_codecs_decode_array, 160 }; 161 162 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 163 .codec_count = 0, 164 .codec_array = NULL, 165 }; 166 167 /* Yellow Carp*/ 168 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 169 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 170 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 171 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 172 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 173 }; 174 175 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 176 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 177 .codec_array = yc_video_codecs_decode_array, 178 }; 179 180 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 181 const struct amdgpu_video_codecs **codecs) 182 { 183 switch (adev->ip_versions[UVD_HWIP][0]) { 184 case IP_VERSION(3, 0, 0): 185 case IP_VERSION(3, 0, 64): 186 case IP_VERSION(3, 0, 192): 187 if (amdgpu_sriov_vf(adev)) { 188 if (encode) 189 *codecs = &sriov_sc_video_codecs_encode; 190 else 191 *codecs = &sriov_sc_video_codecs_decode; 192 } else { 193 if (encode) 194 *codecs = &nv_video_codecs_encode; 195 else 196 *codecs = &sc_video_codecs_decode; 197 } 198 return 0; 199 case IP_VERSION(3, 0, 16): 200 case IP_VERSION(3, 0, 2): 201 if (encode) 202 *codecs = &nv_video_codecs_encode; 203 else 204 *codecs = &sc_video_codecs_decode; 205 return 0; 206 case IP_VERSION(3, 1, 1): 207 if (encode) 208 *codecs = &nv_video_codecs_encode; 209 else 210 *codecs = &yc_video_codecs_decode; 211 return 0; 212 case IP_VERSION(3, 0, 33): 213 if (encode) 214 *codecs = &bg_video_codecs_encode; 215 else 216 *codecs = &bg_video_codecs_decode; 217 return 0; 218 case IP_VERSION(2, 0, 0): 219 case IP_VERSION(2, 0, 2): 220 if (encode) 221 *codecs = &nv_video_codecs_encode; 222 else 223 *codecs = &nv_video_codecs_decode; 224 return 0; 225 default: 226 return -EINVAL; 227 } 228 } 229 230 /* 231 * Indirect registers accessor 232 */ 233 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 234 { 235 unsigned long address, data; 236 address = adev->nbio.funcs->get_pcie_index_offset(adev); 237 data = adev->nbio.funcs->get_pcie_data_offset(adev); 238 239 return amdgpu_device_indirect_rreg(adev, address, data, reg); 240 } 241 242 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 243 { 244 unsigned long address, data; 245 246 address = adev->nbio.funcs->get_pcie_index_offset(adev); 247 data = adev->nbio.funcs->get_pcie_data_offset(adev); 248 249 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 250 } 251 252 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 253 { 254 unsigned long address, data; 255 address = adev->nbio.funcs->get_pcie_index_offset(adev); 256 data = adev->nbio.funcs->get_pcie_data_offset(adev); 257 258 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 259 } 260 261 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 262 { 263 unsigned long address, data; 264 265 address = adev->nbio.funcs->get_pcie_index_offset(adev); 266 data = adev->nbio.funcs->get_pcie_data_offset(adev); 267 268 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 269 } 270 271 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 272 { 273 unsigned long flags, address, data; 274 u32 r; 275 276 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 277 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 278 279 spin_lock_irqsave(&adev->didt_idx_lock, flags); 280 WREG32(address, (reg)); 281 r = RREG32(data); 282 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 283 return r; 284 } 285 286 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 287 { 288 unsigned long flags, address, data; 289 290 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 291 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 292 293 spin_lock_irqsave(&adev->didt_idx_lock, flags); 294 WREG32(address, (reg)); 295 WREG32(data, (v)); 296 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 297 } 298 299 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 300 { 301 return adev->nbio.funcs->get_memsize(adev); 302 } 303 304 static u32 nv_get_xclk(struct amdgpu_device *adev) 305 { 306 return adev->clock.spll.reference_freq; 307 } 308 309 310 void nv_grbm_select(struct amdgpu_device *adev, 311 u32 me, u32 pipe, u32 queue, u32 vmid) 312 { 313 u32 grbm_gfx_cntl = 0; 314 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 315 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 316 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 317 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 318 319 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 320 } 321 322 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 323 { 324 /* todo */ 325 } 326 327 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 328 { 329 /* todo */ 330 return false; 331 } 332 333 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 334 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 335 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 336 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 340 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 341 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 342 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 343 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 344 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 345 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 346 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 347 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 348 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 349 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 352 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 353 }; 354 355 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 356 u32 sh_num, u32 reg_offset) 357 { 358 uint32_t val; 359 360 mutex_lock(&adev->grbm_idx_mutex); 361 if (se_num != 0xffffffff || sh_num != 0xffffffff) 362 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 363 364 val = RREG32(reg_offset); 365 366 if (se_num != 0xffffffff || sh_num != 0xffffffff) 367 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 368 mutex_unlock(&adev->grbm_idx_mutex); 369 return val; 370 } 371 372 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 373 bool indexed, u32 se_num, 374 u32 sh_num, u32 reg_offset) 375 { 376 if (indexed) { 377 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 378 } else { 379 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 380 return adev->gfx.config.gb_addr_config; 381 return RREG32(reg_offset); 382 } 383 } 384 385 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 386 u32 sh_num, u32 reg_offset, u32 *value) 387 { 388 uint32_t i; 389 struct soc15_allowed_register_entry *en; 390 391 *value = 0; 392 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 393 en = &nv_allowed_read_registers[i]; 394 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 395 reg_offset != 396 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 397 continue; 398 399 *value = nv_get_register_value(adev, 400 nv_allowed_read_registers[i].grbm_indexed, 401 se_num, sh_num, reg_offset); 402 return 0; 403 } 404 return -EINVAL; 405 } 406 407 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 408 { 409 u32 i; 410 int ret = 0; 411 412 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 413 414 /* disable BM */ 415 pci_clear_master(adev->pdev); 416 417 amdgpu_device_cache_pci_state(adev->pdev); 418 419 ret = amdgpu_dpm_mode2_reset(adev); 420 if (ret) 421 dev_err(adev->dev, "GPU mode2 reset failed\n"); 422 423 amdgpu_device_load_pci_state(adev->pdev); 424 425 /* wait for asic to come out of reset */ 426 for (i = 0; i < adev->usec_timeout; i++) { 427 u32 memsize = adev->nbio.funcs->get_memsize(adev); 428 429 if (memsize != 0xffffffff) 430 break; 431 udelay(1); 432 } 433 434 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 435 436 return ret; 437 } 438 439 static enum amd_reset_method 440 nv_asic_reset_method(struct amdgpu_device *adev) 441 { 442 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 443 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 444 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 445 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 446 return amdgpu_reset_method; 447 448 if (amdgpu_reset_method != -1) 449 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 450 amdgpu_reset_method); 451 452 switch (adev->ip_versions[MP1_HWIP][0]) { 453 case IP_VERSION(11, 5, 0): 454 case IP_VERSION(13, 0, 1): 455 case IP_VERSION(13, 0, 3): 456 return AMD_RESET_METHOD_MODE2; 457 case IP_VERSION(11, 0, 7): 458 case IP_VERSION(11, 0, 11): 459 case IP_VERSION(11, 0, 12): 460 case IP_VERSION(11, 0, 13): 461 return AMD_RESET_METHOD_MODE1; 462 default: 463 if (amdgpu_dpm_is_baco_supported(adev)) 464 return AMD_RESET_METHOD_BACO; 465 else 466 return AMD_RESET_METHOD_MODE1; 467 } 468 } 469 470 static int nv_asic_reset(struct amdgpu_device *adev) 471 { 472 int ret = 0; 473 474 switch (nv_asic_reset_method(adev)) { 475 case AMD_RESET_METHOD_PCI: 476 dev_info(adev->dev, "PCI reset\n"); 477 ret = amdgpu_device_pci_reset(adev); 478 break; 479 case AMD_RESET_METHOD_BACO: 480 dev_info(adev->dev, "BACO reset\n"); 481 ret = amdgpu_dpm_baco_reset(adev); 482 break; 483 case AMD_RESET_METHOD_MODE2: 484 dev_info(adev->dev, "MODE2 reset\n"); 485 ret = nv_asic_mode2_reset(adev); 486 break; 487 default: 488 dev_info(adev->dev, "MODE1 reset\n"); 489 ret = amdgpu_device_mode1_reset(adev); 490 break; 491 } 492 493 return ret; 494 } 495 496 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 497 { 498 /* todo */ 499 return 0; 500 } 501 502 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 503 { 504 /* todo */ 505 return 0; 506 } 507 508 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 509 { 510 if (pci_is_root_bus(adev->pdev->bus)) 511 return; 512 513 if (amdgpu_pcie_gen2 == 0) 514 return; 515 516 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 517 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 518 return; 519 520 /* todo */ 521 } 522 523 static void nv_program_aspm(struct amdgpu_device *adev) 524 { 525 if (!amdgpu_aspm) 526 return; 527 528 if (!(adev->flags & AMD_IS_APU) && 529 (adev->nbio.funcs->program_aspm)) 530 adev->nbio.funcs->program_aspm(adev); 531 532 } 533 534 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 535 bool enable) 536 { 537 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 538 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 539 } 540 541 const struct amdgpu_ip_block_version nv_common_ip_block = 542 { 543 .type = AMD_IP_BLOCK_TYPE_COMMON, 544 .major = 1, 545 .minor = 0, 546 .rev = 0, 547 .funcs = &nv_common_ip_funcs, 548 }; 549 550 void nv_set_virt_ops(struct amdgpu_device *adev) 551 { 552 adev->virt.ops = &xgpu_nv_virt_ops; 553 } 554 555 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 556 { 557 return adev->nbio.funcs->get_rev_id(adev); 558 } 559 560 static bool nv_need_full_reset(struct amdgpu_device *adev) 561 { 562 return true; 563 } 564 565 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 566 { 567 u32 sol_reg; 568 569 if (adev->flags & AMD_IS_APU) 570 return false; 571 572 /* Check sOS sign of life register to confirm sys driver and sOS 573 * are already been loaded. 574 */ 575 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 576 if (sol_reg) 577 return true; 578 579 return false; 580 } 581 582 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 583 { 584 585 /* TODO 586 * dummy implement for pcie_replay_count sysfs interface 587 * */ 588 589 return 0; 590 } 591 592 static void nv_init_doorbell_index(struct amdgpu_device *adev) 593 { 594 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 595 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 596 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 597 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 598 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 599 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 600 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 601 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 602 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 603 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 604 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 605 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 606 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 607 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 608 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 609 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 610 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 611 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 612 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 613 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 614 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 615 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 616 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 617 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 618 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 619 620 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 621 adev->doorbell_index.sdma_doorbell_range = 20; 622 } 623 624 static void nv_pre_asic_init(struct amdgpu_device *adev) 625 { 626 } 627 628 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 629 bool enter) 630 { 631 if (enter) 632 amdgpu_gfx_rlc_enter_safe_mode(adev); 633 else 634 amdgpu_gfx_rlc_exit_safe_mode(adev); 635 636 if (adev->gfx.funcs->update_perfmon_mgcg) 637 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 638 639 if (!(adev->flags & AMD_IS_APU) && 640 (adev->nbio.funcs->enable_aspm)) 641 adev->nbio.funcs->enable_aspm(adev, !enter); 642 643 return 0; 644 } 645 646 static const struct amdgpu_asic_funcs nv_asic_funcs = 647 { 648 .read_disabled_bios = &nv_read_disabled_bios, 649 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 650 .read_register = &nv_read_register, 651 .reset = &nv_asic_reset, 652 .reset_method = &nv_asic_reset_method, 653 .set_vga_state = &nv_vga_set_state, 654 .get_xclk = &nv_get_xclk, 655 .set_uvd_clocks = &nv_set_uvd_clocks, 656 .set_vce_clocks = &nv_set_vce_clocks, 657 .get_config_memsize = &nv_get_config_memsize, 658 .init_doorbell_index = &nv_init_doorbell_index, 659 .need_full_reset = &nv_need_full_reset, 660 .need_reset_on_init = &nv_need_reset_on_init, 661 .get_pcie_replay_count = &nv_get_pcie_replay_count, 662 .supports_baco = &amdgpu_dpm_is_baco_supported, 663 .pre_asic_init = &nv_pre_asic_init, 664 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 665 .query_video_codecs = &nv_query_video_codecs, 666 }; 667 668 static int nv_common_early_init(void *handle) 669 { 670 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 671 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 672 673 if (!amdgpu_sriov_vf(adev)) { 674 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 675 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 676 } 677 adev->smc_rreg = NULL; 678 adev->smc_wreg = NULL; 679 adev->pcie_rreg = &nv_pcie_rreg; 680 adev->pcie_wreg = &nv_pcie_wreg; 681 adev->pcie_rreg64 = &nv_pcie_rreg64; 682 adev->pcie_wreg64 = &nv_pcie_wreg64; 683 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 684 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 685 686 /* TODO: will add them during VCN v2 implementation */ 687 adev->uvd_ctx_rreg = NULL; 688 adev->uvd_ctx_wreg = NULL; 689 690 adev->didt_rreg = &nv_didt_rreg; 691 adev->didt_wreg = &nv_didt_wreg; 692 693 adev->asic_funcs = &nv_asic_funcs; 694 695 adev->rev_id = nv_get_rev_id(adev); 696 adev->external_rev_id = 0xff; 697 /* TODO: split the GC and PG flags based on the relevant IP version for which 698 * they are relevant. 699 */ 700 switch (adev->ip_versions[GC_HWIP][0]) { 701 case IP_VERSION(10, 1, 10): 702 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 703 AMD_CG_SUPPORT_GFX_CGCG | 704 AMD_CG_SUPPORT_IH_CG | 705 AMD_CG_SUPPORT_HDP_MGCG | 706 AMD_CG_SUPPORT_HDP_LS | 707 AMD_CG_SUPPORT_SDMA_MGCG | 708 AMD_CG_SUPPORT_SDMA_LS | 709 AMD_CG_SUPPORT_MC_MGCG | 710 AMD_CG_SUPPORT_MC_LS | 711 AMD_CG_SUPPORT_ATHUB_MGCG | 712 AMD_CG_SUPPORT_ATHUB_LS | 713 AMD_CG_SUPPORT_VCN_MGCG | 714 AMD_CG_SUPPORT_JPEG_MGCG | 715 AMD_CG_SUPPORT_BIF_MGCG | 716 AMD_CG_SUPPORT_BIF_LS; 717 adev->pg_flags = AMD_PG_SUPPORT_VCN | 718 AMD_PG_SUPPORT_VCN_DPG | 719 AMD_PG_SUPPORT_JPEG | 720 AMD_PG_SUPPORT_ATHUB; 721 adev->external_rev_id = adev->rev_id + 0x1; 722 break; 723 case IP_VERSION(10, 1, 1): 724 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 725 AMD_CG_SUPPORT_GFX_CGCG | 726 AMD_CG_SUPPORT_IH_CG | 727 AMD_CG_SUPPORT_HDP_MGCG | 728 AMD_CG_SUPPORT_HDP_LS | 729 AMD_CG_SUPPORT_SDMA_MGCG | 730 AMD_CG_SUPPORT_SDMA_LS | 731 AMD_CG_SUPPORT_MC_MGCG | 732 AMD_CG_SUPPORT_MC_LS | 733 AMD_CG_SUPPORT_ATHUB_MGCG | 734 AMD_CG_SUPPORT_ATHUB_LS | 735 AMD_CG_SUPPORT_VCN_MGCG | 736 AMD_CG_SUPPORT_JPEG_MGCG | 737 AMD_CG_SUPPORT_BIF_MGCG | 738 AMD_CG_SUPPORT_BIF_LS; 739 adev->pg_flags = AMD_PG_SUPPORT_VCN | 740 AMD_PG_SUPPORT_JPEG | 741 AMD_PG_SUPPORT_VCN_DPG; 742 adev->external_rev_id = adev->rev_id + 20; 743 break; 744 case IP_VERSION(10, 1, 2): 745 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 746 AMD_CG_SUPPORT_GFX_MGLS | 747 AMD_CG_SUPPORT_GFX_CGCG | 748 AMD_CG_SUPPORT_GFX_CP_LS | 749 AMD_CG_SUPPORT_GFX_RLC_LS | 750 AMD_CG_SUPPORT_IH_CG | 751 AMD_CG_SUPPORT_HDP_MGCG | 752 AMD_CG_SUPPORT_HDP_LS | 753 AMD_CG_SUPPORT_SDMA_MGCG | 754 AMD_CG_SUPPORT_SDMA_LS | 755 AMD_CG_SUPPORT_MC_MGCG | 756 AMD_CG_SUPPORT_MC_LS | 757 AMD_CG_SUPPORT_ATHUB_MGCG | 758 AMD_CG_SUPPORT_ATHUB_LS | 759 AMD_CG_SUPPORT_VCN_MGCG | 760 AMD_CG_SUPPORT_JPEG_MGCG; 761 adev->pg_flags = AMD_PG_SUPPORT_VCN | 762 AMD_PG_SUPPORT_VCN_DPG | 763 AMD_PG_SUPPORT_JPEG | 764 AMD_PG_SUPPORT_ATHUB; 765 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 766 * as a consequence, the rev_id and external_rev_id are wrong. 767 * workaround it by hardcoding rev_id to 0 (default value). 768 */ 769 if (amdgpu_sriov_vf(adev)) 770 adev->rev_id = 0; 771 adev->external_rev_id = adev->rev_id + 0xa; 772 break; 773 case IP_VERSION(10, 3, 0): 774 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 775 AMD_CG_SUPPORT_GFX_CGCG | 776 AMD_CG_SUPPORT_GFX_CGLS | 777 AMD_CG_SUPPORT_GFX_3D_CGCG | 778 AMD_CG_SUPPORT_MC_MGCG | 779 AMD_CG_SUPPORT_VCN_MGCG | 780 AMD_CG_SUPPORT_JPEG_MGCG | 781 AMD_CG_SUPPORT_HDP_MGCG | 782 AMD_CG_SUPPORT_HDP_LS | 783 AMD_CG_SUPPORT_IH_CG | 784 AMD_CG_SUPPORT_MC_LS; 785 adev->pg_flags = AMD_PG_SUPPORT_VCN | 786 AMD_PG_SUPPORT_VCN_DPG | 787 AMD_PG_SUPPORT_JPEG | 788 AMD_PG_SUPPORT_ATHUB | 789 AMD_PG_SUPPORT_MMHUB; 790 if (amdgpu_sriov_vf(adev)) { 791 /* hypervisor control CG and PG enablement */ 792 adev->cg_flags = 0; 793 adev->pg_flags = 0; 794 } 795 adev->external_rev_id = adev->rev_id + 0x28; 796 break; 797 case IP_VERSION(10, 3, 2): 798 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 799 AMD_CG_SUPPORT_GFX_CGCG | 800 AMD_CG_SUPPORT_GFX_CGLS | 801 AMD_CG_SUPPORT_GFX_3D_CGCG | 802 AMD_CG_SUPPORT_VCN_MGCG | 803 AMD_CG_SUPPORT_JPEG_MGCG | 804 AMD_CG_SUPPORT_MC_MGCG | 805 AMD_CG_SUPPORT_MC_LS | 806 AMD_CG_SUPPORT_HDP_MGCG | 807 AMD_CG_SUPPORT_HDP_LS | 808 AMD_CG_SUPPORT_IH_CG; 809 adev->pg_flags = AMD_PG_SUPPORT_VCN | 810 AMD_PG_SUPPORT_VCN_DPG | 811 AMD_PG_SUPPORT_JPEG | 812 AMD_PG_SUPPORT_ATHUB | 813 AMD_PG_SUPPORT_MMHUB; 814 adev->external_rev_id = adev->rev_id + 0x32; 815 break; 816 case IP_VERSION(10, 3, 1): 817 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 818 AMD_CG_SUPPORT_GFX_MGLS | 819 AMD_CG_SUPPORT_GFX_CP_LS | 820 AMD_CG_SUPPORT_GFX_RLC_LS | 821 AMD_CG_SUPPORT_GFX_CGCG | 822 AMD_CG_SUPPORT_GFX_CGLS | 823 AMD_CG_SUPPORT_GFX_3D_CGCG | 824 AMD_CG_SUPPORT_GFX_3D_CGLS | 825 AMD_CG_SUPPORT_MC_MGCG | 826 AMD_CG_SUPPORT_MC_LS | 827 AMD_CG_SUPPORT_GFX_FGCG | 828 AMD_CG_SUPPORT_VCN_MGCG | 829 AMD_CG_SUPPORT_SDMA_MGCG | 830 AMD_CG_SUPPORT_SDMA_LS | 831 AMD_CG_SUPPORT_JPEG_MGCG; 832 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 833 AMD_PG_SUPPORT_VCN | 834 AMD_PG_SUPPORT_VCN_DPG | 835 AMD_PG_SUPPORT_JPEG; 836 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 837 adev->external_rev_id = adev->rev_id + 0x01; 838 break; 839 case IP_VERSION(10, 3, 4): 840 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 841 AMD_CG_SUPPORT_GFX_CGCG | 842 AMD_CG_SUPPORT_GFX_CGLS | 843 AMD_CG_SUPPORT_GFX_3D_CGCG | 844 AMD_CG_SUPPORT_VCN_MGCG | 845 AMD_CG_SUPPORT_JPEG_MGCG | 846 AMD_CG_SUPPORT_MC_MGCG | 847 AMD_CG_SUPPORT_MC_LS | 848 AMD_CG_SUPPORT_HDP_MGCG | 849 AMD_CG_SUPPORT_HDP_LS | 850 AMD_CG_SUPPORT_IH_CG; 851 adev->pg_flags = AMD_PG_SUPPORT_VCN | 852 AMD_PG_SUPPORT_VCN_DPG | 853 AMD_PG_SUPPORT_JPEG | 854 AMD_PG_SUPPORT_ATHUB | 855 AMD_PG_SUPPORT_MMHUB; 856 adev->external_rev_id = adev->rev_id + 0x3c; 857 break; 858 case IP_VERSION(10, 3, 5): 859 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 860 AMD_CG_SUPPORT_GFX_CGCG | 861 AMD_CG_SUPPORT_GFX_CGLS | 862 AMD_CG_SUPPORT_GFX_3D_CGCG | 863 AMD_CG_SUPPORT_MC_MGCG | 864 AMD_CG_SUPPORT_MC_LS | 865 AMD_CG_SUPPORT_HDP_MGCG | 866 AMD_CG_SUPPORT_HDP_LS | 867 AMD_CG_SUPPORT_IH_CG | 868 AMD_CG_SUPPORT_VCN_MGCG; 869 adev->pg_flags = AMD_PG_SUPPORT_VCN | 870 AMD_PG_SUPPORT_VCN_DPG | 871 AMD_PG_SUPPORT_ATHUB | 872 AMD_PG_SUPPORT_MMHUB; 873 adev->external_rev_id = adev->rev_id + 0x46; 874 break; 875 case IP_VERSION(10, 3, 3): 876 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 877 AMD_CG_SUPPORT_GFX_MGLS | 878 AMD_CG_SUPPORT_GFX_CGCG | 879 AMD_CG_SUPPORT_GFX_CGLS | 880 AMD_CG_SUPPORT_GFX_3D_CGCG | 881 AMD_CG_SUPPORT_GFX_3D_CGLS | 882 AMD_CG_SUPPORT_GFX_RLC_LS | 883 AMD_CG_SUPPORT_GFX_CP_LS | 884 AMD_CG_SUPPORT_GFX_FGCG | 885 AMD_CG_SUPPORT_MC_MGCG | 886 AMD_CG_SUPPORT_MC_LS | 887 AMD_CG_SUPPORT_SDMA_LS | 888 AMD_CG_SUPPORT_HDP_MGCG | 889 AMD_CG_SUPPORT_HDP_LS | 890 AMD_CG_SUPPORT_ATHUB_MGCG | 891 AMD_CG_SUPPORT_ATHUB_LS | 892 AMD_CG_SUPPORT_IH_CG | 893 AMD_CG_SUPPORT_VCN_MGCG | 894 AMD_CG_SUPPORT_JPEG_MGCG; 895 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 896 AMD_PG_SUPPORT_VCN | 897 AMD_PG_SUPPORT_VCN_DPG | 898 AMD_PG_SUPPORT_JPEG; 899 if (adev->pdev->device == 0x1681) 900 adev->external_rev_id = 0x20; 901 else 902 adev->external_rev_id = adev->rev_id + 0x01; 903 break; 904 case IP_VERSION(10, 1, 3): 905 adev->cg_flags = 0; 906 adev->pg_flags = 0; 907 adev->external_rev_id = adev->rev_id + 0x82; 908 break; 909 default: 910 /* FIXME: not supported yet */ 911 return -EINVAL; 912 } 913 914 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 915 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 916 AMD_PG_SUPPORT_VCN_DPG | 917 AMD_PG_SUPPORT_JPEG); 918 919 if (amdgpu_sriov_vf(adev)) { 920 amdgpu_virt_init_setting(adev); 921 xgpu_nv_mailbox_set_irq_funcs(adev); 922 } 923 924 return 0; 925 } 926 927 static int nv_common_late_init(void *handle) 928 { 929 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 930 931 if (amdgpu_sriov_vf(adev)) { 932 xgpu_nv_mailbox_get_irq(adev); 933 amdgpu_virt_update_sriov_video_codec(adev, 934 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 935 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); 936 } 937 938 return 0; 939 } 940 941 static int nv_common_sw_init(void *handle) 942 { 943 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 944 945 if (amdgpu_sriov_vf(adev)) 946 xgpu_nv_mailbox_add_irq_id(adev); 947 948 return 0; 949 } 950 951 static int nv_common_sw_fini(void *handle) 952 { 953 return 0; 954 } 955 956 static int nv_common_hw_init(void *handle) 957 { 958 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 959 960 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 961 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 962 963 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 964 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 965 966 /* enable pcie gen2/3 link */ 967 nv_pcie_gen3_enable(adev); 968 /* enable aspm */ 969 nv_program_aspm(adev); 970 /* setup nbio registers */ 971 adev->nbio.funcs->init_registers(adev); 972 /* remap HDP registers to a hole in mmio space, 973 * for the purpose of expose those registers 974 * to process space 975 */ 976 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 977 adev->nbio.funcs->remap_hdp_registers(adev); 978 /* enable the doorbell aperture */ 979 nv_enable_doorbell_aperture(adev, true); 980 981 return 0; 982 } 983 984 static int nv_common_hw_fini(void *handle) 985 { 986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 987 988 /* disable the doorbell aperture */ 989 nv_enable_doorbell_aperture(adev, false); 990 991 return 0; 992 } 993 994 static int nv_common_suspend(void *handle) 995 { 996 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 997 998 return nv_common_hw_fini(adev); 999 } 1000 1001 static int nv_common_resume(void *handle) 1002 { 1003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1004 1005 return nv_common_hw_init(adev); 1006 } 1007 1008 static bool nv_common_is_idle(void *handle) 1009 { 1010 return true; 1011 } 1012 1013 static int nv_common_wait_for_idle(void *handle) 1014 { 1015 return 0; 1016 } 1017 1018 static int nv_common_soft_reset(void *handle) 1019 { 1020 return 0; 1021 } 1022 1023 static int nv_common_set_clockgating_state(void *handle, 1024 enum amd_clockgating_state state) 1025 { 1026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1027 1028 if (amdgpu_sriov_vf(adev)) 1029 return 0; 1030 1031 switch (adev->ip_versions[NBIO_HWIP][0]) { 1032 case IP_VERSION(2, 3, 0): 1033 case IP_VERSION(2, 3, 1): 1034 case IP_VERSION(2, 3, 2): 1035 case IP_VERSION(3, 3, 0): 1036 case IP_VERSION(3, 3, 1): 1037 case IP_VERSION(3, 3, 2): 1038 case IP_VERSION(3, 3, 3): 1039 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1040 state == AMD_CG_STATE_GATE); 1041 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1042 state == AMD_CG_STATE_GATE); 1043 adev->hdp.funcs->update_clock_gating(adev, 1044 state == AMD_CG_STATE_GATE); 1045 adev->smuio.funcs->update_rom_clock_gating(adev, 1046 state == AMD_CG_STATE_GATE); 1047 break; 1048 default: 1049 break; 1050 } 1051 return 0; 1052 } 1053 1054 static int nv_common_set_powergating_state(void *handle, 1055 enum amd_powergating_state state) 1056 { 1057 /* TODO */ 1058 return 0; 1059 } 1060 1061 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1062 { 1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1064 1065 if (amdgpu_sriov_vf(adev)) 1066 *flags = 0; 1067 1068 adev->nbio.funcs->get_clockgating_state(adev, flags); 1069 1070 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1071 1072 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1073 1074 return; 1075 } 1076 1077 static const struct amd_ip_funcs nv_common_ip_funcs = { 1078 .name = "nv_common", 1079 .early_init = nv_common_early_init, 1080 .late_init = nv_common_late_init, 1081 .sw_init = nv_common_sw_init, 1082 .sw_fini = nv_common_sw_fini, 1083 .hw_init = nv_common_hw_init, 1084 .hw_fini = nv_common_hw_fini, 1085 .suspend = nv_common_suspend, 1086 .resume = nv_common_resume, 1087 .is_idle = nv_common_is_idle, 1088 .wait_for_idle = nv_common_wait_for_idle, 1089 .soft_reset = nv_common_soft_reset, 1090 .set_clockgating_state = nv_common_set_clockgating_state, 1091 .set_powergating_state = nv_common_set_powergating_state, 1092 .get_clockgating_state = nv_common_get_clockgating_state, 1093 }; 1094