1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 74 }; 75 76 static const struct amdgpu_video_codecs nv_video_codecs_encode = 77 { 78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 79 .codec_array = nv_video_codecs_encode_array, 80 }; 81 82 /* Navi1x */ 83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 92 }; 93 94 static const struct amdgpu_video_codecs nv_video_codecs_decode = 95 { 96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 97 .codec_array = nv_video_codecs_decode_array, 98 }; 99 100 /* Sienna Cichlid */ 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 102 { 103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 104 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 111 }; 112 113 static const struct amdgpu_video_codecs sc_video_codecs_decode = 114 { 115 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 116 .codec_array = sc_video_codecs_decode_array, 117 }; 118 119 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 120 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 121 { 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 124 }; 125 126 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = 127 { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136 }; 137 138 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 139 { 140 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 141 .codec_array = sriov_sc_video_codecs_encode_array, 142 }; 143 144 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = 145 { 146 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), 147 .codec_array = sriov_sc_video_codecs_decode_array, 148 }; 149 150 /* Beige Goby*/ 151 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 153 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 154 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 155 }; 156 157 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 158 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 159 .codec_array = bg_video_codecs_decode_array, 160 }; 161 162 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 163 .codec_count = 0, 164 .codec_array = NULL, 165 }; 166 167 /* Yellow Carp*/ 168 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 169 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 170 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 171 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 172 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 173 }; 174 175 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 176 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 177 .codec_array = yc_video_codecs_decode_array, 178 }; 179 180 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 181 const struct amdgpu_video_codecs **codecs) 182 { 183 switch (adev->ip_versions[UVD_HWIP][0]) { 184 case IP_VERSION(3, 0, 0): 185 case IP_VERSION(3, 0, 64): 186 if (amdgpu_sriov_vf(adev)) { 187 if (encode) 188 *codecs = &sriov_sc_video_codecs_encode; 189 else 190 *codecs = &sriov_sc_video_codecs_decode; 191 } else { 192 if (encode) 193 *codecs = &nv_video_codecs_encode; 194 else 195 *codecs = &sc_video_codecs_decode; 196 } 197 return 0; 198 case IP_VERSION(3, 0, 16): 199 case IP_VERSION(3, 0, 2): 200 if (encode) 201 *codecs = &nv_video_codecs_encode; 202 else 203 *codecs = &sc_video_codecs_decode; 204 return 0; 205 case IP_VERSION(3, 1, 1): 206 if (encode) 207 *codecs = &nv_video_codecs_encode; 208 else 209 *codecs = &yc_video_codecs_decode; 210 return 0; 211 case IP_VERSION(3, 0, 33): 212 if (encode) 213 *codecs = &bg_video_codecs_encode; 214 else 215 *codecs = &bg_video_codecs_decode; 216 return 0; 217 case IP_VERSION(2, 0, 0): 218 case IP_VERSION(2, 0, 2): 219 if (encode) 220 *codecs = &nv_video_codecs_encode; 221 else 222 *codecs = &nv_video_codecs_decode; 223 return 0; 224 default: 225 return -EINVAL; 226 } 227 } 228 229 /* 230 * Indirect registers accessor 231 */ 232 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 233 { 234 unsigned long address, data; 235 address = adev->nbio.funcs->get_pcie_index_offset(adev); 236 data = adev->nbio.funcs->get_pcie_data_offset(adev); 237 238 return amdgpu_device_indirect_rreg(adev, address, data, reg); 239 } 240 241 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 242 { 243 unsigned long address, data; 244 245 address = adev->nbio.funcs->get_pcie_index_offset(adev); 246 data = adev->nbio.funcs->get_pcie_data_offset(adev); 247 248 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 249 } 250 251 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 252 { 253 unsigned long address, data; 254 address = adev->nbio.funcs->get_pcie_index_offset(adev); 255 data = adev->nbio.funcs->get_pcie_data_offset(adev); 256 257 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 258 } 259 260 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 261 { 262 unsigned long flags, address, data; 263 u32 r; 264 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 265 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 266 267 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 268 WREG32(address, reg * 4); 269 (void)RREG32(address); 270 r = RREG32(data); 271 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 272 return r; 273 } 274 275 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 276 { 277 unsigned long address, data; 278 279 address = adev->nbio.funcs->get_pcie_index_offset(adev); 280 data = adev->nbio.funcs->get_pcie_data_offset(adev); 281 282 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 283 } 284 285 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 286 { 287 unsigned long flags, address, data; 288 289 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 290 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 291 292 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 293 WREG32(address, reg * 4); 294 (void)RREG32(address); 295 WREG32(data, v); 296 (void)RREG32(data); 297 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 298 } 299 300 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 301 { 302 unsigned long flags, address, data; 303 u32 r; 304 305 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 306 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 307 308 spin_lock_irqsave(&adev->didt_idx_lock, flags); 309 WREG32(address, (reg)); 310 r = RREG32(data); 311 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 312 return r; 313 } 314 315 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 316 { 317 unsigned long flags, address, data; 318 319 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 320 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 321 322 spin_lock_irqsave(&adev->didt_idx_lock, flags); 323 WREG32(address, (reg)); 324 WREG32(data, (v)); 325 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 326 } 327 328 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 329 { 330 return adev->nbio.funcs->get_memsize(adev); 331 } 332 333 static u32 nv_get_xclk(struct amdgpu_device *adev) 334 { 335 return adev->clock.spll.reference_freq; 336 } 337 338 339 void nv_grbm_select(struct amdgpu_device *adev, 340 u32 me, u32 pipe, u32 queue, u32 vmid) 341 { 342 u32 grbm_gfx_cntl = 0; 343 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 344 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 345 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 346 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 347 348 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 349 } 350 351 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 352 { 353 /* todo */ 354 } 355 356 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 357 { 358 /* todo */ 359 return false; 360 } 361 362 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 363 u8 *bios, u32 length_bytes) 364 { 365 u32 *dw_ptr; 366 u32 i, length_dw; 367 u32 rom_index_offset, rom_data_offset; 368 369 if (bios == NULL) 370 return false; 371 if (length_bytes == 0) 372 return false; 373 /* APU vbios image is part of sbios image */ 374 if (adev->flags & AMD_IS_APU) 375 return false; 376 377 dw_ptr = (u32 *)bios; 378 length_dw = ALIGN(length_bytes, 4) / 4; 379 380 rom_index_offset = 381 adev->smuio.funcs->get_rom_index_offset(adev); 382 rom_data_offset = 383 adev->smuio.funcs->get_rom_data_offset(adev); 384 385 /* set rom index to 0 */ 386 WREG32(rom_index_offset, 0); 387 /* read out the rom data */ 388 for (i = 0; i < length_dw; i++) 389 dw_ptr[i] = RREG32(rom_data_offset); 390 391 return true; 392 } 393 394 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 395 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 396 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 397 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 398 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 399 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 400 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 401 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 402 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 403 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 404 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 405 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 406 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 407 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 408 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 409 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 410 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 411 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 412 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 413 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 414 }; 415 416 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 417 u32 sh_num, u32 reg_offset) 418 { 419 uint32_t val; 420 421 mutex_lock(&adev->grbm_idx_mutex); 422 if (se_num != 0xffffffff || sh_num != 0xffffffff) 423 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 424 425 val = RREG32(reg_offset); 426 427 if (se_num != 0xffffffff || sh_num != 0xffffffff) 428 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 429 mutex_unlock(&adev->grbm_idx_mutex); 430 return val; 431 } 432 433 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 434 bool indexed, u32 se_num, 435 u32 sh_num, u32 reg_offset) 436 { 437 if (indexed) { 438 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 439 } else { 440 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 441 return adev->gfx.config.gb_addr_config; 442 return RREG32(reg_offset); 443 } 444 } 445 446 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 447 u32 sh_num, u32 reg_offset, u32 *value) 448 { 449 uint32_t i; 450 struct soc15_allowed_register_entry *en; 451 452 *value = 0; 453 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 454 en = &nv_allowed_read_registers[i]; 455 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 456 reg_offset != 457 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 458 continue; 459 460 *value = nv_get_register_value(adev, 461 nv_allowed_read_registers[i].grbm_indexed, 462 se_num, sh_num, reg_offset); 463 return 0; 464 } 465 return -EINVAL; 466 } 467 468 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 469 { 470 u32 i; 471 int ret = 0; 472 473 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 474 475 /* disable BM */ 476 pci_clear_master(adev->pdev); 477 478 amdgpu_device_cache_pci_state(adev->pdev); 479 480 ret = amdgpu_dpm_mode2_reset(adev); 481 if (ret) 482 dev_err(adev->dev, "GPU mode2 reset failed\n"); 483 484 amdgpu_device_load_pci_state(adev->pdev); 485 486 /* wait for asic to come out of reset */ 487 for (i = 0; i < adev->usec_timeout; i++) { 488 u32 memsize = adev->nbio.funcs->get_memsize(adev); 489 490 if (memsize != 0xffffffff) 491 break; 492 udelay(1); 493 } 494 495 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 496 497 return ret; 498 } 499 500 static enum amd_reset_method 501 nv_asic_reset_method(struct amdgpu_device *adev) 502 { 503 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 504 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 505 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 506 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 507 return amdgpu_reset_method; 508 509 if (amdgpu_reset_method != -1) 510 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 511 amdgpu_reset_method); 512 513 switch (adev->ip_versions[MP1_HWIP][0]) { 514 case IP_VERSION(11, 5, 0): 515 case IP_VERSION(13, 0, 1): 516 case IP_VERSION(13, 0, 3): 517 return AMD_RESET_METHOD_MODE2; 518 case IP_VERSION(11, 0, 7): 519 case IP_VERSION(11, 0, 11): 520 case IP_VERSION(11, 0, 12): 521 case IP_VERSION(11, 0, 13): 522 return AMD_RESET_METHOD_MODE1; 523 default: 524 if (amdgpu_dpm_is_baco_supported(adev)) 525 return AMD_RESET_METHOD_BACO; 526 else 527 return AMD_RESET_METHOD_MODE1; 528 } 529 } 530 531 static int nv_asic_reset(struct amdgpu_device *adev) 532 { 533 int ret = 0; 534 535 switch (nv_asic_reset_method(adev)) { 536 case AMD_RESET_METHOD_PCI: 537 dev_info(adev->dev, "PCI reset\n"); 538 ret = amdgpu_device_pci_reset(adev); 539 break; 540 case AMD_RESET_METHOD_BACO: 541 dev_info(adev->dev, "BACO reset\n"); 542 ret = amdgpu_dpm_baco_reset(adev); 543 break; 544 case AMD_RESET_METHOD_MODE2: 545 dev_info(adev->dev, "MODE2 reset\n"); 546 ret = nv_asic_mode2_reset(adev); 547 break; 548 default: 549 dev_info(adev->dev, "MODE1 reset\n"); 550 ret = amdgpu_device_mode1_reset(adev); 551 break; 552 } 553 554 return ret; 555 } 556 557 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 558 { 559 /* todo */ 560 return 0; 561 } 562 563 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 564 { 565 /* todo */ 566 return 0; 567 } 568 569 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 570 { 571 if (pci_is_root_bus(adev->pdev->bus)) 572 return; 573 574 if (amdgpu_pcie_gen2 == 0) 575 return; 576 577 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 578 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 579 return; 580 581 /* todo */ 582 } 583 584 static void nv_program_aspm(struct amdgpu_device *adev) 585 { 586 if (!amdgpu_aspm) 587 return; 588 589 if (!(adev->flags & AMD_IS_APU) && 590 (adev->nbio.funcs->program_aspm)) 591 adev->nbio.funcs->program_aspm(adev); 592 593 } 594 595 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 596 bool enable) 597 { 598 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 599 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 600 } 601 602 const struct amdgpu_ip_block_version nv_common_ip_block = 603 { 604 .type = AMD_IP_BLOCK_TYPE_COMMON, 605 .major = 1, 606 .minor = 0, 607 .rev = 0, 608 .funcs = &nv_common_ip_funcs, 609 }; 610 611 void nv_set_virt_ops(struct amdgpu_device *adev) 612 { 613 adev->virt.ops = &xgpu_nv_virt_ops; 614 } 615 616 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 617 { 618 return adev->nbio.funcs->get_rev_id(adev); 619 } 620 621 static bool nv_need_full_reset(struct amdgpu_device *adev) 622 { 623 return true; 624 } 625 626 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 627 { 628 u32 sol_reg; 629 630 if (adev->flags & AMD_IS_APU) 631 return false; 632 633 /* Check sOS sign of life register to confirm sys driver and sOS 634 * are already been loaded. 635 */ 636 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 637 if (sol_reg) 638 return true; 639 640 return false; 641 } 642 643 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 644 { 645 646 /* TODO 647 * dummy implement for pcie_replay_count sysfs interface 648 * */ 649 650 return 0; 651 } 652 653 static void nv_init_doorbell_index(struct amdgpu_device *adev) 654 { 655 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 656 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 657 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 658 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 659 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 660 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 661 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 662 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 663 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 664 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 665 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 666 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 667 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 668 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 669 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 670 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 671 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 672 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 673 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 674 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 675 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 676 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 677 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 678 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 679 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 680 681 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 682 adev->doorbell_index.sdma_doorbell_range = 20; 683 } 684 685 static void nv_pre_asic_init(struct amdgpu_device *adev) 686 { 687 } 688 689 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 690 bool enter) 691 { 692 if (enter) 693 amdgpu_gfx_rlc_enter_safe_mode(adev); 694 else 695 amdgpu_gfx_rlc_exit_safe_mode(adev); 696 697 if (adev->gfx.funcs->update_perfmon_mgcg) 698 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 699 700 if (!(adev->flags & AMD_IS_APU) && 701 (adev->nbio.funcs->enable_aspm)) 702 adev->nbio.funcs->enable_aspm(adev, !enter); 703 704 return 0; 705 } 706 707 static const struct amdgpu_asic_funcs nv_asic_funcs = 708 { 709 .read_disabled_bios = &nv_read_disabled_bios, 710 .read_bios_from_rom = &nv_read_bios_from_rom, 711 .read_register = &nv_read_register, 712 .reset = &nv_asic_reset, 713 .reset_method = &nv_asic_reset_method, 714 .set_vga_state = &nv_vga_set_state, 715 .get_xclk = &nv_get_xclk, 716 .set_uvd_clocks = &nv_set_uvd_clocks, 717 .set_vce_clocks = &nv_set_vce_clocks, 718 .get_config_memsize = &nv_get_config_memsize, 719 .init_doorbell_index = &nv_init_doorbell_index, 720 .need_full_reset = &nv_need_full_reset, 721 .need_reset_on_init = &nv_need_reset_on_init, 722 .get_pcie_replay_count = &nv_get_pcie_replay_count, 723 .supports_baco = &amdgpu_dpm_is_baco_supported, 724 .pre_asic_init = &nv_pre_asic_init, 725 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 726 .query_video_codecs = &nv_query_video_codecs, 727 }; 728 729 static int nv_common_early_init(void *handle) 730 { 731 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 732 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 733 734 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 735 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 736 adev->smc_rreg = NULL; 737 adev->smc_wreg = NULL; 738 adev->pcie_rreg = &nv_pcie_rreg; 739 adev->pcie_wreg = &nv_pcie_wreg; 740 adev->pcie_rreg64 = &nv_pcie_rreg64; 741 adev->pcie_wreg64 = &nv_pcie_wreg64; 742 adev->pciep_rreg = &nv_pcie_port_rreg; 743 adev->pciep_wreg = &nv_pcie_port_wreg; 744 745 /* TODO: will add them during VCN v2 implementation */ 746 adev->uvd_ctx_rreg = NULL; 747 adev->uvd_ctx_wreg = NULL; 748 749 adev->didt_rreg = &nv_didt_rreg; 750 adev->didt_wreg = &nv_didt_wreg; 751 752 adev->asic_funcs = &nv_asic_funcs; 753 754 adev->rev_id = nv_get_rev_id(adev); 755 adev->external_rev_id = 0xff; 756 /* TODO: split the GC and PG flags based on the relevant IP version for which 757 * they are relevant. 758 */ 759 switch (adev->ip_versions[GC_HWIP][0]) { 760 case IP_VERSION(10, 1, 10): 761 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 762 AMD_CG_SUPPORT_GFX_CGCG | 763 AMD_CG_SUPPORT_IH_CG | 764 AMD_CG_SUPPORT_HDP_MGCG | 765 AMD_CG_SUPPORT_HDP_LS | 766 AMD_CG_SUPPORT_SDMA_MGCG | 767 AMD_CG_SUPPORT_SDMA_LS | 768 AMD_CG_SUPPORT_MC_MGCG | 769 AMD_CG_SUPPORT_MC_LS | 770 AMD_CG_SUPPORT_ATHUB_MGCG | 771 AMD_CG_SUPPORT_ATHUB_LS | 772 AMD_CG_SUPPORT_VCN_MGCG | 773 AMD_CG_SUPPORT_JPEG_MGCG | 774 AMD_CG_SUPPORT_BIF_MGCG | 775 AMD_CG_SUPPORT_BIF_LS; 776 adev->pg_flags = AMD_PG_SUPPORT_VCN | 777 AMD_PG_SUPPORT_VCN_DPG | 778 AMD_PG_SUPPORT_JPEG | 779 AMD_PG_SUPPORT_ATHUB; 780 adev->external_rev_id = adev->rev_id + 0x1; 781 break; 782 case IP_VERSION(10, 1, 1): 783 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 784 AMD_CG_SUPPORT_GFX_CGCG | 785 AMD_CG_SUPPORT_IH_CG | 786 AMD_CG_SUPPORT_HDP_MGCG | 787 AMD_CG_SUPPORT_HDP_LS | 788 AMD_CG_SUPPORT_SDMA_MGCG | 789 AMD_CG_SUPPORT_SDMA_LS | 790 AMD_CG_SUPPORT_MC_MGCG | 791 AMD_CG_SUPPORT_MC_LS | 792 AMD_CG_SUPPORT_ATHUB_MGCG | 793 AMD_CG_SUPPORT_ATHUB_LS | 794 AMD_CG_SUPPORT_VCN_MGCG | 795 AMD_CG_SUPPORT_JPEG_MGCG | 796 AMD_CG_SUPPORT_BIF_MGCG | 797 AMD_CG_SUPPORT_BIF_LS; 798 adev->pg_flags = AMD_PG_SUPPORT_VCN | 799 AMD_PG_SUPPORT_JPEG | 800 AMD_PG_SUPPORT_VCN_DPG; 801 adev->external_rev_id = adev->rev_id + 20; 802 break; 803 case IP_VERSION(10, 1, 2): 804 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 805 AMD_CG_SUPPORT_GFX_MGLS | 806 AMD_CG_SUPPORT_GFX_CGCG | 807 AMD_CG_SUPPORT_GFX_CP_LS | 808 AMD_CG_SUPPORT_GFX_RLC_LS | 809 AMD_CG_SUPPORT_IH_CG | 810 AMD_CG_SUPPORT_HDP_MGCG | 811 AMD_CG_SUPPORT_HDP_LS | 812 AMD_CG_SUPPORT_SDMA_MGCG | 813 AMD_CG_SUPPORT_SDMA_LS | 814 AMD_CG_SUPPORT_MC_MGCG | 815 AMD_CG_SUPPORT_MC_LS | 816 AMD_CG_SUPPORT_ATHUB_MGCG | 817 AMD_CG_SUPPORT_ATHUB_LS | 818 AMD_CG_SUPPORT_VCN_MGCG | 819 AMD_CG_SUPPORT_JPEG_MGCG; 820 adev->pg_flags = AMD_PG_SUPPORT_VCN | 821 AMD_PG_SUPPORT_VCN_DPG | 822 AMD_PG_SUPPORT_JPEG | 823 AMD_PG_SUPPORT_ATHUB; 824 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 825 * as a consequence, the rev_id and external_rev_id are wrong. 826 * workaround it by hardcoding rev_id to 0 (default value). 827 */ 828 if (amdgpu_sriov_vf(adev)) 829 adev->rev_id = 0; 830 adev->external_rev_id = adev->rev_id + 0xa; 831 break; 832 case IP_VERSION(10, 3, 0): 833 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 834 AMD_CG_SUPPORT_GFX_CGCG | 835 AMD_CG_SUPPORT_GFX_CGLS | 836 AMD_CG_SUPPORT_GFX_3D_CGCG | 837 AMD_CG_SUPPORT_MC_MGCG | 838 AMD_CG_SUPPORT_VCN_MGCG | 839 AMD_CG_SUPPORT_JPEG_MGCG | 840 AMD_CG_SUPPORT_HDP_MGCG | 841 AMD_CG_SUPPORT_HDP_LS | 842 AMD_CG_SUPPORT_IH_CG | 843 AMD_CG_SUPPORT_MC_LS; 844 adev->pg_flags = AMD_PG_SUPPORT_VCN | 845 AMD_PG_SUPPORT_VCN_DPG | 846 AMD_PG_SUPPORT_JPEG | 847 AMD_PG_SUPPORT_ATHUB | 848 AMD_PG_SUPPORT_MMHUB; 849 if (amdgpu_sriov_vf(adev)) { 850 /* hypervisor control CG and PG enablement */ 851 adev->cg_flags = 0; 852 adev->pg_flags = 0; 853 } 854 adev->external_rev_id = adev->rev_id + 0x28; 855 break; 856 case IP_VERSION(10, 3, 2): 857 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 858 AMD_CG_SUPPORT_GFX_CGCG | 859 AMD_CG_SUPPORT_GFX_CGLS | 860 AMD_CG_SUPPORT_GFX_3D_CGCG | 861 AMD_CG_SUPPORT_VCN_MGCG | 862 AMD_CG_SUPPORT_JPEG_MGCG | 863 AMD_CG_SUPPORT_MC_MGCG | 864 AMD_CG_SUPPORT_MC_LS | 865 AMD_CG_SUPPORT_HDP_MGCG | 866 AMD_CG_SUPPORT_HDP_LS | 867 AMD_CG_SUPPORT_IH_CG; 868 adev->pg_flags = AMD_PG_SUPPORT_VCN | 869 AMD_PG_SUPPORT_VCN_DPG | 870 AMD_PG_SUPPORT_JPEG | 871 AMD_PG_SUPPORT_ATHUB | 872 AMD_PG_SUPPORT_MMHUB; 873 adev->external_rev_id = adev->rev_id + 0x32; 874 break; 875 case IP_VERSION(10, 3, 1): 876 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 877 AMD_CG_SUPPORT_GFX_MGLS | 878 AMD_CG_SUPPORT_GFX_CP_LS | 879 AMD_CG_SUPPORT_GFX_RLC_LS | 880 AMD_CG_SUPPORT_GFX_CGCG | 881 AMD_CG_SUPPORT_GFX_CGLS | 882 AMD_CG_SUPPORT_GFX_3D_CGCG | 883 AMD_CG_SUPPORT_GFX_3D_CGLS | 884 AMD_CG_SUPPORT_MC_MGCG | 885 AMD_CG_SUPPORT_MC_LS | 886 AMD_CG_SUPPORT_GFX_FGCG | 887 AMD_CG_SUPPORT_VCN_MGCG | 888 AMD_CG_SUPPORT_SDMA_MGCG | 889 AMD_CG_SUPPORT_SDMA_LS | 890 AMD_CG_SUPPORT_JPEG_MGCG; 891 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 892 AMD_PG_SUPPORT_VCN | 893 AMD_PG_SUPPORT_VCN_DPG | 894 AMD_PG_SUPPORT_JPEG; 895 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 896 adev->external_rev_id = adev->rev_id + 0x01; 897 break; 898 case IP_VERSION(10, 3, 4): 899 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 900 AMD_CG_SUPPORT_GFX_CGCG | 901 AMD_CG_SUPPORT_GFX_CGLS | 902 AMD_CG_SUPPORT_GFX_3D_CGCG | 903 AMD_CG_SUPPORT_VCN_MGCG | 904 AMD_CG_SUPPORT_JPEG_MGCG | 905 AMD_CG_SUPPORT_MC_MGCG | 906 AMD_CG_SUPPORT_MC_LS | 907 AMD_CG_SUPPORT_HDP_MGCG | 908 AMD_CG_SUPPORT_HDP_LS | 909 AMD_CG_SUPPORT_IH_CG; 910 adev->pg_flags = AMD_PG_SUPPORT_VCN | 911 AMD_PG_SUPPORT_VCN_DPG | 912 AMD_PG_SUPPORT_JPEG | 913 AMD_PG_SUPPORT_ATHUB | 914 AMD_PG_SUPPORT_MMHUB; 915 adev->external_rev_id = adev->rev_id + 0x3c; 916 break; 917 case IP_VERSION(10, 3, 5): 918 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 919 AMD_CG_SUPPORT_GFX_CGCG | 920 AMD_CG_SUPPORT_GFX_CGLS | 921 AMD_CG_SUPPORT_GFX_3D_CGCG | 922 AMD_CG_SUPPORT_MC_MGCG | 923 AMD_CG_SUPPORT_MC_LS | 924 AMD_CG_SUPPORT_HDP_MGCG | 925 AMD_CG_SUPPORT_HDP_LS | 926 AMD_CG_SUPPORT_IH_CG | 927 AMD_CG_SUPPORT_VCN_MGCG; 928 adev->pg_flags = AMD_PG_SUPPORT_VCN | 929 AMD_PG_SUPPORT_VCN_DPG | 930 AMD_PG_SUPPORT_ATHUB | 931 AMD_PG_SUPPORT_MMHUB; 932 adev->external_rev_id = adev->rev_id + 0x46; 933 break; 934 case IP_VERSION(10, 3, 3): 935 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 936 AMD_CG_SUPPORT_GFX_MGLS | 937 AMD_CG_SUPPORT_GFX_CGCG | 938 AMD_CG_SUPPORT_GFX_CGLS | 939 AMD_CG_SUPPORT_GFX_3D_CGCG | 940 AMD_CG_SUPPORT_GFX_3D_CGLS | 941 AMD_CG_SUPPORT_GFX_RLC_LS | 942 AMD_CG_SUPPORT_GFX_CP_LS | 943 AMD_CG_SUPPORT_GFX_FGCG | 944 AMD_CG_SUPPORT_MC_MGCG | 945 AMD_CG_SUPPORT_MC_LS | 946 AMD_CG_SUPPORT_SDMA_LS | 947 AMD_CG_SUPPORT_HDP_MGCG | 948 AMD_CG_SUPPORT_HDP_LS | 949 AMD_CG_SUPPORT_ATHUB_MGCG | 950 AMD_CG_SUPPORT_ATHUB_LS | 951 AMD_CG_SUPPORT_IH_CG | 952 AMD_CG_SUPPORT_VCN_MGCG | 953 AMD_CG_SUPPORT_JPEG_MGCG; 954 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 955 AMD_PG_SUPPORT_VCN | 956 AMD_PG_SUPPORT_VCN_DPG | 957 AMD_PG_SUPPORT_JPEG; 958 if (adev->pdev->device == 0x1681) 959 adev->external_rev_id = 0x20; 960 else 961 adev->external_rev_id = adev->rev_id + 0x01; 962 break; 963 case IP_VERSION(10, 1, 3): 964 adev->cg_flags = 0; 965 adev->pg_flags = 0; 966 adev->external_rev_id = adev->rev_id + 0x82; 967 break; 968 default: 969 /* FIXME: not supported yet */ 970 return -EINVAL; 971 } 972 973 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 974 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 975 AMD_PG_SUPPORT_VCN_DPG | 976 AMD_PG_SUPPORT_JPEG); 977 978 if (amdgpu_sriov_vf(adev)) { 979 amdgpu_virt_init_setting(adev); 980 xgpu_nv_mailbox_set_irq_funcs(adev); 981 } 982 983 return 0; 984 } 985 986 static int nv_common_late_init(void *handle) 987 { 988 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 989 990 if (amdgpu_sriov_vf(adev)) { 991 xgpu_nv_mailbox_get_irq(adev); 992 amdgpu_virt_update_sriov_video_codec(adev, 993 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 994 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); 995 } 996 997 return 0; 998 } 999 1000 static int nv_common_sw_init(void *handle) 1001 { 1002 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1003 1004 if (amdgpu_sriov_vf(adev)) 1005 xgpu_nv_mailbox_add_irq_id(adev); 1006 1007 return 0; 1008 } 1009 1010 static int nv_common_sw_fini(void *handle) 1011 { 1012 return 0; 1013 } 1014 1015 static int nv_common_hw_init(void *handle) 1016 { 1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1018 1019 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 1020 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 1021 1022 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1023 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1024 1025 /* enable pcie gen2/3 link */ 1026 nv_pcie_gen3_enable(adev); 1027 /* enable aspm */ 1028 nv_program_aspm(adev); 1029 /* setup nbio registers */ 1030 adev->nbio.funcs->init_registers(adev); 1031 /* remap HDP registers to a hole in mmio space, 1032 * for the purpose of expose those registers 1033 * to process space 1034 */ 1035 if (adev->nbio.funcs->remap_hdp_registers) 1036 adev->nbio.funcs->remap_hdp_registers(adev); 1037 /* enable the doorbell aperture */ 1038 nv_enable_doorbell_aperture(adev, true); 1039 1040 return 0; 1041 } 1042 1043 static int nv_common_hw_fini(void *handle) 1044 { 1045 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1046 1047 /* disable the doorbell aperture */ 1048 nv_enable_doorbell_aperture(adev, false); 1049 1050 return 0; 1051 } 1052 1053 static int nv_common_suspend(void *handle) 1054 { 1055 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1056 1057 return nv_common_hw_fini(adev); 1058 } 1059 1060 static int nv_common_resume(void *handle) 1061 { 1062 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1063 1064 return nv_common_hw_init(adev); 1065 } 1066 1067 static bool nv_common_is_idle(void *handle) 1068 { 1069 return true; 1070 } 1071 1072 static int nv_common_wait_for_idle(void *handle) 1073 { 1074 return 0; 1075 } 1076 1077 static int nv_common_soft_reset(void *handle) 1078 { 1079 return 0; 1080 } 1081 1082 static int nv_common_set_clockgating_state(void *handle, 1083 enum amd_clockgating_state state) 1084 { 1085 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1086 1087 if (amdgpu_sriov_vf(adev)) 1088 return 0; 1089 1090 switch (adev->ip_versions[NBIO_HWIP][0]) { 1091 case IP_VERSION(2, 3, 0): 1092 case IP_VERSION(2, 3, 1): 1093 case IP_VERSION(2, 3, 2): 1094 case IP_VERSION(3, 3, 0): 1095 case IP_VERSION(3, 3, 1): 1096 case IP_VERSION(3, 3, 2): 1097 case IP_VERSION(3, 3, 3): 1098 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1099 state == AMD_CG_STATE_GATE); 1100 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1101 state == AMD_CG_STATE_GATE); 1102 adev->hdp.funcs->update_clock_gating(adev, 1103 state == AMD_CG_STATE_GATE); 1104 adev->smuio.funcs->update_rom_clock_gating(adev, 1105 state == AMD_CG_STATE_GATE); 1106 break; 1107 default: 1108 break; 1109 } 1110 return 0; 1111 } 1112 1113 static int nv_common_set_powergating_state(void *handle, 1114 enum amd_powergating_state state) 1115 { 1116 /* TODO */ 1117 return 0; 1118 } 1119 1120 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1121 { 1122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1123 1124 if (amdgpu_sriov_vf(adev)) 1125 *flags = 0; 1126 1127 adev->nbio.funcs->get_clockgating_state(adev, flags); 1128 1129 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1130 1131 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1132 1133 return; 1134 } 1135 1136 static const struct amd_ip_funcs nv_common_ip_funcs = { 1137 .name = "nv_common", 1138 .early_init = nv_common_early_init, 1139 .late_init = nv_common_late_init, 1140 .sw_init = nv_common_sw_init, 1141 .sw_fini = nv_common_sw_fini, 1142 .hw_init = nv_common_hw_init, 1143 .hw_fini = nv_common_hw_fini, 1144 .suspend = nv_common_suspend, 1145 .resume = nv_common_resume, 1146 .is_idle = nv_common_is_idle, 1147 .wait_for_idle = nv_common_wait_for_idle, 1148 .soft_reset = nv_common_soft_reset, 1149 .set_clockgating_state = nv_common_set_clockgating_state, 1150 .set_powergating_state = nv_common_set_powergating_state, 1151 .get_clockgating_state = nv_common_get_clockgating_state, 1152 }; 1153