1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "hdp/hdp_5_0_0_sh_mask.h" 43 #include "smuio/smuio_11_0_0_offset.h" 44 45 #include "soc15.h" 46 #include "soc15_common.h" 47 #include "gmc_v10_0.h" 48 #include "gfxhub_v2_0.h" 49 #include "mmhub_v2_0.h" 50 #include "nbio_v2_3.h" 51 #include "nv.h" 52 #include "navi10_ih.h" 53 #include "gfx_v10_0.h" 54 #include "sdma_v5_0.h" 55 #include "vcn_v2_0.h" 56 #include "jpeg_v2_0.h" 57 #include "dce_virtual.h" 58 #include "mes_v10_1.h" 59 #include "mxgpu_nv.h" 60 61 static const struct amd_ip_funcs nv_common_ip_funcs; 62 63 /* 64 * Indirect registers accessor 65 */ 66 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 67 { 68 unsigned long flags, address, data; 69 u32 r; 70 address = adev->nbio.funcs->get_pcie_index_offset(adev); 71 data = adev->nbio.funcs->get_pcie_data_offset(adev); 72 73 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 74 WREG32(address, reg); 75 (void)RREG32(address); 76 r = RREG32(data); 77 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 78 return r; 79 } 80 81 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 82 { 83 unsigned long flags, address, data; 84 85 address = adev->nbio.funcs->get_pcie_index_offset(adev); 86 data = adev->nbio.funcs->get_pcie_data_offset(adev); 87 88 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 89 WREG32(address, reg); 90 (void)RREG32(address); 91 WREG32(data, v); 92 (void)RREG32(data); 93 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 94 } 95 96 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 97 { 98 unsigned long flags, address, data; 99 u32 r; 100 101 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 102 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 103 104 spin_lock_irqsave(&adev->didt_idx_lock, flags); 105 WREG32(address, (reg)); 106 r = RREG32(data); 107 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 108 return r; 109 } 110 111 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 112 { 113 unsigned long flags, address, data; 114 115 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 116 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 117 118 spin_lock_irqsave(&adev->didt_idx_lock, flags); 119 WREG32(address, (reg)); 120 WREG32(data, (v)); 121 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 122 } 123 124 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 125 { 126 return adev->nbio.funcs->get_memsize(adev); 127 } 128 129 static u32 nv_get_xclk(struct amdgpu_device *adev) 130 { 131 return adev->clock.spll.reference_freq; 132 } 133 134 135 void nv_grbm_select(struct amdgpu_device *adev, 136 u32 me, u32 pipe, u32 queue, u32 vmid) 137 { 138 u32 grbm_gfx_cntl = 0; 139 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 140 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 141 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 142 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 143 144 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 145 } 146 147 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 148 { 149 /* todo */ 150 } 151 152 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 153 { 154 /* todo */ 155 return false; 156 } 157 158 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 159 u8 *bios, u32 length_bytes) 160 { 161 u32 *dw_ptr; 162 u32 i, length_dw; 163 164 if (bios == NULL) 165 return false; 166 if (length_bytes == 0) 167 return false; 168 /* APU vbios image is part of sbios image */ 169 if (adev->flags & AMD_IS_APU) 170 return false; 171 172 dw_ptr = (u32 *)bios; 173 length_dw = ALIGN(length_bytes, 4) / 4; 174 175 /* set rom index to 0 */ 176 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 177 /* read out the rom data */ 178 for (i = 0; i < length_dw; i++) 179 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 180 181 return true; 182 } 183 184 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 185 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 186 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 187 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 188 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 189 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 190 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 191 #if 0 /* TODO: will set it when SDMA header is available */ 192 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 193 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 194 #endif 195 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 196 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 197 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 198 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 199 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 200 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 201 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 202 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 203 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 204 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 205 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 206 }; 207 208 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 209 u32 sh_num, u32 reg_offset) 210 { 211 uint32_t val; 212 213 mutex_lock(&adev->grbm_idx_mutex); 214 if (se_num != 0xffffffff || sh_num != 0xffffffff) 215 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 216 217 val = RREG32(reg_offset); 218 219 if (se_num != 0xffffffff || sh_num != 0xffffffff) 220 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 221 mutex_unlock(&adev->grbm_idx_mutex); 222 return val; 223 } 224 225 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 226 bool indexed, u32 se_num, 227 u32 sh_num, u32 reg_offset) 228 { 229 if (indexed) { 230 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 231 } else { 232 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 233 return adev->gfx.config.gb_addr_config; 234 return RREG32(reg_offset); 235 } 236 } 237 238 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 239 u32 sh_num, u32 reg_offset, u32 *value) 240 { 241 uint32_t i; 242 struct soc15_allowed_register_entry *en; 243 244 *value = 0; 245 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 246 en = &nv_allowed_read_registers[i]; 247 if (reg_offset != 248 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 249 continue; 250 251 *value = nv_get_register_value(adev, 252 nv_allowed_read_registers[i].grbm_indexed, 253 se_num, sh_num, reg_offset); 254 return 0; 255 } 256 return -EINVAL; 257 } 258 259 #if 0 260 static void nv_gpu_pci_config_reset(struct amdgpu_device *adev) 261 { 262 u32 i; 263 264 dev_info(adev->dev, "GPU pci config reset\n"); 265 266 /* disable BM */ 267 pci_clear_master(adev->pdev); 268 /* reset */ 269 amdgpu_pci_config_reset(adev); 270 271 udelay(100); 272 273 /* wait for asic to come out of reset */ 274 for (i = 0; i < adev->usec_timeout; i++) { 275 u32 memsize = nbio_v2_3_get_memsize(adev); 276 if (memsize != 0xffffffff) 277 break; 278 udelay(1); 279 } 280 281 } 282 #endif 283 284 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 285 { 286 u32 i; 287 int ret = 0; 288 289 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 290 291 dev_info(adev->dev, "GPU mode1 reset\n"); 292 293 /* disable BM */ 294 pci_clear_master(adev->pdev); 295 296 pci_save_state(adev->pdev); 297 298 ret = psp_gpu_reset(adev); 299 if (ret) 300 dev_err(adev->dev, "GPU mode1 reset failed\n"); 301 302 pci_restore_state(adev->pdev); 303 304 /* wait for asic to come out of reset */ 305 for (i = 0; i < adev->usec_timeout; i++) { 306 u32 memsize = adev->nbio.funcs->get_memsize(adev); 307 308 if (memsize != 0xffffffff) 309 break; 310 udelay(1); 311 } 312 313 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 314 315 return ret; 316 } 317 318 static bool nv_asic_supports_baco(struct amdgpu_device *adev) 319 { 320 struct smu_context *smu = &adev->smu; 321 322 if (smu_baco_is_support(smu)) 323 return true; 324 else 325 return false; 326 } 327 328 static enum amd_reset_method 329 nv_asic_reset_method(struct amdgpu_device *adev) 330 { 331 struct smu_context *smu = &adev->smu; 332 333 if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu)) 334 return AMD_RESET_METHOD_BACO; 335 else 336 return AMD_RESET_METHOD_MODE1; 337 } 338 339 static int nv_asic_reset(struct amdgpu_device *adev) 340 { 341 342 /* FIXME: it doesn't work since vega10 */ 343 #if 0 344 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 345 346 nv_gpu_pci_config_reset(adev); 347 348 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 349 #endif 350 int ret = 0; 351 struct smu_context *smu = &adev->smu; 352 353 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 354 ret = smu_baco_enter(smu); 355 if (ret) 356 return ret; 357 ret = smu_baco_exit(smu); 358 if (ret) 359 return ret; 360 } else { 361 ret = nv_asic_mode1_reset(adev); 362 } 363 364 return ret; 365 } 366 367 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 368 { 369 /* todo */ 370 return 0; 371 } 372 373 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 374 { 375 /* todo */ 376 return 0; 377 } 378 379 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 380 { 381 if (pci_is_root_bus(adev->pdev->bus)) 382 return; 383 384 if (amdgpu_pcie_gen2 == 0) 385 return; 386 387 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 388 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 389 return; 390 391 /* todo */ 392 } 393 394 static void nv_program_aspm(struct amdgpu_device *adev) 395 { 396 397 if (amdgpu_aspm == 0) 398 return; 399 400 /* todo */ 401 } 402 403 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 404 bool enable) 405 { 406 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 407 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 408 } 409 410 static const struct amdgpu_ip_block_version nv_common_ip_block = 411 { 412 .type = AMD_IP_BLOCK_TYPE_COMMON, 413 .major = 1, 414 .minor = 0, 415 .rev = 0, 416 .funcs = &nv_common_ip_funcs, 417 }; 418 419 static int nv_reg_base_init(struct amdgpu_device *adev) 420 { 421 int r; 422 423 if (amdgpu_discovery) { 424 r = amdgpu_discovery_reg_base_init(adev); 425 if (r) { 426 DRM_WARN("failed to init reg base from ip discovery table, " 427 "fallback to legacy init method\n"); 428 goto legacy_init; 429 } 430 431 return 0; 432 } 433 434 legacy_init: 435 switch (adev->asic_type) { 436 case CHIP_NAVI10: 437 navi10_reg_base_init(adev); 438 break; 439 case CHIP_NAVI14: 440 navi14_reg_base_init(adev); 441 break; 442 case CHIP_NAVI12: 443 navi12_reg_base_init(adev); 444 break; 445 default: 446 return -EINVAL; 447 } 448 449 return 0; 450 } 451 452 int nv_set_ip_blocks(struct amdgpu_device *adev) 453 { 454 int r; 455 456 adev->nbio.funcs = &nbio_v2_3_funcs; 457 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 458 459 if (amdgpu_sriov_vf(adev)) { 460 adev->virt.ops = &xgpu_nv_virt_ops; 461 /* try send GPU_INIT_DATA request to host */ 462 amdgpu_virt_request_init_data(adev); 463 } 464 465 /* Set IP register base before any HW register access */ 466 r = nv_reg_base_init(adev); 467 if (r) 468 return r; 469 470 switch (adev->asic_type) { 471 case CHIP_NAVI10: 472 case CHIP_NAVI14: 473 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 474 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 475 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 476 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 477 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 478 !amdgpu_sriov_vf(adev)) 479 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 480 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 481 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 482 #if defined(CONFIG_DRM_AMD_DC) 483 else if (amdgpu_device_has_dc_support(adev)) 484 amdgpu_device_ip_block_add(adev, &dm_ip_block); 485 #endif 486 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 487 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 488 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 489 !amdgpu_sriov_vf(adev)) 490 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 491 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 492 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 493 if (adev->enable_mes) 494 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 495 break; 496 case CHIP_NAVI12: 497 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 498 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 499 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 500 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 501 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 502 !amdgpu_sriov_vf(adev)) 503 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 504 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 505 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 506 #if defined(CONFIG_DRM_AMD_DC) 507 else if (amdgpu_device_has_dc_support(adev)) 508 amdgpu_device_ip_block_add(adev, &dm_ip_block); 509 #endif 510 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 511 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 512 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 513 !amdgpu_sriov_vf(adev)) 514 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 515 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 516 if (!amdgpu_sriov_vf(adev)) 517 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 518 break; 519 default: 520 return -EINVAL; 521 } 522 523 return 0; 524 } 525 526 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 527 { 528 return adev->nbio.funcs->get_rev_id(adev); 529 } 530 531 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 532 { 533 adev->nbio.funcs->hdp_flush(adev, ring); 534 } 535 536 static void nv_invalidate_hdp(struct amdgpu_device *adev, 537 struct amdgpu_ring *ring) 538 { 539 if (!ring || !ring->funcs->emit_wreg) { 540 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 541 } else { 542 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 543 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 544 } 545 } 546 547 static bool nv_need_full_reset(struct amdgpu_device *adev) 548 { 549 return true; 550 } 551 552 static void nv_get_pcie_usage(struct amdgpu_device *adev, 553 uint64_t *count0, 554 uint64_t *count1) 555 { 556 /*TODO*/ 557 } 558 559 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 560 { 561 #if 0 562 u32 sol_reg; 563 564 if (adev->flags & AMD_IS_APU) 565 return false; 566 567 /* Check sOS sign of life register to confirm sys driver and sOS 568 * are already been loaded. 569 */ 570 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 571 if (sol_reg) 572 return true; 573 #endif 574 /* TODO: re-enable it when mode1 reset is functional */ 575 return false; 576 } 577 578 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 579 { 580 581 /* TODO 582 * dummy implement for pcie_replay_count sysfs interface 583 * */ 584 585 return 0; 586 } 587 588 static void nv_init_doorbell_index(struct amdgpu_device *adev) 589 { 590 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 591 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 592 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 593 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 594 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 595 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 596 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 597 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 598 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 599 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 600 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 601 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 602 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 603 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 604 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 605 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 606 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 607 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 608 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 609 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 610 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 611 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 612 613 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 614 adev->doorbell_index.sdma_doorbell_range = 20; 615 } 616 617 static const struct amdgpu_asic_funcs nv_asic_funcs = 618 { 619 .read_disabled_bios = &nv_read_disabled_bios, 620 .read_bios_from_rom = &nv_read_bios_from_rom, 621 .read_register = &nv_read_register, 622 .reset = &nv_asic_reset, 623 .reset_method = &nv_asic_reset_method, 624 .set_vga_state = &nv_vga_set_state, 625 .get_xclk = &nv_get_xclk, 626 .set_uvd_clocks = &nv_set_uvd_clocks, 627 .set_vce_clocks = &nv_set_vce_clocks, 628 .get_config_memsize = &nv_get_config_memsize, 629 .flush_hdp = &nv_flush_hdp, 630 .invalidate_hdp = &nv_invalidate_hdp, 631 .init_doorbell_index = &nv_init_doorbell_index, 632 .need_full_reset = &nv_need_full_reset, 633 .get_pcie_usage = &nv_get_pcie_usage, 634 .need_reset_on_init = &nv_need_reset_on_init, 635 .get_pcie_replay_count = &nv_get_pcie_replay_count, 636 .supports_baco = &nv_asic_supports_baco, 637 }; 638 639 static int nv_common_early_init(void *handle) 640 { 641 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 642 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 643 644 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 645 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 646 adev->smc_rreg = NULL; 647 adev->smc_wreg = NULL; 648 adev->pcie_rreg = &nv_pcie_rreg; 649 adev->pcie_wreg = &nv_pcie_wreg; 650 651 /* TODO: will add them during VCN v2 implementation */ 652 adev->uvd_ctx_rreg = NULL; 653 adev->uvd_ctx_wreg = NULL; 654 655 adev->didt_rreg = &nv_didt_rreg; 656 adev->didt_wreg = &nv_didt_wreg; 657 658 adev->asic_funcs = &nv_asic_funcs; 659 660 adev->rev_id = nv_get_rev_id(adev); 661 adev->external_rev_id = 0xff; 662 switch (adev->asic_type) { 663 case CHIP_NAVI10: 664 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 665 AMD_CG_SUPPORT_GFX_CGCG | 666 AMD_CG_SUPPORT_IH_CG | 667 AMD_CG_SUPPORT_HDP_MGCG | 668 AMD_CG_SUPPORT_HDP_LS | 669 AMD_CG_SUPPORT_SDMA_MGCG | 670 AMD_CG_SUPPORT_SDMA_LS | 671 AMD_CG_SUPPORT_MC_MGCG | 672 AMD_CG_SUPPORT_MC_LS | 673 AMD_CG_SUPPORT_ATHUB_MGCG | 674 AMD_CG_SUPPORT_ATHUB_LS | 675 AMD_CG_SUPPORT_VCN_MGCG | 676 AMD_CG_SUPPORT_JPEG_MGCG | 677 AMD_CG_SUPPORT_BIF_MGCG | 678 AMD_CG_SUPPORT_BIF_LS; 679 adev->pg_flags = AMD_PG_SUPPORT_VCN | 680 AMD_PG_SUPPORT_VCN_DPG | 681 AMD_PG_SUPPORT_JPEG | 682 AMD_PG_SUPPORT_ATHUB; 683 adev->external_rev_id = adev->rev_id + 0x1; 684 break; 685 case CHIP_NAVI14: 686 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 687 AMD_CG_SUPPORT_GFX_CGCG | 688 AMD_CG_SUPPORT_IH_CG | 689 AMD_CG_SUPPORT_HDP_MGCG | 690 AMD_CG_SUPPORT_HDP_LS | 691 AMD_CG_SUPPORT_SDMA_MGCG | 692 AMD_CG_SUPPORT_SDMA_LS | 693 AMD_CG_SUPPORT_MC_MGCG | 694 AMD_CG_SUPPORT_MC_LS | 695 AMD_CG_SUPPORT_ATHUB_MGCG | 696 AMD_CG_SUPPORT_ATHUB_LS | 697 AMD_CG_SUPPORT_VCN_MGCG | 698 AMD_CG_SUPPORT_JPEG_MGCG | 699 AMD_CG_SUPPORT_BIF_MGCG | 700 AMD_CG_SUPPORT_BIF_LS; 701 adev->pg_flags = AMD_PG_SUPPORT_VCN | 702 AMD_PG_SUPPORT_JPEG | 703 AMD_PG_SUPPORT_VCN_DPG; 704 adev->external_rev_id = adev->rev_id + 20; 705 break; 706 case CHIP_NAVI12: 707 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 708 AMD_CG_SUPPORT_GFX_MGLS | 709 AMD_CG_SUPPORT_GFX_CGCG | 710 AMD_CG_SUPPORT_GFX_CP_LS | 711 AMD_CG_SUPPORT_GFX_RLC_LS | 712 AMD_CG_SUPPORT_IH_CG | 713 AMD_CG_SUPPORT_HDP_MGCG | 714 AMD_CG_SUPPORT_HDP_LS | 715 AMD_CG_SUPPORT_SDMA_MGCG | 716 AMD_CG_SUPPORT_SDMA_LS | 717 AMD_CG_SUPPORT_MC_MGCG | 718 AMD_CG_SUPPORT_MC_LS | 719 AMD_CG_SUPPORT_ATHUB_MGCG | 720 AMD_CG_SUPPORT_ATHUB_LS | 721 AMD_CG_SUPPORT_VCN_MGCG | 722 AMD_CG_SUPPORT_JPEG_MGCG; 723 adev->pg_flags = AMD_PG_SUPPORT_VCN | 724 AMD_PG_SUPPORT_VCN_DPG | 725 AMD_PG_SUPPORT_JPEG | 726 AMD_PG_SUPPORT_ATHUB; 727 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 728 * as a consequence, the rev_id and external_rev_id are wrong. 729 * workaround it by hardcoding rev_id to 0 (default value). 730 */ 731 if (amdgpu_sriov_vf(adev)) 732 adev->rev_id = 0; 733 adev->external_rev_id = adev->rev_id + 0xa; 734 break; 735 default: 736 /* FIXME: not supported yet */ 737 return -EINVAL; 738 } 739 740 if (amdgpu_sriov_vf(adev)) { 741 amdgpu_virt_init_setting(adev); 742 xgpu_nv_mailbox_set_irq_funcs(adev); 743 } 744 745 return 0; 746 } 747 748 static int nv_common_late_init(void *handle) 749 { 750 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 751 752 if (amdgpu_sriov_vf(adev)) 753 xgpu_nv_mailbox_get_irq(adev); 754 755 return 0; 756 } 757 758 static int nv_common_sw_init(void *handle) 759 { 760 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 761 762 if (amdgpu_sriov_vf(adev)) 763 xgpu_nv_mailbox_add_irq_id(adev); 764 765 return 0; 766 } 767 768 static int nv_common_sw_fini(void *handle) 769 { 770 return 0; 771 } 772 773 static int nv_common_hw_init(void *handle) 774 { 775 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 776 777 /* enable pcie gen2/3 link */ 778 nv_pcie_gen3_enable(adev); 779 /* enable aspm */ 780 nv_program_aspm(adev); 781 /* setup nbio registers */ 782 adev->nbio.funcs->init_registers(adev); 783 /* remap HDP registers to a hole in mmio space, 784 * for the purpose of expose those registers 785 * to process space 786 */ 787 if (adev->nbio.funcs->remap_hdp_registers) 788 adev->nbio.funcs->remap_hdp_registers(adev); 789 /* enable the doorbell aperture */ 790 nv_enable_doorbell_aperture(adev, true); 791 792 return 0; 793 } 794 795 static int nv_common_hw_fini(void *handle) 796 { 797 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 798 799 /* disable the doorbell aperture */ 800 nv_enable_doorbell_aperture(adev, false); 801 802 return 0; 803 } 804 805 static int nv_common_suspend(void *handle) 806 { 807 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 808 809 return nv_common_hw_fini(adev); 810 } 811 812 static int nv_common_resume(void *handle) 813 { 814 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 815 816 return nv_common_hw_init(adev); 817 } 818 819 static bool nv_common_is_idle(void *handle) 820 { 821 return true; 822 } 823 824 static int nv_common_wait_for_idle(void *handle) 825 { 826 return 0; 827 } 828 829 static int nv_common_soft_reset(void *handle) 830 { 831 return 0; 832 } 833 834 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 835 bool enable) 836 { 837 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 838 uint32_t hdp_mem_pwr_cntl; 839 840 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 841 AMD_CG_SUPPORT_HDP_DS | 842 AMD_CG_SUPPORT_HDP_SD))) 843 return; 844 845 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 846 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 847 848 /* Before doing clock/power mode switch, 849 * forced on IPH & RC clock */ 850 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 851 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 852 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 853 RC_MEM_CLK_SOFT_OVERRIDE, 1); 854 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 855 856 /* HDP 5.0 doesn't support dynamic power mode switch, 857 * disable clock and power gating before any changing */ 858 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 859 IPH_MEM_POWER_CTRL_EN, 0); 860 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 861 IPH_MEM_POWER_LS_EN, 0); 862 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 863 IPH_MEM_POWER_DS_EN, 0); 864 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 865 IPH_MEM_POWER_SD_EN, 0); 866 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 867 RC_MEM_POWER_CTRL_EN, 0); 868 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 869 RC_MEM_POWER_LS_EN, 0); 870 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 871 RC_MEM_POWER_DS_EN, 0); 872 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 873 RC_MEM_POWER_SD_EN, 0); 874 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 875 876 /* only one clock gating mode (LS/DS/SD) can be enabled */ 877 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 878 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 879 HDP_MEM_POWER_CTRL, 880 IPH_MEM_POWER_LS_EN, enable); 881 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 882 HDP_MEM_POWER_CTRL, 883 RC_MEM_POWER_LS_EN, enable); 884 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 885 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 886 HDP_MEM_POWER_CTRL, 887 IPH_MEM_POWER_DS_EN, enable); 888 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 889 HDP_MEM_POWER_CTRL, 890 RC_MEM_POWER_DS_EN, enable); 891 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 892 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 893 HDP_MEM_POWER_CTRL, 894 IPH_MEM_POWER_SD_EN, enable); 895 /* RC should not use shut down mode, fallback to ds */ 896 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 897 HDP_MEM_POWER_CTRL, 898 RC_MEM_POWER_DS_EN, enable); 899 } 900 901 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 902 903 /* restore IPH & RC clock override after clock/power mode changing */ 904 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 905 } 906 907 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 908 bool enable) 909 { 910 uint32_t hdp_clk_cntl; 911 912 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 913 return; 914 915 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 916 917 if (enable) { 918 hdp_clk_cntl &= 919 ~(uint32_t) 920 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 921 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 922 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 923 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 924 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 925 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 926 } else { 927 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 928 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 929 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 930 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 931 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 932 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 933 } 934 935 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 936 } 937 938 static int nv_common_set_clockgating_state(void *handle, 939 enum amd_clockgating_state state) 940 { 941 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 942 943 if (amdgpu_sriov_vf(adev)) 944 return 0; 945 946 switch (adev->asic_type) { 947 case CHIP_NAVI10: 948 case CHIP_NAVI14: 949 case CHIP_NAVI12: 950 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 951 state == AMD_CG_STATE_GATE); 952 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 953 state == AMD_CG_STATE_GATE); 954 nv_update_hdp_mem_power_gating(adev, 955 state == AMD_CG_STATE_GATE); 956 nv_update_hdp_clock_gating(adev, 957 state == AMD_CG_STATE_GATE); 958 break; 959 default: 960 break; 961 } 962 return 0; 963 } 964 965 static int nv_common_set_powergating_state(void *handle, 966 enum amd_powergating_state state) 967 { 968 /* TODO */ 969 return 0; 970 } 971 972 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 973 { 974 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 975 uint32_t tmp; 976 977 if (amdgpu_sriov_vf(adev)) 978 *flags = 0; 979 980 adev->nbio.funcs->get_clockgating_state(adev, flags); 981 982 /* AMD_CG_SUPPORT_HDP_MGCG */ 983 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 984 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 985 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 986 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 987 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 988 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 989 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 990 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 991 992 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 993 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 994 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 995 *flags |= AMD_CG_SUPPORT_HDP_LS; 996 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 997 *flags |= AMD_CG_SUPPORT_HDP_DS; 998 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 999 *flags |= AMD_CG_SUPPORT_HDP_SD; 1000 1001 return; 1002 } 1003 1004 static const struct amd_ip_funcs nv_common_ip_funcs = { 1005 .name = "nv_common", 1006 .early_init = nv_common_early_init, 1007 .late_init = nv_common_late_init, 1008 .sw_init = nv_common_sw_init, 1009 .sw_fini = nv_common_sw_fini, 1010 .hw_init = nv_common_hw_init, 1011 .hw_fini = nv_common_hw_fini, 1012 .suspend = nv_common_suspend, 1013 .resume = nv_common_resume, 1014 .is_idle = nv_common_is_idle, 1015 .wait_for_idle = nv_common_wait_for_idle, 1016 .soft_reset = nv_common_soft_reset, 1017 .set_clockgating_state = nv_common_set_clockgating_state, 1018 .set_powergating_state = nv_common_set_powergating_state, 1019 .get_clockgating_state = nv_common_get_clockgating_state, 1020 }; 1021