1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_atombios.h" 29 #include "amdgpu_ih.h" 30 #include "amdgpu_uvd.h" 31 #include "amdgpu_vce.h" 32 #include "amdgpu_ucode.h" 33 #include "amdgpu_psp.h" 34 #include "amdgpu_smu.h" 35 #include "atom.h" 36 #include "amd_pcie.h" 37 38 #include "gc/gc_10_1_0_offset.h" 39 #include "gc/gc_10_1_0_sh_mask.h" 40 #include "hdp/hdp_5_0_0_offset.h" 41 #include "hdp/hdp_5_0_0_sh_mask.h" 42 43 #include "soc15.h" 44 #include "soc15_common.h" 45 #include "gmc_v10_0.h" 46 #include "gfxhub_v2_0.h" 47 #include "mmhub_v2_0.h" 48 #include "nv.h" 49 #include "navi10_ih.h" 50 #include "gfx_v10_0.h" 51 #include "sdma_v5_0.h" 52 #include "vcn_v2_0.h" 53 #include "dce_virtual.h" 54 #include "mes_v10_1.h" 55 56 static const struct amd_ip_funcs nv_common_ip_funcs; 57 58 /* 59 * Indirect registers accessor 60 */ 61 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 62 { 63 unsigned long flags, address, data; 64 u32 r; 65 address = adev->nbio_funcs->get_pcie_index_offset(adev); 66 data = adev->nbio_funcs->get_pcie_data_offset(adev); 67 68 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 69 WREG32(address, reg); 70 (void)RREG32(address); 71 r = RREG32(data); 72 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 73 return r; 74 } 75 76 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 77 { 78 unsigned long flags, address, data; 79 80 address = adev->nbio_funcs->get_pcie_index_offset(adev); 81 data = adev->nbio_funcs->get_pcie_data_offset(adev); 82 83 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 84 WREG32(address, reg); 85 (void)RREG32(address); 86 WREG32(data, v); 87 (void)RREG32(data); 88 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 89 } 90 91 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 92 { 93 unsigned long flags, address, data; 94 u32 r; 95 96 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 97 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 98 99 spin_lock_irqsave(&adev->didt_idx_lock, flags); 100 WREG32(address, (reg)); 101 r = RREG32(data); 102 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 103 return r; 104 } 105 106 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 107 { 108 unsigned long flags, address, data; 109 110 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 111 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 112 113 spin_lock_irqsave(&adev->didt_idx_lock, flags); 114 WREG32(address, (reg)); 115 WREG32(data, (v)); 116 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 117 } 118 119 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 120 { 121 return adev->nbio_funcs->get_memsize(adev); 122 } 123 124 static u32 nv_get_xclk(struct amdgpu_device *adev) 125 { 126 return adev->clock.spll.reference_freq; 127 } 128 129 130 void nv_grbm_select(struct amdgpu_device *adev, 131 u32 me, u32 pipe, u32 queue, u32 vmid) 132 { 133 u32 grbm_gfx_cntl = 0; 134 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 135 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 136 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 137 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 138 139 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 140 } 141 142 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 143 { 144 /* todo */ 145 } 146 147 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 148 { 149 /* todo */ 150 return false; 151 } 152 153 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 154 u8 *bios, u32 length_bytes) 155 { 156 /* TODO: will implement it when SMU header is available */ 157 return false; 158 } 159 160 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 161 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 162 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 163 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 164 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 165 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 166 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 167 #if 0 /* TODO: will set it when SDMA header is available */ 168 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 169 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 170 #endif 171 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 172 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 173 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 174 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 175 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 176 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 177 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 178 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 179 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 180 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 181 }; 182 183 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 184 u32 sh_num, u32 reg_offset) 185 { 186 uint32_t val; 187 188 mutex_lock(&adev->grbm_idx_mutex); 189 if (se_num != 0xffffffff || sh_num != 0xffffffff) 190 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 191 192 val = RREG32(reg_offset); 193 194 if (se_num != 0xffffffff || sh_num != 0xffffffff) 195 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 196 mutex_unlock(&adev->grbm_idx_mutex); 197 return val; 198 } 199 200 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 201 bool indexed, u32 se_num, 202 u32 sh_num, u32 reg_offset) 203 { 204 if (indexed) { 205 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 206 } else { 207 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 208 return adev->gfx.config.gb_addr_config; 209 return RREG32(reg_offset); 210 } 211 } 212 213 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 214 u32 sh_num, u32 reg_offset, u32 *value) 215 { 216 uint32_t i; 217 struct soc15_allowed_register_entry *en; 218 219 *value = 0; 220 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 221 en = &nv_allowed_read_registers[i]; 222 if (reg_offset != 223 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 224 continue; 225 226 *value = nv_get_register_value(adev, 227 nv_allowed_read_registers[i].grbm_indexed, 228 se_num, sh_num, reg_offset); 229 return 0; 230 } 231 return -EINVAL; 232 } 233 234 #if 0 235 static void nv_gpu_pci_config_reset(struct amdgpu_device *adev) 236 { 237 u32 i; 238 239 dev_info(adev->dev, "GPU pci config reset\n"); 240 241 /* disable BM */ 242 pci_clear_master(adev->pdev); 243 /* reset */ 244 amdgpu_pci_config_reset(adev); 245 246 udelay(100); 247 248 /* wait for asic to come out of reset */ 249 for (i = 0; i < adev->usec_timeout; i++) { 250 u32 memsize = nbio_v2_3_get_memsize(adev); 251 if (memsize != 0xffffffff) 252 break; 253 udelay(1); 254 } 255 256 } 257 #endif 258 259 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 260 { 261 u32 i; 262 int ret = 0; 263 264 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 265 266 dev_info(adev->dev, "GPU mode1 reset\n"); 267 268 /* disable BM */ 269 pci_clear_master(adev->pdev); 270 271 pci_save_state(adev->pdev); 272 273 ret = psp_gpu_reset(adev); 274 if (ret) 275 dev_err(adev->dev, "GPU mode1 reset failed\n"); 276 277 pci_restore_state(adev->pdev); 278 279 /* wait for asic to come out of reset */ 280 for (i = 0; i < adev->usec_timeout; i++) { 281 u32 memsize = adev->nbio_funcs->get_memsize(adev); 282 283 if (memsize != 0xffffffff) 284 break; 285 udelay(1); 286 } 287 288 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 289 290 return ret; 291 } 292 static int nv_asic_reset(struct amdgpu_device *adev) 293 { 294 295 /* FIXME: it doesn't work since vega10 */ 296 #if 0 297 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 298 299 nv_gpu_pci_config_reset(adev); 300 301 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 302 #endif 303 int ret = 0; 304 struct smu_context *smu = &adev->smu; 305 306 if (smu_baco_is_support(smu)) 307 ret = smu_baco_reset(smu); 308 else 309 ret = nv_asic_mode1_reset(adev); 310 311 return ret; 312 } 313 314 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 315 { 316 /* todo */ 317 return 0; 318 } 319 320 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 321 { 322 /* todo */ 323 return 0; 324 } 325 326 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 327 { 328 if (pci_is_root_bus(adev->pdev->bus)) 329 return; 330 331 if (amdgpu_pcie_gen2 == 0) 332 return; 333 334 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 335 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 336 return; 337 338 /* todo */ 339 } 340 341 static void nv_program_aspm(struct amdgpu_device *adev) 342 { 343 344 if (amdgpu_aspm == 0) 345 return; 346 347 /* todo */ 348 } 349 350 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 351 bool enable) 352 { 353 adev->nbio_funcs->enable_doorbell_aperture(adev, enable); 354 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable); 355 } 356 357 static const struct amdgpu_ip_block_version nv_common_ip_block = 358 { 359 .type = AMD_IP_BLOCK_TYPE_COMMON, 360 .major = 1, 361 .minor = 0, 362 .rev = 0, 363 .funcs = &nv_common_ip_funcs, 364 }; 365 366 int nv_set_ip_blocks(struct amdgpu_device *adev) 367 { 368 /* Set IP register base before any HW register access */ 369 switch (adev->asic_type) { 370 case CHIP_NAVI10: 371 navi10_reg_base_init(adev); 372 break; 373 case CHIP_NAVI14: 374 navi14_reg_base_init(adev); 375 break; 376 default: 377 return -EINVAL; 378 } 379 380 adev->nbio_funcs = &nbio_v2_3_funcs; 381 382 adev->nbio_funcs->detect_hw_virt(adev); 383 384 switch (adev->asic_type) { 385 case CHIP_NAVI10: 386 case CHIP_NAVI14: 387 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 388 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 389 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 390 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 391 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 392 is_support_sw_smu(adev)) 393 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 394 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 395 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 396 #if defined(CONFIG_DRM_AMD_DC) 397 else if (amdgpu_device_has_dc_support(adev)) 398 amdgpu_device_ip_block_add(adev, &dm_ip_block); 399 #endif 400 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 401 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 402 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 403 is_support_sw_smu(adev)) 404 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 405 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 406 if (adev->enable_mes) 407 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 408 break; 409 default: 410 return -EINVAL; 411 } 412 413 return 0; 414 } 415 416 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 417 { 418 return adev->nbio_funcs->get_rev_id(adev); 419 } 420 421 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 422 { 423 adev->nbio_funcs->hdp_flush(adev, ring); 424 } 425 426 static void nv_invalidate_hdp(struct amdgpu_device *adev, 427 struct amdgpu_ring *ring) 428 { 429 if (!ring || !ring->funcs->emit_wreg) { 430 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 431 } else { 432 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 433 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 434 } 435 } 436 437 static bool nv_need_full_reset(struct amdgpu_device *adev) 438 { 439 return true; 440 } 441 442 static void nv_get_pcie_usage(struct amdgpu_device *adev, 443 uint64_t *count0, 444 uint64_t *count1) 445 { 446 /*TODO*/ 447 } 448 449 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 450 { 451 #if 0 452 u32 sol_reg; 453 454 if (adev->flags & AMD_IS_APU) 455 return false; 456 457 /* Check sOS sign of life register to confirm sys driver and sOS 458 * are already been loaded. 459 */ 460 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 461 if (sol_reg) 462 return true; 463 #endif 464 /* TODO: re-enable it when mode1 reset is functional */ 465 return false; 466 } 467 468 static void nv_init_doorbell_index(struct amdgpu_device *adev) 469 { 470 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 471 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 472 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 473 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 474 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 475 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 476 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 477 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 478 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 479 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 480 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 481 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 482 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 483 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 484 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 485 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 486 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 487 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 488 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 489 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 490 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 491 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 492 493 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 494 adev->doorbell_index.sdma_doorbell_range = 20; 495 } 496 497 static const struct amdgpu_asic_funcs nv_asic_funcs = 498 { 499 .read_disabled_bios = &nv_read_disabled_bios, 500 .read_bios_from_rom = &nv_read_bios_from_rom, 501 .read_register = &nv_read_register, 502 .reset = &nv_asic_reset, 503 .set_vga_state = &nv_vga_set_state, 504 .get_xclk = &nv_get_xclk, 505 .set_uvd_clocks = &nv_set_uvd_clocks, 506 .set_vce_clocks = &nv_set_vce_clocks, 507 .get_config_memsize = &nv_get_config_memsize, 508 .flush_hdp = &nv_flush_hdp, 509 .invalidate_hdp = &nv_invalidate_hdp, 510 .init_doorbell_index = &nv_init_doorbell_index, 511 .need_full_reset = &nv_need_full_reset, 512 .get_pcie_usage = &nv_get_pcie_usage, 513 .need_reset_on_init = &nv_need_reset_on_init, 514 }; 515 516 static int nv_common_early_init(void *handle) 517 { 518 bool psp_enabled = false; 519 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 520 521 adev->smc_rreg = NULL; 522 adev->smc_wreg = NULL; 523 adev->pcie_rreg = &nv_pcie_rreg; 524 adev->pcie_wreg = &nv_pcie_wreg; 525 526 /* TODO: will add them during VCN v2 implementation */ 527 adev->uvd_ctx_rreg = NULL; 528 adev->uvd_ctx_wreg = NULL; 529 530 adev->didt_rreg = &nv_didt_rreg; 531 adev->didt_wreg = &nv_didt_wreg; 532 533 adev->asic_funcs = &nv_asic_funcs; 534 535 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && 536 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) 537 psp_enabled = true; 538 539 adev->rev_id = nv_get_rev_id(adev); 540 adev->external_rev_id = 0xff; 541 switch (adev->asic_type) { 542 case CHIP_NAVI10: 543 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 544 AMD_CG_SUPPORT_GFX_CGCG | 545 AMD_CG_SUPPORT_IH_CG | 546 AMD_CG_SUPPORT_HDP_MGCG | 547 AMD_CG_SUPPORT_HDP_LS | 548 AMD_CG_SUPPORT_SDMA_MGCG | 549 AMD_CG_SUPPORT_SDMA_LS | 550 AMD_CG_SUPPORT_MC_MGCG | 551 AMD_CG_SUPPORT_MC_LS | 552 AMD_CG_SUPPORT_ATHUB_MGCG | 553 AMD_CG_SUPPORT_ATHUB_LS | 554 AMD_CG_SUPPORT_VCN_MGCG | 555 AMD_CG_SUPPORT_BIF_MGCG | 556 AMD_CG_SUPPORT_BIF_LS; 557 adev->pg_flags = AMD_PG_SUPPORT_VCN | 558 AMD_PG_SUPPORT_VCN_DPG | 559 AMD_PG_SUPPORT_MMHUB | 560 AMD_PG_SUPPORT_ATHUB; 561 adev->external_rev_id = adev->rev_id + 0x1; 562 break; 563 case CHIP_NAVI14: 564 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 565 AMD_CG_SUPPORT_GFX_CGCG | 566 AMD_CG_SUPPORT_IH_CG | 567 AMD_CG_SUPPORT_HDP_MGCG | 568 AMD_CG_SUPPORT_HDP_LS | 569 AMD_CG_SUPPORT_SDMA_MGCG | 570 AMD_CG_SUPPORT_SDMA_LS | 571 AMD_CG_SUPPORT_MC_MGCG | 572 AMD_CG_SUPPORT_MC_LS | 573 AMD_CG_SUPPORT_ATHUB_MGCG | 574 AMD_CG_SUPPORT_ATHUB_LS | 575 AMD_CG_SUPPORT_VCN_MGCG | 576 AMD_CG_SUPPORT_BIF_MGCG | 577 AMD_CG_SUPPORT_BIF_LS; 578 adev->pg_flags = AMD_PG_SUPPORT_VCN | 579 AMD_PG_SUPPORT_VCN_DPG; 580 adev->external_rev_id = adev->rev_id + 0x1; /* ??? */ 581 break; 582 default: 583 /* FIXME: not supported yet */ 584 return -EINVAL; 585 } 586 587 return 0; 588 } 589 590 static int nv_common_late_init(void *handle) 591 { 592 return 0; 593 } 594 595 static int nv_common_sw_init(void *handle) 596 { 597 return 0; 598 } 599 600 static int nv_common_sw_fini(void *handle) 601 { 602 return 0; 603 } 604 605 static int nv_common_hw_init(void *handle) 606 { 607 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 608 609 /* enable pcie gen2/3 link */ 610 nv_pcie_gen3_enable(adev); 611 /* enable aspm */ 612 nv_program_aspm(adev); 613 /* setup nbio registers */ 614 adev->nbio_funcs->init_registers(adev); 615 /* enable the doorbell aperture */ 616 nv_enable_doorbell_aperture(adev, true); 617 618 return 0; 619 } 620 621 static int nv_common_hw_fini(void *handle) 622 { 623 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 624 625 /* disable the doorbell aperture */ 626 nv_enable_doorbell_aperture(adev, false); 627 628 return 0; 629 } 630 631 static int nv_common_suspend(void *handle) 632 { 633 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 634 635 return nv_common_hw_fini(adev); 636 } 637 638 static int nv_common_resume(void *handle) 639 { 640 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 641 642 return nv_common_hw_init(adev); 643 } 644 645 static bool nv_common_is_idle(void *handle) 646 { 647 return true; 648 } 649 650 static int nv_common_wait_for_idle(void *handle) 651 { 652 return 0; 653 } 654 655 static int nv_common_soft_reset(void *handle) 656 { 657 return 0; 658 } 659 660 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 661 bool enable) 662 { 663 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 664 uint32_t hdp_mem_pwr_cntl; 665 666 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 667 AMD_CG_SUPPORT_HDP_DS | 668 AMD_CG_SUPPORT_HDP_SD))) 669 return; 670 671 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 672 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 673 674 /* Before doing clock/power mode switch, 675 * forced on IPH & RC clock */ 676 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 677 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 678 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 679 RC_MEM_CLK_SOFT_OVERRIDE, 1); 680 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 681 682 /* HDP 5.0 doesn't support dynamic power mode switch, 683 * disable clock and power gating before any changing */ 684 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 685 IPH_MEM_POWER_CTRL_EN, 0); 686 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 687 IPH_MEM_POWER_LS_EN, 0); 688 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 689 IPH_MEM_POWER_DS_EN, 0); 690 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 691 IPH_MEM_POWER_SD_EN, 0); 692 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 693 RC_MEM_POWER_CTRL_EN, 0); 694 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 695 RC_MEM_POWER_LS_EN, 0); 696 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 697 RC_MEM_POWER_DS_EN, 0); 698 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 699 RC_MEM_POWER_SD_EN, 0); 700 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 701 702 /* only one clock gating mode (LS/DS/SD) can be enabled */ 703 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 704 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 705 HDP_MEM_POWER_CTRL, 706 IPH_MEM_POWER_LS_EN, enable); 707 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 708 HDP_MEM_POWER_CTRL, 709 RC_MEM_POWER_LS_EN, enable); 710 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 711 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 712 HDP_MEM_POWER_CTRL, 713 IPH_MEM_POWER_DS_EN, enable); 714 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 715 HDP_MEM_POWER_CTRL, 716 RC_MEM_POWER_DS_EN, enable); 717 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 718 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 719 HDP_MEM_POWER_CTRL, 720 IPH_MEM_POWER_SD_EN, enable); 721 /* RC should not use shut down mode, fallback to ds */ 722 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 723 HDP_MEM_POWER_CTRL, 724 RC_MEM_POWER_DS_EN, enable); 725 } 726 727 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 728 729 /* restore IPH & RC clock override after clock/power mode changing */ 730 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 731 } 732 733 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 734 bool enable) 735 { 736 uint32_t hdp_clk_cntl; 737 738 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 739 return; 740 741 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 742 743 if (enable) { 744 hdp_clk_cntl &= 745 ~(uint32_t) 746 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 747 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 748 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 749 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 750 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 751 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 752 } else { 753 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 754 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 755 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 756 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 757 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 758 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 759 } 760 761 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 762 } 763 764 static int nv_common_set_clockgating_state(void *handle, 765 enum amd_clockgating_state state) 766 { 767 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 768 769 if (amdgpu_sriov_vf(adev)) 770 return 0; 771 772 switch (adev->asic_type) { 773 case CHIP_NAVI10: 774 case CHIP_NAVI14: 775 adev->nbio_funcs->update_medium_grain_clock_gating(adev, 776 state == AMD_CG_STATE_GATE ? true : false); 777 adev->nbio_funcs->update_medium_grain_light_sleep(adev, 778 state == AMD_CG_STATE_GATE ? true : false); 779 nv_update_hdp_mem_power_gating(adev, 780 state == AMD_CG_STATE_GATE ? true : false); 781 nv_update_hdp_clock_gating(adev, 782 state == AMD_CG_STATE_GATE ? true : false); 783 break; 784 default: 785 break; 786 } 787 return 0; 788 } 789 790 static int nv_common_set_powergating_state(void *handle, 791 enum amd_powergating_state state) 792 { 793 /* TODO */ 794 return 0; 795 } 796 797 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 798 { 799 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 800 uint32_t tmp; 801 802 if (amdgpu_sriov_vf(adev)) 803 *flags = 0; 804 805 adev->nbio_funcs->get_clockgating_state(adev, flags); 806 807 /* AMD_CG_SUPPORT_HDP_MGCG */ 808 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 809 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 810 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 811 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 812 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 813 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 814 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 815 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 816 817 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 818 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 819 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 820 *flags |= AMD_CG_SUPPORT_HDP_LS; 821 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 822 *flags |= AMD_CG_SUPPORT_HDP_DS; 823 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 824 *flags |= AMD_CG_SUPPORT_HDP_SD; 825 826 return; 827 } 828 829 static const struct amd_ip_funcs nv_common_ip_funcs = { 830 .name = "nv_common", 831 .early_init = nv_common_early_init, 832 .late_init = nv_common_late_init, 833 .sw_init = nv_common_sw_init, 834 .sw_fini = nv_common_sw_fini, 835 .hw_init = nv_common_hw_init, 836 .hw_fini = nv_common_hw_fini, 837 .suspend = nv_common_suspend, 838 .resume = nv_common_resume, 839 .is_idle = nv_common_is_idle, 840 .wait_for_idle = nv_common_wait_for_idle, 841 .soft_reset = nv_common_soft_reset, 842 .set_clockgating_state = nv_common_set_clockgating_state, 843 .set_powergating_state = nv_common_set_powergating_state, 844 .get_clockgating_state = nv_common_get_clockgating_state, 845 }; 846