1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "hdp/hdp_5_0_0_sh_mask.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nv.h" 51 #include "navi10_ih.h" 52 #include "gfx_v10_0.h" 53 #include "sdma_v5_0.h" 54 #include "vcn_v2_0.h" 55 #include "dce_virtual.h" 56 #include "mes_v10_1.h" 57 #include "mxgpu_nv.h" 58 59 static const struct amd_ip_funcs nv_common_ip_funcs; 60 61 /* 62 * Indirect registers accessor 63 */ 64 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 65 { 66 unsigned long flags, address, data; 67 u32 r; 68 address = adev->nbio.funcs->get_pcie_index_offset(adev); 69 data = adev->nbio.funcs->get_pcie_data_offset(adev); 70 71 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 72 WREG32(address, reg); 73 (void)RREG32(address); 74 r = RREG32(data); 75 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 76 return r; 77 } 78 79 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 80 { 81 unsigned long flags, address, data; 82 83 address = adev->nbio.funcs->get_pcie_index_offset(adev); 84 data = adev->nbio.funcs->get_pcie_data_offset(adev); 85 86 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 87 WREG32(address, reg); 88 (void)RREG32(address); 89 WREG32(data, v); 90 (void)RREG32(data); 91 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 92 } 93 94 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 95 { 96 unsigned long flags, address, data; 97 u32 r; 98 99 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 100 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 101 102 spin_lock_irqsave(&adev->didt_idx_lock, flags); 103 WREG32(address, (reg)); 104 r = RREG32(data); 105 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 106 return r; 107 } 108 109 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 110 { 111 unsigned long flags, address, data; 112 113 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 114 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 115 116 spin_lock_irqsave(&adev->didt_idx_lock, flags); 117 WREG32(address, (reg)); 118 WREG32(data, (v)); 119 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 120 } 121 122 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 123 { 124 return adev->nbio.funcs->get_memsize(adev); 125 } 126 127 static u32 nv_get_xclk(struct amdgpu_device *adev) 128 { 129 return adev->clock.spll.reference_freq; 130 } 131 132 133 void nv_grbm_select(struct amdgpu_device *adev, 134 u32 me, u32 pipe, u32 queue, u32 vmid) 135 { 136 u32 grbm_gfx_cntl = 0; 137 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 138 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 139 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 140 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 141 142 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 143 } 144 145 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 146 { 147 /* todo */ 148 } 149 150 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 151 { 152 /* todo */ 153 return false; 154 } 155 156 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 157 u8 *bios, u32 length_bytes) 158 { 159 /* TODO: will implement it when SMU header is available */ 160 return false; 161 } 162 163 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 164 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 165 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 166 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 167 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 168 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 169 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 170 #if 0 /* TODO: will set it when SDMA header is available */ 171 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 172 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 173 #endif 174 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 175 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 176 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 177 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 178 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 179 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 180 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 181 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 182 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 183 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 184 }; 185 186 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 187 u32 sh_num, u32 reg_offset) 188 { 189 uint32_t val; 190 191 mutex_lock(&adev->grbm_idx_mutex); 192 if (se_num != 0xffffffff || sh_num != 0xffffffff) 193 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 194 195 val = RREG32(reg_offset); 196 197 if (se_num != 0xffffffff || sh_num != 0xffffffff) 198 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 199 mutex_unlock(&adev->grbm_idx_mutex); 200 return val; 201 } 202 203 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 204 bool indexed, u32 se_num, 205 u32 sh_num, u32 reg_offset) 206 { 207 if (indexed) { 208 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 209 } else { 210 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 211 return adev->gfx.config.gb_addr_config; 212 return RREG32(reg_offset); 213 } 214 } 215 216 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 217 u32 sh_num, u32 reg_offset, u32 *value) 218 { 219 uint32_t i; 220 struct soc15_allowed_register_entry *en; 221 222 *value = 0; 223 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 224 en = &nv_allowed_read_registers[i]; 225 if (reg_offset != 226 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 227 continue; 228 229 *value = nv_get_register_value(adev, 230 nv_allowed_read_registers[i].grbm_indexed, 231 se_num, sh_num, reg_offset); 232 return 0; 233 } 234 return -EINVAL; 235 } 236 237 #if 0 238 static void nv_gpu_pci_config_reset(struct amdgpu_device *adev) 239 { 240 u32 i; 241 242 dev_info(adev->dev, "GPU pci config reset\n"); 243 244 /* disable BM */ 245 pci_clear_master(adev->pdev); 246 /* reset */ 247 amdgpu_pci_config_reset(adev); 248 249 udelay(100); 250 251 /* wait for asic to come out of reset */ 252 for (i = 0; i < adev->usec_timeout; i++) { 253 u32 memsize = nbio_v2_3_get_memsize(adev); 254 if (memsize != 0xffffffff) 255 break; 256 udelay(1); 257 } 258 259 } 260 #endif 261 262 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 263 { 264 u32 i; 265 int ret = 0; 266 267 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 268 269 dev_info(adev->dev, "GPU mode1 reset\n"); 270 271 /* disable BM */ 272 pci_clear_master(adev->pdev); 273 274 pci_save_state(adev->pdev); 275 276 ret = psp_gpu_reset(adev); 277 if (ret) 278 dev_err(adev->dev, "GPU mode1 reset failed\n"); 279 280 pci_restore_state(adev->pdev); 281 282 /* wait for asic to come out of reset */ 283 for (i = 0; i < adev->usec_timeout; i++) { 284 u32 memsize = adev->nbio.funcs->get_memsize(adev); 285 286 if (memsize != 0xffffffff) 287 break; 288 udelay(1); 289 } 290 291 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 292 293 return ret; 294 } 295 296 static enum amd_reset_method 297 nv_asic_reset_method(struct amdgpu_device *adev) 298 { 299 struct smu_context *smu = &adev->smu; 300 301 if (smu_baco_is_support(smu)) 302 return AMD_RESET_METHOD_BACO; 303 else 304 return AMD_RESET_METHOD_MODE1; 305 } 306 307 static int nv_asic_reset(struct amdgpu_device *adev) 308 { 309 310 /* FIXME: it doesn't work since vega10 */ 311 #if 0 312 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 313 314 nv_gpu_pci_config_reset(adev); 315 316 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 317 #endif 318 int ret = 0; 319 struct smu_context *smu = &adev->smu; 320 321 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 322 if (!adev->in_suspend) 323 amdgpu_inc_vram_lost(adev); 324 ret = smu_baco_reset(smu); 325 } else { 326 if (!adev->in_suspend) 327 amdgpu_inc_vram_lost(adev); 328 ret = nv_asic_mode1_reset(adev); 329 } 330 331 return ret; 332 } 333 334 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 335 { 336 /* todo */ 337 return 0; 338 } 339 340 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 341 { 342 /* todo */ 343 return 0; 344 } 345 346 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 347 { 348 if (pci_is_root_bus(adev->pdev->bus)) 349 return; 350 351 if (amdgpu_pcie_gen2 == 0) 352 return; 353 354 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 355 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 356 return; 357 358 /* todo */ 359 } 360 361 static void nv_program_aspm(struct amdgpu_device *adev) 362 { 363 364 if (amdgpu_aspm == 0) 365 return; 366 367 /* todo */ 368 } 369 370 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 371 bool enable) 372 { 373 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 374 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 375 } 376 377 static const struct amdgpu_ip_block_version nv_common_ip_block = 378 { 379 .type = AMD_IP_BLOCK_TYPE_COMMON, 380 .major = 1, 381 .minor = 0, 382 .rev = 0, 383 .funcs = &nv_common_ip_funcs, 384 }; 385 386 static int nv_reg_base_init(struct amdgpu_device *adev) 387 { 388 int r; 389 390 if (amdgpu_discovery) { 391 r = amdgpu_discovery_reg_base_init(adev); 392 if (r) { 393 DRM_WARN("failed to init reg base from ip discovery table, " 394 "fallback to legacy init method\n"); 395 goto legacy_init; 396 } 397 398 return 0; 399 } 400 401 legacy_init: 402 switch (adev->asic_type) { 403 case CHIP_NAVI10: 404 navi10_reg_base_init(adev); 405 break; 406 case CHIP_NAVI14: 407 navi14_reg_base_init(adev); 408 break; 409 case CHIP_NAVI12: 410 navi12_reg_base_init(adev); 411 break; 412 default: 413 return -EINVAL; 414 } 415 416 return 0; 417 } 418 419 int nv_set_ip_blocks(struct amdgpu_device *adev) 420 { 421 int r; 422 423 /* Set IP register base before any HW register access */ 424 r = nv_reg_base_init(adev); 425 if (r) 426 return r; 427 428 adev->nbio.funcs = &nbio_v2_3_funcs; 429 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 430 431 adev->nbio.funcs->detect_hw_virt(adev); 432 433 if (amdgpu_sriov_vf(adev)) 434 adev->virt.ops = &xgpu_nv_virt_ops; 435 436 switch (adev->asic_type) { 437 case CHIP_NAVI10: 438 case CHIP_NAVI14: 439 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 440 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 441 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 442 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 443 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 444 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 445 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 446 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 447 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 448 #if defined(CONFIG_DRM_AMD_DC) 449 else if (amdgpu_device_has_dc_support(adev)) 450 amdgpu_device_ip_block_add(adev, &dm_ip_block); 451 #endif 452 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 453 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 454 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 455 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 456 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 457 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 458 if (adev->enable_mes) 459 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 460 break; 461 case CHIP_NAVI12: 462 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 463 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 464 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 465 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 466 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 467 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 468 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 469 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 470 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 471 #if defined(CONFIG_DRM_AMD_DC) 472 else if (amdgpu_device_has_dc_support(adev)) 473 amdgpu_device_ip_block_add(adev, &dm_ip_block); 474 #endif 475 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 476 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 477 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 478 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 479 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 480 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 481 break; 482 default: 483 return -EINVAL; 484 } 485 486 return 0; 487 } 488 489 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 490 { 491 return adev->nbio.funcs->get_rev_id(adev); 492 } 493 494 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 495 { 496 adev->nbio.funcs->hdp_flush(adev, ring); 497 } 498 499 static void nv_invalidate_hdp(struct amdgpu_device *adev, 500 struct amdgpu_ring *ring) 501 { 502 if (!ring || !ring->funcs->emit_wreg) { 503 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 504 } else { 505 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 506 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 507 } 508 } 509 510 static bool nv_need_full_reset(struct amdgpu_device *adev) 511 { 512 return true; 513 } 514 515 static void nv_get_pcie_usage(struct amdgpu_device *adev, 516 uint64_t *count0, 517 uint64_t *count1) 518 { 519 /*TODO*/ 520 } 521 522 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 523 { 524 #if 0 525 u32 sol_reg; 526 527 if (adev->flags & AMD_IS_APU) 528 return false; 529 530 /* Check sOS sign of life register to confirm sys driver and sOS 531 * are already been loaded. 532 */ 533 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 534 if (sol_reg) 535 return true; 536 #endif 537 /* TODO: re-enable it when mode1 reset is functional */ 538 return false; 539 } 540 541 static void nv_init_doorbell_index(struct amdgpu_device *adev) 542 { 543 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 544 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 545 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 546 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 547 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 548 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 549 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 550 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 551 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 552 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 553 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 554 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 555 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 556 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 557 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 558 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 559 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 560 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 561 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 562 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 563 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 564 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 565 566 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 567 adev->doorbell_index.sdma_doorbell_range = 20; 568 } 569 570 static const struct amdgpu_asic_funcs nv_asic_funcs = 571 { 572 .read_disabled_bios = &nv_read_disabled_bios, 573 .read_bios_from_rom = &nv_read_bios_from_rom, 574 .read_register = &nv_read_register, 575 .reset = &nv_asic_reset, 576 .reset_method = &nv_asic_reset_method, 577 .set_vga_state = &nv_vga_set_state, 578 .get_xclk = &nv_get_xclk, 579 .set_uvd_clocks = &nv_set_uvd_clocks, 580 .set_vce_clocks = &nv_set_vce_clocks, 581 .get_config_memsize = &nv_get_config_memsize, 582 .flush_hdp = &nv_flush_hdp, 583 .invalidate_hdp = &nv_invalidate_hdp, 584 .init_doorbell_index = &nv_init_doorbell_index, 585 .need_full_reset = &nv_need_full_reset, 586 .get_pcie_usage = &nv_get_pcie_usage, 587 .need_reset_on_init = &nv_need_reset_on_init, 588 }; 589 590 static int nv_common_early_init(void *handle) 591 { 592 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 593 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 594 595 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 596 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 597 adev->smc_rreg = NULL; 598 adev->smc_wreg = NULL; 599 adev->pcie_rreg = &nv_pcie_rreg; 600 adev->pcie_wreg = &nv_pcie_wreg; 601 602 /* TODO: will add them during VCN v2 implementation */ 603 adev->uvd_ctx_rreg = NULL; 604 adev->uvd_ctx_wreg = NULL; 605 606 adev->didt_rreg = &nv_didt_rreg; 607 adev->didt_wreg = &nv_didt_wreg; 608 609 adev->asic_funcs = &nv_asic_funcs; 610 611 adev->rev_id = nv_get_rev_id(adev); 612 adev->external_rev_id = 0xff; 613 switch (adev->asic_type) { 614 case CHIP_NAVI10: 615 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 616 AMD_CG_SUPPORT_GFX_CGCG | 617 AMD_CG_SUPPORT_IH_CG | 618 AMD_CG_SUPPORT_HDP_MGCG | 619 AMD_CG_SUPPORT_HDP_LS | 620 AMD_CG_SUPPORT_SDMA_MGCG | 621 AMD_CG_SUPPORT_SDMA_LS | 622 AMD_CG_SUPPORT_MC_MGCG | 623 AMD_CG_SUPPORT_MC_LS | 624 AMD_CG_SUPPORT_ATHUB_MGCG | 625 AMD_CG_SUPPORT_ATHUB_LS | 626 AMD_CG_SUPPORT_VCN_MGCG | 627 AMD_CG_SUPPORT_BIF_MGCG | 628 AMD_CG_SUPPORT_BIF_LS; 629 adev->pg_flags = AMD_PG_SUPPORT_VCN | 630 AMD_PG_SUPPORT_VCN_DPG | 631 AMD_PG_SUPPORT_ATHUB; 632 adev->external_rev_id = adev->rev_id + 0x1; 633 break; 634 case CHIP_NAVI14: 635 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 636 AMD_CG_SUPPORT_GFX_CGCG | 637 AMD_CG_SUPPORT_IH_CG | 638 AMD_CG_SUPPORT_HDP_MGCG | 639 AMD_CG_SUPPORT_HDP_LS | 640 AMD_CG_SUPPORT_SDMA_MGCG | 641 AMD_CG_SUPPORT_SDMA_LS | 642 AMD_CG_SUPPORT_MC_MGCG | 643 AMD_CG_SUPPORT_MC_LS | 644 AMD_CG_SUPPORT_ATHUB_MGCG | 645 AMD_CG_SUPPORT_ATHUB_LS | 646 AMD_CG_SUPPORT_VCN_MGCG | 647 AMD_CG_SUPPORT_BIF_MGCG | 648 AMD_CG_SUPPORT_BIF_LS; 649 adev->pg_flags = AMD_PG_SUPPORT_VCN | 650 AMD_PG_SUPPORT_VCN_DPG; 651 adev->external_rev_id = adev->rev_id + 20; 652 break; 653 case CHIP_NAVI12: 654 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 655 AMD_CG_SUPPORT_GFX_MGLS | 656 AMD_CG_SUPPORT_GFX_CGCG | 657 AMD_CG_SUPPORT_GFX_CP_LS | 658 AMD_CG_SUPPORT_GFX_RLC_LS | 659 AMD_CG_SUPPORT_IH_CG | 660 AMD_CG_SUPPORT_HDP_MGCG | 661 AMD_CG_SUPPORT_HDP_LS | 662 AMD_CG_SUPPORT_SDMA_MGCG | 663 AMD_CG_SUPPORT_SDMA_LS | 664 AMD_CG_SUPPORT_MC_MGCG | 665 AMD_CG_SUPPORT_MC_LS | 666 AMD_CG_SUPPORT_ATHUB_MGCG | 667 AMD_CG_SUPPORT_ATHUB_LS | 668 AMD_CG_SUPPORT_VCN_MGCG; 669 adev->pg_flags = AMD_PG_SUPPORT_VCN | 670 AMD_PG_SUPPORT_VCN_DPG | 671 AMD_PG_SUPPORT_ATHUB; 672 adev->external_rev_id = adev->rev_id + 0xa; 673 break; 674 default: 675 /* FIXME: not supported yet */ 676 return -EINVAL; 677 } 678 679 if (amdgpu_sriov_vf(adev)) { 680 amdgpu_virt_init_setting(adev); 681 xgpu_nv_mailbox_set_irq_funcs(adev); 682 } 683 684 return 0; 685 } 686 687 static int nv_common_late_init(void *handle) 688 { 689 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 690 691 if (amdgpu_sriov_vf(adev)) 692 xgpu_nv_mailbox_get_irq(adev); 693 694 return 0; 695 } 696 697 static int nv_common_sw_init(void *handle) 698 { 699 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 700 701 if (amdgpu_sriov_vf(adev)) 702 xgpu_nv_mailbox_add_irq_id(adev); 703 704 return 0; 705 } 706 707 static int nv_common_sw_fini(void *handle) 708 { 709 return 0; 710 } 711 712 static int nv_common_hw_init(void *handle) 713 { 714 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 715 716 /* enable pcie gen2/3 link */ 717 nv_pcie_gen3_enable(adev); 718 /* enable aspm */ 719 nv_program_aspm(adev); 720 /* setup nbio registers */ 721 adev->nbio.funcs->init_registers(adev); 722 /* remap HDP registers to a hole in mmio space, 723 * for the purpose of expose those registers 724 * to process space 725 */ 726 if (adev->nbio.funcs->remap_hdp_registers) 727 adev->nbio.funcs->remap_hdp_registers(adev); 728 /* enable the doorbell aperture */ 729 nv_enable_doorbell_aperture(adev, true); 730 731 return 0; 732 } 733 734 static int nv_common_hw_fini(void *handle) 735 { 736 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 737 738 /* disable the doorbell aperture */ 739 nv_enable_doorbell_aperture(adev, false); 740 741 return 0; 742 } 743 744 static int nv_common_suspend(void *handle) 745 { 746 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 747 748 return nv_common_hw_fini(adev); 749 } 750 751 static int nv_common_resume(void *handle) 752 { 753 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 754 755 return nv_common_hw_init(adev); 756 } 757 758 static bool nv_common_is_idle(void *handle) 759 { 760 return true; 761 } 762 763 static int nv_common_wait_for_idle(void *handle) 764 { 765 return 0; 766 } 767 768 static int nv_common_soft_reset(void *handle) 769 { 770 return 0; 771 } 772 773 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 774 bool enable) 775 { 776 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 777 uint32_t hdp_mem_pwr_cntl; 778 779 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 780 AMD_CG_SUPPORT_HDP_DS | 781 AMD_CG_SUPPORT_HDP_SD))) 782 return; 783 784 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 785 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 786 787 /* Before doing clock/power mode switch, 788 * forced on IPH & RC clock */ 789 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 790 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 791 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 792 RC_MEM_CLK_SOFT_OVERRIDE, 1); 793 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 794 795 /* HDP 5.0 doesn't support dynamic power mode switch, 796 * disable clock and power gating before any changing */ 797 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 798 IPH_MEM_POWER_CTRL_EN, 0); 799 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 800 IPH_MEM_POWER_LS_EN, 0); 801 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 802 IPH_MEM_POWER_DS_EN, 0); 803 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 804 IPH_MEM_POWER_SD_EN, 0); 805 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 806 RC_MEM_POWER_CTRL_EN, 0); 807 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 808 RC_MEM_POWER_LS_EN, 0); 809 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 810 RC_MEM_POWER_DS_EN, 0); 811 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 812 RC_MEM_POWER_SD_EN, 0); 813 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 814 815 /* only one clock gating mode (LS/DS/SD) can be enabled */ 816 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 817 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 818 HDP_MEM_POWER_CTRL, 819 IPH_MEM_POWER_LS_EN, enable); 820 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 821 HDP_MEM_POWER_CTRL, 822 RC_MEM_POWER_LS_EN, enable); 823 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 824 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 825 HDP_MEM_POWER_CTRL, 826 IPH_MEM_POWER_DS_EN, enable); 827 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 828 HDP_MEM_POWER_CTRL, 829 RC_MEM_POWER_DS_EN, enable); 830 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 831 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 832 HDP_MEM_POWER_CTRL, 833 IPH_MEM_POWER_SD_EN, enable); 834 /* RC should not use shut down mode, fallback to ds */ 835 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 836 HDP_MEM_POWER_CTRL, 837 RC_MEM_POWER_DS_EN, enable); 838 } 839 840 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 841 842 /* restore IPH & RC clock override after clock/power mode changing */ 843 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 844 } 845 846 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 847 bool enable) 848 { 849 uint32_t hdp_clk_cntl; 850 851 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 852 return; 853 854 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 855 856 if (enable) { 857 hdp_clk_cntl &= 858 ~(uint32_t) 859 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 860 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 861 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 862 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 863 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 864 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 865 } else { 866 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 867 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 868 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 869 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 870 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 871 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 872 } 873 874 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 875 } 876 877 static int nv_common_set_clockgating_state(void *handle, 878 enum amd_clockgating_state state) 879 { 880 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 881 882 if (amdgpu_sriov_vf(adev)) 883 return 0; 884 885 switch (adev->asic_type) { 886 case CHIP_NAVI10: 887 case CHIP_NAVI14: 888 case CHIP_NAVI12: 889 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 890 state == AMD_CG_STATE_GATE ? true : false); 891 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 892 state == AMD_CG_STATE_GATE ? true : false); 893 nv_update_hdp_mem_power_gating(adev, 894 state == AMD_CG_STATE_GATE ? true : false); 895 nv_update_hdp_clock_gating(adev, 896 state == AMD_CG_STATE_GATE ? true : false); 897 break; 898 default: 899 break; 900 } 901 return 0; 902 } 903 904 static int nv_common_set_powergating_state(void *handle, 905 enum amd_powergating_state state) 906 { 907 /* TODO */ 908 return 0; 909 } 910 911 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 912 { 913 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 914 uint32_t tmp; 915 916 if (amdgpu_sriov_vf(adev)) 917 *flags = 0; 918 919 adev->nbio.funcs->get_clockgating_state(adev, flags); 920 921 /* AMD_CG_SUPPORT_HDP_MGCG */ 922 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 923 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 924 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 925 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 926 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 927 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 928 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 929 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 930 931 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 932 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 933 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 934 *flags |= AMD_CG_SUPPORT_HDP_LS; 935 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 936 *flags |= AMD_CG_SUPPORT_HDP_DS; 937 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 938 *flags |= AMD_CG_SUPPORT_HDP_SD; 939 940 return; 941 } 942 943 static const struct amd_ip_funcs nv_common_ip_funcs = { 944 .name = "nv_common", 945 .early_init = nv_common_early_init, 946 .late_init = nv_common_late_init, 947 .sw_init = nv_common_sw_init, 948 .sw_fini = nv_common_sw_fini, 949 .hw_init = nv_common_hw_init, 950 .hw_fini = nv_common_hw_fini, 951 .suspend = nv_common_suspend, 952 .resume = nv_common_resume, 953 .is_idle = nv_common_is_idle, 954 .wait_for_idle = nv_common_wait_for_idle, 955 .soft_reset = nv_common_soft_reset, 956 .set_clockgating_state = nv_common_set_clockgating_state, 957 .set_powergating_state = nv_common_set_powergating_state, 958 .get_clockgating_state = nv_common_get_clockgating_state, 959 }; 960