1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "hdp/hdp_5_0_0_sh_mask.h" 43 #include "smuio/smuio_11_0_0_offset.h" 44 #include "mp/mp_11_0_offset.h" 45 46 #include "soc15.h" 47 #include "soc15_common.h" 48 #include "gmc_v10_0.h" 49 #include "gfxhub_v2_0.h" 50 #include "mmhub_v2_0.h" 51 #include "nbio_v2_3.h" 52 #include "nbio_v7_2.h" 53 #include "nv.h" 54 #include "navi10_ih.h" 55 #include "gfx_v10_0.h" 56 #include "sdma_v5_0.h" 57 #include "sdma_v5_2.h" 58 #include "vcn_v2_0.h" 59 #include "jpeg_v2_0.h" 60 #include "vcn_v3_0.h" 61 #include "jpeg_v3_0.h" 62 #include "dce_virtual.h" 63 #include "mes_v10_1.h" 64 #include "mxgpu_nv.h" 65 66 static const struct amd_ip_funcs nv_common_ip_funcs; 67 68 /* 69 * Indirect registers accessor 70 */ 71 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 72 { 73 unsigned long address, data; 74 address = adev->nbio.funcs->get_pcie_index_offset(adev); 75 data = adev->nbio.funcs->get_pcie_data_offset(adev); 76 77 return amdgpu_device_indirect_rreg(adev, address, data, reg); 78 } 79 80 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 81 { 82 unsigned long address, data; 83 84 address = adev->nbio.funcs->get_pcie_index_offset(adev); 85 data = adev->nbio.funcs->get_pcie_data_offset(adev); 86 87 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 88 } 89 90 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 91 { 92 unsigned long address, data; 93 address = adev->nbio.funcs->get_pcie_index_offset(adev); 94 data = adev->nbio.funcs->get_pcie_data_offset(adev); 95 96 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 97 } 98 99 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 100 { 101 unsigned long flags, address, data; 102 u32 r; 103 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 104 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 105 106 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 107 WREG32(address, reg * 4); 108 (void)RREG32(address); 109 r = RREG32(data); 110 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 111 return r; 112 } 113 114 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 115 { 116 unsigned long address, data; 117 118 address = adev->nbio.funcs->get_pcie_index_offset(adev); 119 data = adev->nbio.funcs->get_pcie_data_offset(adev); 120 121 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 122 } 123 124 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 125 { 126 unsigned long flags, address, data; 127 128 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 129 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 130 131 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 132 WREG32(address, reg * 4); 133 (void)RREG32(address); 134 WREG32(data, v); 135 (void)RREG32(data); 136 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 137 } 138 139 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 140 { 141 unsigned long flags, address, data; 142 u32 r; 143 144 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 145 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 146 147 spin_lock_irqsave(&adev->didt_idx_lock, flags); 148 WREG32(address, (reg)); 149 r = RREG32(data); 150 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 151 return r; 152 } 153 154 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 155 { 156 unsigned long flags, address, data; 157 158 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 159 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 160 161 spin_lock_irqsave(&adev->didt_idx_lock, flags); 162 WREG32(address, (reg)); 163 WREG32(data, (v)); 164 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 165 } 166 167 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 168 { 169 return adev->nbio.funcs->get_memsize(adev); 170 } 171 172 static u32 nv_get_xclk(struct amdgpu_device *adev) 173 { 174 return adev->clock.spll.reference_freq; 175 } 176 177 178 void nv_grbm_select(struct amdgpu_device *adev, 179 u32 me, u32 pipe, u32 queue, u32 vmid) 180 { 181 u32 grbm_gfx_cntl = 0; 182 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 183 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 184 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 185 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 186 187 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 188 } 189 190 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 191 { 192 /* todo */ 193 } 194 195 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 196 { 197 /* todo */ 198 return false; 199 } 200 201 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 202 u8 *bios, u32 length_bytes) 203 { 204 u32 *dw_ptr; 205 u32 i, length_dw; 206 207 if (bios == NULL) 208 return false; 209 if (length_bytes == 0) 210 return false; 211 /* APU vbios image is part of sbios image */ 212 if (adev->flags & AMD_IS_APU) 213 return false; 214 215 dw_ptr = (u32 *)bios; 216 length_dw = ALIGN(length_bytes, 4) / 4; 217 218 /* set rom index to 0 */ 219 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 220 /* read out the rom data */ 221 for (i = 0; i < length_dw; i++) 222 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 223 224 return true; 225 } 226 227 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 228 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 229 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 230 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 231 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 232 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 233 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 234 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 235 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 236 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 237 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 238 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 239 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 240 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 241 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 242 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 243 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 244 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 245 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 246 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 247 }; 248 249 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 250 u32 sh_num, u32 reg_offset) 251 { 252 uint32_t val; 253 254 mutex_lock(&adev->grbm_idx_mutex); 255 if (se_num != 0xffffffff || sh_num != 0xffffffff) 256 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 257 258 val = RREG32(reg_offset); 259 260 if (se_num != 0xffffffff || sh_num != 0xffffffff) 261 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 262 mutex_unlock(&adev->grbm_idx_mutex); 263 return val; 264 } 265 266 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 267 bool indexed, u32 se_num, 268 u32 sh_num, u32 reg_offset) 269 { 270 if (indexed) { 271 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 272 } else { 273 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 274 return adev->gfx.config.gb_addr_config; 275 return RREG32(reg_offset); 276 } 277 } 278 279 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 280 u32 sh_num, u32 reg_offset, u32 *value) 281 { 282 uint32_t i; 283 struct soc15_allowed_register_entry *en; 284 285 *value = 0; 286 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 287 en = &nv_allowed_read_registers[i]; 288 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 289 reg_offset != 290 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 291 continue; 292 293 *value = nv_get_register_value(adev, 294 nv_allowed_read_registers[i].grbm_indexed, 295 se_num, sh_num, reg_offset); 296 return 0; 297 } 298 return -EINVAL; 299 } 300 301 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 302 { 303 u32 i; 304 int ret = 0; 305 306 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 307 308 /* disable BM */ 309 pci_clear_master(adev->pdev); 310 311 amdgpu_device_cache_pci_state(adev->pdev); 312 313 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 314 dev_info(adev->dev, "GPU smu mode1 reset\n"); 315 ret = amdgpu_dpm_mode1_reset(adev); 316 } else { 317 dev_info(adev->dev, "GPU psp mode1 reset\n"); 318 ret = psp_gpu_reset(adev); 319 } 320 321 if (ret) 322 dev_err(adev->dev, "GPU mode1 reset failed\n"); 323 amdgpu_device_load_pci_state(adev->pdev); 324 325 /* wait for asic to come out of reset */ 326 for (i = 0; i < adev->usec_timeout; i++) { 327 u32 memsize = adev->nbio.funcs->get_memsize(adev); 328 329 if (memsize != 0xffffffff) 330 break; 331 udelay(1); 332 } 333 334 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 335 336 return ret; 337 } 338 339 static bool nv_asic_supports_baco(struct amdgpu_device *adev) 340 { 341 struct smu_context *smu = &adev->smu; 342 343 if (smu_baco_is_support(smu)) 344 return true; 345 else 346 return false; 347 } 348 349 static enum amd_reset_method 350 nv_asic_reset_method(struct amdgpu_device *adev) 351 { 352 struct smu_context *smu = &adev->smu; 353 354 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 355 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 356 return amdgpu_reset_method; 357 358 if (amdgpu_reset_method != -1) 359 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 360 amdgpu_reset_method); 361 362 switch (adev->asic_type) { 363 case CHIP_SIENNA_CICHLID: 364 case CHIP_NAVY_FLOUNDER: 365 return AMD_RESET_METHOD_MODE1; 366 default: 367 if (smu_baco_is_support(smu)) 368 return AMD_RESET_METHOD_BACO; 369 else 370 return AMD_RESET_METHOD_MODE1; 371 } 372 } 373 374 static int nv_asic_reset(struct amdgpu_device *adev) 375 { 376 int ret = 0; 377 struct smu_context *smu = &adev->smu; 378 379 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 380 dev_info(adev->dev, "BACO reset\n"); 381 382 ret = smu_baco_enter(smu); 383 if (ret) 384 return ret; 385 ret = smu_baco_exit(smu); 386 if (ret) 387 return ret; 388 } else { 389 dev_info(adev->dev, "MODE1 reset\n"); 390 ret = nv_asic_mode1_reset(adev); 391 } 392 393 return ret; 394 } 395 396 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 397 { 398 /* todo */ 399 return 0; 400 } 401 402 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 403 { 404 /* todo */ 405 return 0; 406 } 407 408 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 409 { 410 if (pci_is_root_bus(adev->pdev->bus)) 411 return; 412 413 if (amdgpu_pcie_gen2 == 0) 414 return; 415 416 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 417 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 418 return; 419 420 /* todo */ 421 } 422 423 static void nv_program_aspm(struct amdgpu_device *adev) 424 { 425 426 if (amdgpu_aspm == 0) 427 return; 428 429 /* todo */ 430 } 431 432 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 433 bool enable) 434 { 435 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 436 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 437 } 438 439 static const struct amdgpu_ip_block_version nv_common_ip_block = 440 { 441 .type = AMD_IP_BLOCK_TYPE_COMMON, 442 .major = 1, 443 .minor = 0, 444 .rev = 0, 445 .funcs = &nv_common_ip_funcs, 446 }; 447 448 static int nv_reg_base_init(struct amdgpu_device *adev) 449 { 450 int r; 451 452 /* IP discovery table is not available yet */ 453 if (adev->asic_type == CHIP_VANGOGH) 454 goto legacy_init; 455 456 if (amdgpu_discovery) { 457 r = amdgpu_discovery_reg_base_init(adev); 458 if (r) { 459 DRM_WARN("failed to init reg base from ip discovery table, " 460 "fallback to legacy init method\n"); 461 goto legacy_init; 462 } 463 464 return 0; 465 } 466 467 legacy_init: 468 switch (adev->asic_type) { 469 case CHIP_NAVI10: 470 navi10_reg_base_init(adev); 471 break; 472 case CHIP_NAVI14: 473 navi14_reg_base_init(adev); 474 break; 475 case CHIP_NAVI12: 476 navi12_reg_base_init(adev); 477 break; 478 case CHIP_SIENNA_CICHLID: 479 case CHIP_NAVY_FLOUNDER: 480 sienna_cichlid_reg_base_init(adev); 481 break; 482 case CHIP_VANGOGH: 483 vangogh_reg_base_init(adev); 484 break; 485 default: 486 return -EINVAL; 487 } 488 489 return 0; 490 } 491 492 void nv_set_virt_ops(struct amdgpu_device *adev) 493 { 494 adev->virt.ops = &xgpu_nv_virt_ops; 495 } 496 497 int nv_set_ip_blocks(struct amdgpu_device *adev) 498 { 499 int r; 500 501 if (adev->flags & AMD_IS_APU) { 502 adev->nbio.funcs = &nbio_v7_2_funcs; 503 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 504 } else { 505 adev->nbio.funcs = &nbio_v2_3_funcs; 506 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 507 } 508 509 if (adev->asic_type == CHIP_SIENNA_CICHLID) 510 adev->gmc.xgmi.supported = true; 511 512 /* Set IP register base before any HW register access */ 513 r = nv_reg_base_init(adev); 514 if (r) 515 return r; 516 517 switch (adev->asic_type) { 518 case CHIP_NAVI10: 519 case CHIP_NAVI14: 520 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 521 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 522 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 523 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 524 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 525 !amdgpu_sriov_vf(adev)) 526 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 527 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 528 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 529 #if defined(CONFIG_DRM_AMD_DC) 530 else if (amdgpu_device_has_dc_support(adev)) 531 amdgpu_device_ip_block_add(adev, &dm_ip_block); 532 #endif 533 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 534 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 535 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 536 !amdgpu_sriov_vf(adev)) 537 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 538 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 539 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 540 if (adev->enable_mes) 541 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 542 break; 543 case CHIP_NAVI12: 544 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 545 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 546 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 547 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 548 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 549 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 550 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 551 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 552 #if defined(CONFIG_DRM_AMD_DC) 553 else if (amdgpu_device_has_dc_support(adev)) 554 amdgpu_device_ip_block_add(adev, &dm_ip_block); 555 #endif 556 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 557 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 558 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 559 !amdgpu_sriov_vf(adev)) 560 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 561 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 562 if (!amdgpu_sriov_vf(adev)) 563 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 564 break; 565 case CHIP_SIENNA_CICHLID: 566 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 567 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 568 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 569 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 570 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 571 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 572 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 573 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 574 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 575 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 576 #if defined(CONFIG_DRM_AMD_DC) 577 else if (amdgpu_device_has_dc_support(adev)) 578 amdgpu_device_ip_block_add(adev, &dm_ip_block); 579 #endif 580 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 581 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 582 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 583 if (!amdgpu_sriov_vf(adev)) 584 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 585 586 if (adev->enable_mes) 587 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 588 break; 589 case CHIP_NAVY_FLOUNDER: 590 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 591 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 592 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 593 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 594 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 595 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 596 is_support_sw_smu(adev)) 597 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 598 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 599 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 600 #if defined(CONFIG_DRM_AMD_DC) 601 else if (amdgpu_device_has_dc_support(adev)) 602 amdgpu_device_ip_block_add(adev, &dm_ip_block); 603 #endif 604 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 605 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 606 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 607 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 608 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 609 is_support_sw_smu(adev)) 610 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 611 break; 612 case CHIP_VANGOGH: 613 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 614 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 615 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 616 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 617 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 618 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 619 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 620 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 621 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 622 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 623 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 624 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 625 break; 626 default: 627 return -EINVAL; 628 } 629 630 return 0; 631 } 632 633 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 634 { 635 return adev->nbio.funcs->get_rev_id(adev); 636 } 637 638 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 639 { 640 adev->nbio.funcs->hdp_flush(adev, ring); 641 } 642 643 static void nv_invalidate_hdp(struct amdgpu_device *adev, 644 struct amdgpu_ring *ring) 645 { 646 if (!ring || !ring->funcs->emit_wreg) { 647 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 648 } else { 649 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 650 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 651 } 652 } 653 654 static bool nv_need_full_reset(struct amdgpu_device *adev) 655 { 656 return true; 657 } 658 659 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 660 { 661 u32 sol_reg; 662 663 if (adev->flags & AMD_IS_APU) 664 return false; 665 666 /* Check sOS sign of life register to confirm sys driver and sOS 667 * are already been loaded. 668 */ 669 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 670 if (sol_reg) 671 return true; 672 673 return false; 674 } 675 676 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 677 { 678 679 /* TODO 680 * dummy implement for pcie_replay_count sysfs interface 681 * */ 682 683 return 0; 684 } 685 686 static void nv_init_doorbell_index(struct amdgpu_device *adev) 687 { 688 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 689 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 690 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 691 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 692 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 693 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 694 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 695 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 696 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 697 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 698 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 699 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 700 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 701 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 702 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 703 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 704 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 705 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 706 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 707 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 708 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 709 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 710 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 711 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 712 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 713 714 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 715 adev->doorbell_index.sdma_doorbell_range = 20; 716 } 717 718 static void nv_pre_asic_init(struct amdgpu_device *adev) 719 { 720 } 721 722 static const struct amdgpu_asic_funcs nv_asic_funcs = 723 { 724 .read_disabled_bios = &nv_read_disabled_bios, 725 .read_bios_from_rom = &nv_read_bios_from_rom, 726 .read_register = &nv_read_register, 727 .reset = &nv_asic_reset, 728 .reset_method = &nv_asic_reset_method, 729 .set_vga_state = &nv_vga_set_state, 730 .get_xclk = &nv_get_xclk, 731 .set_uvd_clocks = &nv_set_uvd_clocks, 732 .set_vce_clocks = &nv_set_vce_clocks, 733 .get_config_memsize = &nv_get_config_memsize, 734 .flush_hdp = &nv_flush_hdp, 735 .invalidate_hdp = &nv_invalidate_hdp, 736 .init_doorbell_index = &nv_init_doorbell_index, 737 .need_full_reset = &nv_need_full_reset, 738 .need_reset_on_init = &nv_need_reset_on_init, 739 .get_pcie_replay_count = &nv_get_pcie_replay_count, 740 .supports_baco = &nv_asic_supports_baco, 741 .pre_asic_init = &nv_pre_asic_init, 742 }; 743 744 static int nv_common_early_init(void *handle) 745 { 746 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 747 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 748 749 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 750 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 751 adev->smc_rreg = NULL; 752 adev->smc_wreg = NULL; 753 adev->pcie_rreg = &nv_pcie_rreg; 754 adev->pcie_wreg = &nv_pcie_wreg; 755 adev->pcie_rreg64 = &nv_pcie_rreg64; 756 adev->pcie_wreg64 = &nv_pcie_wreg64; 757 adev->pciep_rreg = &nv_pcie_port_rreg; 758 adev->pciep_wreg = &nv_pcie_port_wreg; 759 760 /* TODO: will add them during VCN v2 implementation */ 761 adev->uvd_ctx_rreg = NULL; 762 adev->uvd_ctx_wreg = NULL; 763 764 adev->didt_rreg = &nv_didt_rreg; 765 adev->didt_wreg = &nv_didt_wreg; 766 767 adev->asic_funcs = &nv_asic_funcs; 768 769 adev->rev_id = nv_get_rev_id(adev); 770 adev->external_rev_id = 0xff; 771 switch (adev->asic_type) { 772 case CHIP_NAVI10: 773 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 774 AMD_CG_SUPPORT_GFX_CGCG | 775 AMD_CG_SUPPORT_IH_CG | 776 AMD_CG_SUPPORT_HDP_MGCG | 777 AMD_CG_SUPPORT_HDP_LS | 778 AMD_CG_SUPPORT_SDMA_MGCG | 779 AMD_CG_SUPPORT_SDMA_LS | 780 AMD_CG_SUPPORT_MC_MGCG | 781 AMD_CG_SUPPORT_MC_LS | 782 AMD_CG_SUPPORT_ATHUB_MGCG | 783 AMD_CG_SUPPORT_ATHUB_LS | 784 AMD_CG_SUPPORT_VCN_MGCG | 785 AMD_CG_SUPPORT_JPEG_MGCG | 786 AMD_CG_SUPPORT_BIF_MGCG | 787 AMD_CG_SUPPORT_BIF_LS; 788 adev->pg_flags = AMD_PG_SUPPORT_VCN | 789 AMD_PG_SUPPORT_VCN_DPG | 790 AMD_PG_SUPPORT_JPEG | 791 AMD_PG_SUPPORT_ATHUB; 792 adev->external_rev_id = adev->rev_id + 0x1; 793 break; 794 case CHIP_NAVI14: 795 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 796 AMD_CG_SUPPORT_GFX_CGCG | 797 AMD_CG_SUPPORT_IH_CG | 798 AMD_CG_SUPPORT_HDP_MGCG | 799 AMD_CG_SUPPORT_HDP_LS | 800 AMD_CG_SUPPORT_SDMA_MGCG | 801 AMD_CG_SUPPORT_SDMA_LS | 802 AMD_CG_SUPPORT_MC_MGCG | 803 AMD_CG_SUPPORT_MC_LS | 804 AMD_CG_SUPPORT_ATHUB_MGCG | 805 AMD_CG_SUPPORT_ATHUB_LS | 806 AMD_CG_SUPPORT_VCN_MGCG | 807 AMD_CG_SUPPORT_JPEG_MGCG | 808 AMD_CG_SUPPORT_BIF_MGCG | 809 AMD_CG_SUPPORT_BIF_LS; 810 adev->pg_flags = AMD_PG_SUPPORT_VCN | 811 AMD_PG_SUPPORT_JPEG | 812 AMD_PG_SUPPORT_VCN_DPG; 813 adev->external_rev_id = adev->rev_id + 20; 814 break; 815 case CHIP_NAVI12: 816 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 817 AMD_CG_SUPPORT_GFX_MGLS | 818 AMD_CG_SUPPORT_GFX_CGCG | 819 AMD_CG_SUPPORT_GFX_CP_LS | 820 AMD_CG_SUPPORT_GFX_RLC_LS | 821 AMD_CG_SUPPORT_IH_CG | 822 AMD_CG_SUPPORT_HDP_MGCG | 823 AMD_CG_SUPPORT_HDP_LS | 824 AMD_CG_SUPPORT_SDMA_MGCG | 825 AMD_CG_SUPPORT_SDMA_LS | 826 AMD_CG_SUPPORT_MC_MGCG | 827 AMD_CG_SUPPORT_MC_LS | 828 AMD_CG_SUPPORT_ATHUB_MGCG | 829 AMD_CG_SUPPORT_ATHUB_LS | 830 AMD_CG_SUPPORT_VCN_MGCG | 831 AMD_CG_SUPPORT_JPEG_MGCG; 832 adev->pg_flags = AMD_PG_SUPPORT_VCN | 833 AMD_PG_SUPPORT_VCN_DPG | 834 AMD_PG_SUPPORT_JPEG | 835 AMD_PG_SUPPORT_ATHUB; 836 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 837 * as a consequence, the rev_id and external_rev_id are wrong. 838 * workaround it by hardcoding rev_id to 0 (default value). 839 */ 840 if (amdgpu_sriov_vf(adev)) 841 adev->rev_id = 0; 842 adev->external_rev_id = adev->rev_id + 0xa; 843 break; 844 case CHIP_SIENNA_CICHLID: 845 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 846 AMD_CG_SUPPORT_GFX_CGCG | 847 AMD_CG_SUPPORT_GFX_3D_CGCG | 848 AMD_CG_SUPPORT_MC_MGCG | 849 AMD_CG_SUPPORT_VCN_MGCG | 850 AMD_CG_SUPPORT_JPEG_MGCG | 851 AMD_CG_SUPPORT_HDP_MGCG | 852 AMD_CG_SUPPORT_HDP_LS | 853 AMD_CG_SUPPORT_IH_CG | 854 AMD_CG_SUPPORT_MC_LS; 855 adev->pg_flags = AMD_PG_SUPPORT_VCN | 856 AMD_PG_SUPPORT_VCN_DPG | 857 AMD_PG_SUPPORT_JPEG | 858 AMD_PG_SUPPORT_ATHUB | 859 AMD_PG_SUPPORT_MMHUB; 860 if (amdgpu_sriov_vf(adev)) { 861 /* hypervisor control CG and PG enablement */ 862 adev->cg_flags = 0; 863 adev->pg_flags = 0; 864 } 865 adev->external_rev_id = adev->rev_id + 0x28; 866 break; 867 case CHIP_NAVY_FLOUNDER: 868 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 869 AMD_CG_SUPPORT_GFX_CGCG | 870 AMD_CG_SUPPORT_GFX_3D_CGCG | 871 AMD_CG_SUPPORT_VCN_MGCG | 872 AMD_CG_SUPPORT_JPEG_MGCG | 873 AMD_CG_SUPPORT_MC_MGCG | 874 AMD_CG_SUPPORT_MC_LS | 875 AMD_CG_SUPPORT_HDP_MGCG | 876 AMD_CG_SUPPORT_HDP_LS | 877 AMD_CG_SUPPORT_IH_CG; 878 adev->pg_flags = AMD_PG_SUPPORT_VCN | 879 AMD_PG_SUPPORT_VCN_DPG | 880 AMD_PG_SUPPORT_JPEG | 881 AMD_PG_SUPPORT_ATHUB | 882 AMD_PG_SUPPORT_MMHUB; 883 adev->external_rev_id = adev->rev_id + 0x32; 884 break; 885 886 case CHIP_VANGOGH: 887 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 888 AMD_CG_SUPPORT_GFX_CGLS | 889 AMD_CG_SUPPORT_GFX_3D_CGCG | 890 AMD_CG_SUPPORT_GFX_3D_CGLS; 891 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG; 892 adev->external_rev_id = adev->rev_id + 0x01; 893 break; 894 default: 895 /* FIXME: not supported yet */ 896 return -EINVAL; 897 } 898 899 if (amdgpu_sriov_vf(adev)) { 900 amdgpu_virt_init_setting(adev); 901 xgpu_nv_mailbox_set_irq_funcs(adev); 902 } 903 904 return 0; 905 } 906 907 static int nv_common_late_init(void *handle) 908 { 909 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 910 911 if (amdgpu_sriov_vf(adev)) 912 xgpu_nv_mailbox_get_irq(adev); 913 914 return 0; 915 } 916 917 static int nv_common_sw_init(void *handle) 918 { 919 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 920 921 if (amdgpu_sriov_vf(adev)) 922 xgpu_nv_mailbox_add_irq_id(adev); 923 924 return 0; 925 } 926 927 static int nv_common_sw_fini(void *handle) 928 { 929 return 0; 930 } 931 932 static int nv_common_hw_init(void *handle) 933 { 934 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 935 936 /* enable pcie gen2/3 link */ 937 nv_pcie_gen3_enable(adev); 938 /* enable aspm */ 939 nv_program_aspm(adev); 940 /* setup nbio registers */ 941 adev->nbio.funcs->init_registers(adev); 942 /* remap HDP registers to a hole in mmio space, 943 * for the purpose of expose those registers 944 * to process space 945 */ 946 if (adev->nbio.funcs->remap_hdp_registers) 947 adev->nbio.funcs->remap_hdp_registers(adev); 948 /* enable the doorbell aperture */ 949 nv_enable_doorbell_aperture(adev, true); 950 951 return 0; 952 } 953 954 static int nv_common_hw_fini(void *handle) 955 { 956 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 957 958 /* disable the doorbell aperture */ 959 nv_enable_doorbell_aperture(adev, false); 960 961 return 0; 962 } 963 964 static int nv_common_suspend(void *handle) 965 { 966 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 967 968 return nv_common_hw_fini(adev); 969 } 970 971 static int nv_common_resume(void *handle) 972 { 973 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 974 975 return nv_common_hw_init(adev); 976 } 977 978 static bool nv_common_is_idle(void *handle) 979 { 980 return true; 981 } 982 983 static int nv_common_wait_for_idle(void *handle) 984 { 985 return 0; 986 } 987 988 static int nv_common_soft_reset(void *handle) 989 { 990 return 0; 991 } 992 993 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 994 bool enable) 995 { 996 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 997 uint32_t hdp_mem_pwr_cntl; 998 999 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 1000 AMD_CG_SUPPORT_HDP_DS | 1001 AMD_CG_SUPPORT_HDP_SD))) 1002 return; 1003 1004 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1005 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1006 1007 /* Before doing clock/power mode switch, 1008 * forced on IPH & RC clock */ 1009 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 1010 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 1011 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 1012 RC_MEM_CLK_SOFT_OVERRIDE, 1); 1013 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1014 1015 /* HDP 5.0 doesn't support dynamic power mode switch, 1016 * disable clock and power gating before any changing */ 1017 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1018 IPH_MEM_POWER_CTRL_EN, 0); 1019 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1020 IPH_MEM_POWER_LS_EN, 0); 1021 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1022 IPH_MEM_POWER_DS_EN, 0); 1023 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1024 IPH_MEM_POWER_SD_EN, 0); 1025 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1026 RC_MEM_POWER_CTRL_EN, 0); 1027 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1028 RC_MEM_POWER_LS_EN, 0); 1029 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1030 RC_MEM_POWER_DS_EN, 0); 1031 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1032 RC_MEM_POWER_SD_EN, 0); 1033 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1034 1035 /* only one clock gating mode (LS/DS/SD) can be enabled */ 1036 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1037 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1038 HDP_MEM_POWER_CTRL, 1039 IPH_MEM_POWER_LS_EN, enable); 1040 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1041 HDP_MEM_POWER_CTRL, 1042 RC_MEM_POWER_LS_EN, enable); 1043 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 1044 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1045 HDP_MEM_POWER_CTRL, 1046 IPH_MEM_POWER_DS_EN, enable); 1047 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1048 HDP_MEM_POWER_CTRL, 1049 RC_MEM_POWER_DS_EN, enable); 1050 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 1051 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1052 HDP_MEM_POWER_CTRL, 1053 IPH_MEM_POWER_SD_EN, enable); 1054 /* RC should not use shut down mode, fallback to ds */ 1055 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1056 HDP_MEM_POWER_CTRL, 1057 RC_MEM_POWER_DS_EN, enable); 1058 } 1059 1060 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 1061 * be set for SRAM LS/DS/SD */ 1062 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 1063 AMD_CG_SUPPORT_HDP_SD)) { 1064 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1065 IPH_MEM_POWER_CTRL_EN, 1); 1066 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1067 RC_MEM_POWER_CTRL_EN, 1); 1068 } 1069 1070 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1071 1072 /* restore IPH & RC clock override after clock/power mode changing */ 1073 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 1074 } 1075 1076 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 1077 bool enable) 1078 { 1079 uint32_t hdp_clk_cntl; 1080 1081 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1082 return; 1083 1084 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1085 1086 if (enable) { 1087 hdp_clk_cntl &= 1088 ~(uint32_t) 1089 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1090 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1091 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1092 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1093 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1094 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 1095 } else { 1096 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1097 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1098 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1099 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1100 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1101 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 1102 } 1103 1104 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1105 } 1106 1107 static int nv_common_set_clockgating_state(void *handle, 1108 enum amd_clockgating_state state) 1109 { 1110 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1111 1112 if (amdgpu_sriov_vf(adev)) 1113 return 0; 1114 1115 switch (adev->asic_type) { 1116 case CHIP_NAVI10: 1117 case CHIP_NAVI14: 1118 case CHIP_NAVI12: 1119 case CHIP_SIENNA_CICHLID: 1120 case CHIP_NAVY_FLOUNDER: 1121 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1122 state == AMD_CG_STATE_GATE); 1123 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1124 state == AMD_CG_STATE_GATE); 1125 nv_update_hdp_mem_power_gating(adev, 1126 state == AMD_CG_STATE_GATE); 1127 nv_update_hdp_clock_gating(adev, 1128 state == AMD_CG_STATE_GATE); 1129 break; 1130 default: 1131 break; 1132 } 1133 return 0; 1134 } 1135 1136 static int nv_common_set_powergating_state(void *handle, 1137 enum amd_powergating_state state) 1138 { 1139 /* TODO */ 1140 return 0; 1141 } 1142 1143 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1144 { 1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1146 uint32_t tmp; 1147 1148 if (amdgpu_sriov_vf(adev)) 1149 *flags = 0; 1150 1151 adev->nbio.funcs->get_clockgating_state(adev, flags); 1152 1153 /* AMD_CG_SUPPORT_HDP_MGCG */ 1154 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1155 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1156 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1157 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1158 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1159 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1160 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 1161 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1162 1163 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 1164 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1165 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 1166 *flags |= AMD_CG_SUPPORT_HDP_LS; 1167 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1168 *flags |= AMD_CG_SUPPORT_HDP_DS; 1169 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1170 *flags |= AMD_CG_SUPPORT_HDP_SD; 1171 1172 return; 1173 } 1174 1175 static const struct amd_ip_funcs nv_common_ip_funcs = { 1176 .name = "nv_common", 1177 .early_init = nv_common_early_init, 1178 .late_init = nv_common_late_init, 1179 .sw_init = nv_common_sw_init, 1180 .sw_fini = nv_common_sw_fini, 1181 .hw_init = nv_common_hw_init, 1182 .hw_fini = nv_common_hw_fini, 1183 .suspend = nv_common_suspend, 1184 .resume = nv_common_resume, 1185 .is_idle = nv_common_is_idle, 1186 .wait_for_idle = nv_common_wait_for_idle, 1187 .soft_reset = nv_common_soft_reset, 1188 .set_clockgating_state = nv_common_set_clockgating_state, 1189 .set_powergating_state = nv_common_set_powergating_state, 1190 .get_clockgating_state = nv_common_get_clockgating_state, 1191 }; 1192