1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 74 }; 75 76 static const struct amdgpu_video_codecs nv_video_codecs_encode = 77 { 78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 79 .codec_array = nv_video_codecs_encode_array, 80 }; 81 82 /* Navi1x */ 83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 92 }; 93 94 static const struct amdgpu_video_codecs nv_video_codecs_decode = 95 { 96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 97 .codec_array = nv_video_codecs_decode_array, 98 }; 99 100 /* Sienna Cichlid */ 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 102 { 103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 104 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 111 }; 112 113 static const struct amdgpu_video_codecs sc_video_codecs_decode = 114 { 115 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 116 .codec_array = sc_video_codecs_decode_array, 117 }; 118 119 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 120 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 121 { 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 124 }; 125 126 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = 127 { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136 }; 137 138 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 139 { 140 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 141 .codec_array = sriov_sc_video_codecs_encode_array, 142 }; 143 144 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = 145 { 146 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), 147 .codec_array = sriov_sc_video_codecs_decode_array, 148 }; 149 150 /* Beige Goby*/ 151 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 153 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 154 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 155 }; 156 157 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 158 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 159 .codec_array = bg_video_codecs_decode_array, 160 }; 161 162 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 163 .codec_count = 0, 164 .codec_array = NULL, 165 }; 166 167 /* Yellow Carp*/ 168 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 169 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 170 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 171 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 172 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 173 }; 174 175 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 176 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 177 .codec_array = yc_video_codecs_decode_array, 178 }; 179 180 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 181 const struct amdgpu_video_codecs **codecs) 182 { 183 switch (adev->ip_versions[UVD_HWIP][0]) { 184 case IP_VERSION(3, 0, 0): 185 case IP_VERSION(3, 0, 64): 186 case IP_VERSION(3, 0, 192): 187 if (amdgpu_sriov_vf(adev)) { 188 if (encode) 189 *codecs = &sriov_sc_video_codecs_encode; 190 else 191 *codecs = &sriov_sc_video_codecs_decode; 192 } else { 193 if (encode) 194 *codecs = &nv_video_codecs_encode; 195 else 196 *codecs = &sc_video_codecs_decode; 197 } 198 return 0; 199 case IP_VERSION(3, 0, 16): 200 case IP_VERSION(3, 0, 2): 201 if (encode) 202 *codecs = &nv_video_codecs_encode; 203 else 204 *codecs = &sc_video_codecs_decode; 205 return 0; 206 case IP_VERSION(3, 1, 1): 207 case IP_VERSION(3, 1, 2): 208 if (encode) 209 *codecs = &nv_video_codecs_encode; 210 else 211 *codecs = &yc_video_codecs_decode; 212 return 0; 213 case IP_VERSION(3, 0, 33): 214 if (encode) 215 *codecs = &bg_video_codecs_encode; 216 else 217 *codecs = &bg_video_codecs_decode; 218 return 0; 219 case IP_VERSION(2, 0, 0): 220 case IP_VERSION(2, 0, 2): 221 if (encode) 222 *codecs = &nv_video_codecs_encode; 223 else 224 *codecs = &nv_video_codecs_decode; 225 return 0; 226 default: 227 return -EINVAL; 228 } 229 } 230 231 /* 232 * Indirect registers accessor 233 */ 234 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 235 { 236 unsigned long address, data; 237 address = adev->nbio.funcs->get_pcie_index_offset(adev); 238 data = adev->nbio.funcs->get_pcie_data_offset(adev); 239 240 return amdgpu_device_indirect_rreg(adev, address, data, reg); 241 } 242 243 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 244 { 245 unsigned long address, data; 246 247 address = adev->nbio.funcs->get_pcie_index_offset(adev); 248 data = adev->nbio.funcs->get_pcie_data_offset(adev); 249 250 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 251 } 252 253 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 254 { 255 unsigned long address, data; 256 address = adev->nbio.funcs->get_pcie_index_offset(adev); 257 data = adev->nbio.funcs->get_pcie_data_offset(adev); 258 259 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 260 } 261 262 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 263 { 264 unsigned long address, data; 265 266 address = adev->nbio.funcs->get_pcie_index_offset(adev); 267 data = adev->nbio.funcs->get_pcie_data_offset(adev); 268 269 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 270 } 271 272 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 273 { 274 unsigned long flags, address, data; 275 u32 r; 276 277 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 278 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 279 280 spin_lock_irqsave(&adev->didt_idx_lock, flags); 281 WREG32(address, (reg)); 282 r = RREG32(data); 283 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 284 return r; 285 } 286 287 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 288 { 289 unsigned long flags, address, data; 290 291 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 292 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 293 294 spin_lock_irqsave(&adev->didt_idx_lock, flags); 295 WREG32(address, (reg)); 296 WREG32(data, (v)); 297 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 298 } 299 300 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 301 { 302 return adev->nbio.funcs->get_memsize(adev); 303 } 304 305 static u32 nv_get_xclk(struct amdgpu_device *adev) 306 { 307 return adev->clock.spll.reference_freq; 308 } 309 310 311 void nv_grbm_select(struct amdgpu_device *adev, 312 u32 me, u32 pipe, u32 queue, u32 vmid) 313 { 314 u32 grbm_gfx_cntl = 0; 315 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 316 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 317 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 318 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 319 320 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 321 } 322 323 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 324 { 325 /* todo */ 326 } 327 328 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 329 { 330 /* todo */ 331 return false; 332 } 333 334 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 335 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 336 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 340 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 341 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 342 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 343 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 344 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 345 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 346 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 347 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 348 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 349 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 352 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 353 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 354 }; 355 356 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 357 u32 sh_num, u32 reg_offset) 358 { 359 uint32_t val; 360 361 mutex_lock(&adev->grbm_idx_mutex); 362 if (se_num != 0xffffffff || sh_num != 0xffffffff) 363 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 364 365 val = RREG32(reg_offset); 366 367 if (se_num != 0xffffffff || sh_num != 0xffffffff) 368 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 369 mutex_unlock(&adev->grbm_idx_mutex); 370 return val; 371 } 372 373 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 374 bool indexed, u32 se_num, 375 u32 sh_num, u32 reg_offset) 376 { 377 if (indexed) { 378 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 379 } else { 380 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 381 return adev->gfx.config.gb_addr_config; 382 return RREG32(reg_offset); 383 } 384 } 385 386 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 387 u32 sh_num, u32 reg_offset, u32 *value) 388 { 389 uint32_t i; 390 struct soc15_allowed_register_entry *en; 391 392 *value = 0; 393 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 394 en = &nv_allowed_read_registers[i]; 395 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 396 reg_offset != 397 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 398 continue; 399 400 *value = nv_get_register_value(adev, 401 nv_allowed_read_registers[i].grbm_indexed, 402 se_num, sh_num, reg_offset); 403 return 0; 404 } 405 return -EINVAL; 406 } 407 408 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 409 { 410 u32 i; 411 int ret = 0; 412 413 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 414 415 /* disable BM */ 416 pci_clear_master(adev->pdev); 417 418 amdgpu_device_cache_pci_state(adev->pdev); 419 420 ret = amdgpu_dpm_mode2_reset(adev); 421 if (ret) 422 dev_err(adev->dev, "GPU mode2 reset failed\n"); 423 424 amdgpu_device_load_pci_state(adev->pdev); 425 426 /* wait for asic to come out of reset */ 427 for (i = 0; i < adev->usec_timeout; i++) { 428 u32 memsize = adev->nbio.funcs->get_memsize(adev); 429 430 if (memsize != 0xffffffff) 431 break; 432 udelay(1); 433 } 434 435 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 436 437 return ret; 438 } 439 440 static enum amd_reset_method 441 nv_asic_reset_method(struct amdgpu_device *adev) 442 { 443 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 444 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 445 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 446 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 447 return amdgpu_reset_method; 448 449 if (amdgpu_reset_method != -1) 450 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 451 amdgpu_reset_method); 452 453 switch (adev->ip_versions[MP1_HWIP][0]) { 454 case IP_VERSION(11, 5, 0): 455 case IP_VERSION(13, 0, 1): 456 case IP_VERSION(13, 0, 3): 457 return AMD_RESET_METHOD_MODE2; 458 case IP_VERSION(11, 0, 7): 459 case IP_VERSION(11, 0, 11): 460 case IP_VERSION(11, 0, 12): 461 case IP_VERSION(11, 0, 13): 462 return AMD_RESET_METHOD_MODE1; 463 default: 464 if (amdgpu_dpm_is_baco_supported(adev)) 465 return AMD_RESET_METHOD_BACO; 466 else 467 return AMD_RESET_METHOD_MODE1; 468 } 469 } 470 471 static int nv_asic_reset(struct amdgpu_device *adev) 472 { 473 int ret = 0; 474 475 switch (nv_asic_reset_method(adev)) { 476 case AMD_RESET_METHOD_PCI: 477 dev_info(adev->dev, "PCI reset\n"); 478 ret = amdgpu_device_pci_reset(adev); 479 break; 480 case AMD_RESET_METHOD_BACO: 481 dev_info(adev->dev, "BACO reset\n"); 482 ret = amdgpu_dpm_baco_reset(adev); 483 break; 484 case AMD_RESET_METHOD_MODE2: 485 dev_info(adev->dev, "MODE2 reset\n"); 486 ret = nv_asic_mode2_reset(adev); 487 break; 488 default: 489 dev_info(adev->dev, "MODE1 reset\n"); 490 ret = amdgpu_device_mode1_reset(adev); 491 break; 492 } 493 494 return ret; 495 } 496 497 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 498 { 499 /* todo */ 500 return 0; 501 } 502 503 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 504 { 505 /* todo */ 506 return 0; 507 } 508 509 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 510 { 511 if (pci_is_root_bus(adev->pdev->bus)) 512 return; 513 514 if (amdgpu_pcie_gen2 == 0) 515 return; 516 517 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 518 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 519 return; 520 521 /* todo */ 522 } 523 524 static void nv_program_aspm(struct amdgpu_device *adev) 525 { 526 if (!amdgpu_device_should_use_aspm(adev)) 527 return; 528 529 if (!(adev->flags & AMD_IS_APU) && 530 (adev->nbio.funcs->program_aspm)) 531 adev->nbio.funcs->program_aspm(adev); 532 533 } 534 535 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 536 bool enable) 537 { 538 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 539 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 540 } 541 542 const struct amdgpu_ip_block_version nv_common_ip_block = 543 { 544 .type = AMD_IP_BLOCK_TYPE_COMMON, 545 .major = 1, 546 .minor = 0, 547 .rev = 0, 548 .funcs = &nv_common_ip_funcs, 549 }; 550 551 void nv_set_virt_ops(struct amdgpu_device *adev) 552 { 553 adev->virt.ops = &xgpu_nv_virt_ops; 554 } 555 556 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 557 { 558 return adev->nbio.funcs->get_rev_id(adev); 559 } 560 561 static bool nv_need_full_reset(struct amdgpu_device *adev) 562 { 563 return true; 564 } 565 566 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 567 { 568 u32 sol_reg; 569 570 if (adev->flags & AMD_IS_APU) 571 return false; 572 573 /* Check sOS sign of life register to confirm sys driver and sOS 574 * are already been loaded. 575 */ 576 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 577 if (sol_reg) 578 return true; 579 580 return false; 581 } 582 583 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 584 { 585 586 /* TODO 587 * dummy implement for pcie_replay_count sysfs interface 588 * */ 589 590 return 0; 591 } 592 593 static void nv_init_doorbell_index(struct amdgpu_device *adev) 594 { 595 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 596 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 597 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 598 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 599 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 600 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 601 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 602 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 603 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 604 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 605 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 606 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 607 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 608 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 609 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 610 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 611 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 612 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 613 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 614 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 615 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 616 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 617 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 618 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 619 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 620 621 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 622 adev->doorbell_index.sdma_doorbell_range = 20; 623 } 624 625 static void nv_pre_asic_init(struct amdgpu_device *adev) 626 { 627 } 628 629 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 630 bool enter) 631 { 632 if (enter) 633 amdgpu_gfx_rlc_enter_safe_mode(adev); 634 else 635 amdgpu_gfx_rlc_exit_safe_mode(adev); 636 637 if (adev->gfx.funcs->update_perfmon_mgcg) 638 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 639 640 if (!(adev->flags & AMD_IS_APU) && 641 (adev->nbio.funcs->enable_aspm) && 642 amdgpu_device_should_use_aspm(adev)) 643 adev->nbio.funcs->enable_aspm(adev, !enter); 644 645 return 0; 646 } 647 648 static const struct amdgpu_asic_funcs nv_asic_funcs = 649 { 650 .read_disabled_bios = &nv_read_disabled_bios, 651 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 652 .read_register = &nv_read_register, 653 .reset = &nv_asic_reset, 654 .reset_method = &nv_asic_reset_method, 655 .set_vga_state = &nv_vga_set_state, 656 .get_xclk = &nv_get_xclk, 657 .set_uvd_clocks = &nv_set_uvd_clocks, 658 .set_vce_clocks = &nv_set_vce_clocks, 659 .get_config_memsize = &nv_get_config_memsize, 660 .init_doorbell_index = &nv_init_doorbell_index, 661 .need_full_reset = &nv_need_full_reset, 662 .need_reset_on_init = &nv_need_reset_on_init, 663 .get_pcie_replay_count = &nv_get_pcie_replay_count, 664 .supports_baco = &amdgpu_dpm_is_baco_supported, 665 .pre_asic_init = &nv_pre_asic_init, 666 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 667 .query_video_codecs = &nv_query_video_codecs, 668 }; 669 670 static int nv_common_early_init(void *handle) 671 { 672 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 673 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 674 675 if (!amdgpu_sriov_vf(adev)) { 676 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 677 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 678 } 679 adev->smc_rreg = NULL; 680 adev->smc_wreg = NULL; 681 adev->pcie_rreg = &nv_pcie_rreg; 682 adev->pcie_wreg = &nv_pcie_wreg; 683 adev->pcie_rreg64 = &nv_pcie_rreg64; 684 adev->pcie_wreg64 = &nv_pcie_wreg64; 685 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 686 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 687 688 /* TODO: will add them during VCN v2 implementation */ 689 adev->uvd_ctx_rreg = NULL; 690 adev->uvd_ctx_wreg = NULL; 691 692 adev->didt_rreg = &nv_didt_rreg; 693 adev->didt_wreg = &nv_didt_wreg; 694 695 adev->asic_funcs = &nv_asic_funcs; 696 697 adev->rev_id = nv_get_rev_id(adev); 698 adev->external_rev_id = 0xff; 699 /* TODO: split the GC and PG flags based on the relevant IP version for which 700 * they are relevant. 701 */ 702 switch (adev->ip_versions[GC_HWIP][0]) { 703 case IP_VERSION(10, 1, 10): 704 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 705 AMD_CG_SUPPORT_GFX_CGCG | 706 AMD_CG_SUPPORT_IH_CG | 707 AMD_CG_SUPPORT_HDP_MGCG | 708 AMD_CG_SUPPORT_HDP_LS | 709 AMD_CG_SUPPORT_SDMA_MGCG | 710 AMD_CG_SUPPORT_SDMA_LS | 711 AMD_CG_SUPPORT_MC_MGCG | 712 AMD_CG_SUPPORT_MC_LS | 713 AMD_CG_SUPPORT_ATHUB_MGCG | 714 AMD_CG_SUPPORT_ATHUB_LS | 715 AMD_CG_SUPPORT_VCN_MGCG | 716 AMD_CG_SUPPORT_JPEG_MGCG | 717 AMD_CG_SUPPORT_BIF_MGCG | 718 AMD_CG_SUPPORT_BIF_LS; 719 adev->pg_flags = AMD_PG_SUPPORT_VCN | 720 AMD_PG_SUPPORT_VCN_DPG | 721 AMD_PG_SUPPORT_JPEG | 722 AMD_PG_SUPPORT_ATHUB; 723 adev->external_rev_id = adev->rev_id + 0x1; 724 break; 725 case IP_VERSION(10, 1, 1): 726 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 727 AMD_CG_SUPPORT_GFX_CGCG | 728 AMD_CG_SUPPORT_IH_CG | 729 AMD_CG_SUPPORT_HDP_MGCG | 730 AMD_CG_SUPPORT_HDP_LS | 731 AMD_CG_SUPPORT_SDMA_MGCG | 732 AMD_CG_SUPPORT_SDMA_LS | 733 AMD_CG_SUPPORT_MC_MGCG | 734 AMD_CG_SUPPORT_MC_LS | 735 AMD_CG_SUPPORT_ATHUB_MGCG | 736 AMD_CG_SUPPORT_ATHUB_LS | 737 AMD_CG_SUPPORT_VCN_MGCG | 738 AMD_CG_SUPPORT_JPEG_MGCG | 739 AMD_CG_SUPPORT_BIF_MGCG | 740 AMD_CG_SUPPORT_BIF_LS; 741 adev->pg_flags = AMD_PG_SUPPORT_VCN | 742 AMD_PG_SUPPORT_JPEG | 743 AMD_PG_SUPPORT_VCN_DPG; 744 adev->external_rev_id = adev->rev_id + 20; 745 break; 746 case IP_VERSION(10, 1, 2): 747 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 748 AMD_CG_SUPPORT_GFX_MGLS | 749 AMD_CG_SUPPORT_GFX_CGCG | 750 AMD_CG_SUPPORT_GFX_CP_LS | 751 AMD_CG_SUPPORT_GFX_RLC_LS | 752 AMD_CG_SUPPORT_IH_CG | 753 AMD_CG_SUPPORT_HDP_MGCG | 754 AMD_CG_SUPPORT_HDP_LS | 755 AMD_CG_SUPPORT_SDMA_MGCG | 756 AMD_CG_SUPPORT_SDMA_LS | 757 AMD_CG_SUPPORT_MC_MGCG | 758 AMD_CG_SUPPORT_MC_LS | 759 AMD_CG_SUPPORT_ATHUB_MGCG | 760 AMD_CG_SUPPORT_ATHUB_LS | 761 AMD_CG_SUPPORT_VCN_MGCG | 762 AMD_CG_SUPPORT_JPEG_MGCG; 763 adev->pg_flags = AMD_PG_SUPPORT_VCN | 764 AMD_PG_SUPPORT_VCN_DPG | 765 AMD_PG_SUPPORT_JPEG | 766 AMD_PG_SUPPORT_ATHUB; 767 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 768 * as a consequence, the rev_id and external_rev_id are wrong. 769 * workaround it by hardcoding rev_id to 0 (default value). 770 */ 771 if (amdgpu_sriov_vf(adev)) 772 adev->rev_id = 0; 773 adev->external_rev_id = adev->rev_id + 0xa; 774 break; 775 case IP_VERSION(10, 3, 0): 776 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 777 AMD_CG_SUPPORT_GFX_CGCG | 778 AMD_CG_SUPPORT_GFX_CGLS | 779 AMD_CG_SUPPORT_GFX_3D_CGCG | 780 AMD_CG_SUPPORT_MC_MGCG | 781 AMD_CG_SUPPORT_VCN_MGCG | 782 AMD_CG_SUPPORT_JPEG_MGCG | 783 AMD_CG_SUPPORT_HDP_MGCG | 784 AMD_CG_SUPPORT_HDP_LS | 785 AMD_CG_SUPPORT_IH_CG | 786 AMD_CG_SUPPORT_MC_LS; 787 adev->pg_flags = AMD_PG_SUPPORT_VCN | 788 AMD_PG_SUPPORT_VCN_DPG | 789 AMD_PG_SUPPORT_JPEG | 790 AMD_PG_SUPPORT_ATHUB | 791 AMD_PG_SUPPORT_MMHUB; 792 if (amdgpu_sriov_vf(adev)) { 793 /* hypervisor control CG and PG enablement */ 794 adev->cg_flags = 0; 795 adev->pg_flags = 0; 796 } 797 adev->external_rev_id = adev->rev_id + 0x28; 798 break; 799 case IP_VERSION(10, 3, 2): 800 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 801 AMD_CG_SUPPORT_GFX_CGCG | 802 AMD_CG_SUPPORT_GFX_CGLS | 803 AMD_CG_SUPPORT_GFX_3D_CGCG | 804 AMD_CG_SUPPORT_VCN_MGCG | 805 AMD_CG_SUPPORT_JPEG_MGCG | 806 AMD_CG_SUPPORT_MC_MGCG | 807 AMD_CG_SUPPORT_MC_LS | 808 AMD_CG_SUPPORT_HDP_MGCG | 809 AMD_CG_SUPPORT_HDP_LS | 810 AMD_CG_SUPPORT_IH_CG; 811 adev->pg_flags = AMD_PG_SUPPORT_VCN | 812 AMD_PG_SUPPORT_VCN_DPG | 813 AMD_PG_SUPPORT_JPEG | 814 AMD_PG_SUPPORT_ATHUB | 815 AMD_PG_SUPPORT_MMHUB; 816 adev->external_rev_id = adev->rev_id + 0x32; 817 break; 818 case IP_VERSION(10, 3, 1): 819 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 820 AMD_CG_SUPPORT_GFX_MGLS | 821 AMD_CG_SUPPORT_GFX_CP_LS | 822 AMD_CG_SUPPORT_GFX_RLC_LS | 823 AMD_CG_SUPPORT_GFX_CGCG | 824 AMD_CG_SUPPORT_GFX_CGLS | 825 AMD_CG_SUPPORT_GFX_3D_CGCG | 826 AMD_CG_SUPPORT_GFX_3D_CGLS | 827 AMD_CG_SUPPORT_MC_MGCG | 828 AMD_CG_SUPPORT_MC_LS | 829 AMD_CG_SUPPORT_GFX_FGCG | 830 AMD_CG_SUPPORT_VCN_MGCG | 831 AMD_CG_SUPPORT_SDMA_MGCG | 832 AMD_CG_SUPPORT_SDMA_LS | 833 AMD_CG_SUPPORT_JPEG_MGCG; 834 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 835 AMD_PG_SUPPORT_VCN | 836 AMD_PG_SUPPORT_VCN_DPG | 837 AMD_PG_SUPPORT_JPEG; 838 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 839 adev->external_rev_id = adev->rev_id + 0x01; 840 break; 841 case IP_VERSION(10, 3, 4): 842 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 843 AMD_CG_SUPPORT_GFX_CGCG | 844 AMD_CG_SUPPORT_GFX_CGLS | 845 AMD_CG_SUPPORT_GFX_3D_CGCG | 846 AMD_CG_SUPPORT_VCN_MGCG | 847 AMD_CG_SUPPORT_JPEG_MGCG | 848 AMD_CG_SUPPORT_MC_MGCG | 849 AMD_CG_SUPPORT_MC_LS | 850 AMD_CG_SUPPORT_HDP_MGCG | 851 AMD_CG_SUPPORT_HDP_LS | 852 AMD_CG_SUPPORT_IH_CG; 853 adev->pg_flags = AMD_PG_SUPPORT_VCN | 854 AMD_PG_SUPPORT_VCN_DPG | 855 AMD_PG_SUPPORT_JPEG | 856 AMD_PG_SUPPORT_ATHUB | 857 AMD_PG_SUPPORT_MMHUB; 858 adev->external_rev_id = adev->rev_id + 0x3c; 859 break; 860 case IP_VERSION(10, 3, 5): 861 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 862 AMD_CG_SUPPORT_GFX_CGCG | 863 AMD_CG_SUPPORT_GFX_CGLS | 864 AMD_CG_SUPPORT_GFX_3D_CGCG | 865 AMD_CG_SUPPORT_MC_MGCG | 866 AMD_CG_SUPPORT_MC_LS | 867 AMD_CG_SUPPORT_HDP_MGCG | 868 AMD_CG_SUPPORT_HDP_LS | 869 AMD_CG_SUPPORT_IH_CG | 870 AMD_CG_SUPPORT_VCN_MGCG; 871 adev->pg_flags = AMD_PG_SUPPORT_VCN | 872 AMD_PG_SUPPORT_VCN_DPG | 873 AMD_PG_SUPPORT_ATHUB | 874 AMD_PG_SUPPORT_MMHUB; 875 adev->external_rev_id = adev->rev_id + 0x46; 876 break; 877 case IP_VERSION(10, 3, 3): 878 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 879 AMD_CG_SUPPORT_GFX_MGLS | 880 AMD_CG_SUPPORT_GFX_CGCG | 881 AMD_CG_SUPPORT_GFX_CGLS | 882 AMD_CG_SUPPORT_GFX_3D_CGCG | 883 AMD_CG_SUPPORT_GFX_3D_CGLS | 884 AMD_CG_SUPPORT_GFX_RLC_LS | 885 AMD_CG_SUPPORT_GFX_CP_LS | 886 AMD_CG_SUPPORT_GFX_FGCG | 887 AMD_CG_SUPPORT_MC_MGCG | 888 AMD_CG_SUPPORT_MC_LS | 889 AMD_CG_SUPPORT_SDMA_LS | 890 AMD_CG_SUPPORT_HDP_MGCG | 891 AMD_CG_SUPPORT_HDP_LS | 892 AMD_CG_SUPPORT_ATHUB_MGCG | 893 AMD_CG_SUPPORT_ATHUB_LS | 894 AMD_CG_SUPPORT_IH_CG | 895 AMD_CG_SUPPORT_VCN_MGCG | 896 AMD_CG_SUPPORT_JPEG_MGCG; 897 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 898 AMD_PG_SUPPORT_VCN | 899 AMD_PG_SUPPORT_VCN_DPG | 900 AMD_PG_SUPPORT_JPEG; 901 if (adev->pdev->device == 0x1681) 902 adev->external_rev_id = 0x20; 903 else 904 adev->external_rev_id = adev->rev_id + 0x01; 905 break; 906 case IP_VERSION(10, 1, 3): 907 case IP_VERSION(10, 1, 4): 908 adev->cg_flags = 0; 909 adev->pg_flags = 0; 910 adev->external_rev_id = adev->rev_id + 0x82; 911 break; 912 case IP_VERSION(10, 3, 6): 913 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 914 AMD_CG_SUPPORT_GFX_MGLS | 915 AMD_CG_SUPPORT_GFX_CGCG | 916 AMD_CG_SUPPORT_GFX_CGLS | 917 AMD_CG_SUPPORT_GFX_3D_CGCG | 918 AMD_CG_SUPPORT_GFX_3D_CGLS | 919 AMD_CG_SUPPORT_GFX_RLC_LS | 920 AMD_CG_SUPPORT_GFX_CP_LS | 921 AMD_CG_SUPPORT_GFX_FGCG | 922 AMD_CG_SUPPORT_MC_MGCG | 923 AMD_CG_SUPPORT_MC_LS | 924 AMD_CG_SUPPORT_SDMA_LS | 925 AMD_CG_SUPPORT_HDP_MGCG | 926 AMD_CG_SUPPORT_HDP_LS | 927 AMD_CG_SUPPORT_ATHUB_MGCG | 928 AMD_CG_SUPPORT_ATHUB_LS | 929 AMD_CG_SUPPORT_IH_CG | 930 AMD_CG_SUPPORT_VCN_MGCG | 931 AMD_CG_SUPPORT_JPEG_MGCG; 932 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 933 AMD_PG_SUPPORT_VCN | 934 AMD_PG_SUPPORT_VCN_DPG | 935 AMD_PG_SUPPORT_JPEG; 936 adev->external_rev_id = adev->rev_id + 0x01; 937 break; 938 case IP_VERSION(10, 3, 7): 939 adev->cg_flags = 0; 940 adev->pg_flags = AMD_PG_SUPPORT_VCN | 941 AMD_PG_SUPPORT_VCN_DPG | 942 AMD_PG_SUPPORT_JPEG; 943 adev->external_rev_id = adev->rev_id + 0x01; 944 break; 945 default: 946 /* FIXME: not supported yet */ 947 return -EINVAL; 948 } 949 950 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 951 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 952 AMD_PG_SUPPORT_VCN_DPG | 953 AMD_PG_SUPPORT_JPEG); 954 955 if (amdgpu_sriov_vf(adev)) { 956 amdgpu_virt_init_setting(adev); 957 xgpu_nv_mailbox_set_irq_funcs(adev); 958 } 959 960 return 0; 961 } 962 963 static int nv_common_late_init(void *handle) 964 { 965 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 966 967 if (amdgpu_sriov_vf(adev)) { 968 xgpu_nv_mailbox_get_irq(adev); 969 amdgpu_virt_update_sriov_video_codec(adev, 970 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 971 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); 972 } 973 974 return 0; 975 } 976 977 static int nv_common_sw_init(void *handle) 978 { 979 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 980 981 if (amdgpu_sriov_vf(adev)) 982 xgpu_nv_mailbox_add_irq_id(adev); 983 984 return 0; 985 } 986 987 static int nv_common_sw_fini(void *handle) 988 { 989 return 0; 990 } 991 992 static int nv_common_hw_init(void *handle) 993 { 994 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 995 996 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 997 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 998 999 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1000 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1001 1002 /* enable pcie gen2/3 link */ 1003 nv_pcie_gen3_enable(adev); 1004 /* enable aspm */ 1005 nv_program_aspm(adev); 1006 /* setup nbio registers */ 1007 adev->nbio.funcs->init_registers(adev); 1008 /* remap HDP registers to a hole in mmio space, 1009 * for the purpose of expose those registers 1010 * to process space 1011 */ 1012 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1013 adev->nbio.funcs->remap_hdp_registers(adev); 1014 /* enable the doorbell aperture */ 1015 nv_enable_doorbell_aperture(adev, true); 1016 1017 return 0; 1018 } 1019 1020 static int nv_common_hw_fini(void *handle) 1021 { 1022 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1023 1024 /* disable the doorbell aperture */ 1025 nv_enable_doorbell_aperture(adev, false); 1026 1027 return 0; 1028 } 1029 1030 static int nv_common_suspend(void *handle) 1031 { 1032 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1033 1034 return nv_common_hw_fini(adev); 1035 } 1036 1037 static int nv_common_resume(void *handle) 1038 { 1039 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1040 1041 return nv_common_hw_init(adev); 1042 } 1043 1044 static bool nv_common_is_idle(void *handle) 1045 { 1046 return true; 1047 } 1048 1049 static int nv_common_wait_for_idle(void *handle) 1050 { 1051 return 0; 1052 } 1053 1054 static int nv_common_soft_reset(void *handle) 1055 { 1056 return 0; 1057 } 1058 1059 static int nv_common_set_clockgating_state(void *handle, 1060 enum amd_clockgating_state state) 1061 { 1062 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1063 1064 if (amdgpu_sriov_vf(adev)) 1065 return 0; 1066 1067 switch (adev->ip_versions[NBIO_HWIP][0]) { 1068 case IP_VERSION(2, 3, 0): 1069 case IP_VERSION(2, 3, 1): 1070 case IP_VERSION(2, 3, 2): 1071 case IP_VERSION(3, 3, 0): 1072 case IP_VERSION(3, 3, 1): 1073 case IP_VERSION(3, 3, 2): 1074 case IP_VERSION(3, 3, 3): 1075 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1076 state == AMD_CG_STATE_GATE); 1077 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1078 state == AMD_CG_STATE_GATE); 1079 adev->hdp.funcs->update_clock_gating(adev, 1080 state == AMD_CG_STATE_GATE); 1081 adev->smuio.funcs->update_rom_clock_gating(adev, 1082 state == AMD_CG_STATE_GATE); 1083 break; 1084 default: 1085 break; 1086 } 1087 return 0; 1088 } 1089 1090 static int nv_common_set_powergating_state(void *handle, 1091 enum amd_powergating_state state) 1092 { 1093 /* TODO */ 1094 return 0; 1095 } 1096 1097 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1098 { 1099 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1100 1101 if (amdgpu_sriov_vf(adev)) 1102 *flags = 0; 1103 1104 adev->nbio.funcs->get_clockgating_state(adev, flags); 1105 1106 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1107 1108 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1109 1110 return; 1111 } 1112 1113 static const struct amd_ip_funcs nv_common_ip_funcs = { 1114 .name = "nv_common", 1115 .early_init = nv_common_early_init, 1116 .late_init = nv_common_late_init, 1117 .sw_init = nv_common_sw_init, 1118 .sw_fini = nv_common_sw_fini, 1119 .hw_init = nv_common_hw_init, 1120 .hw_fini = nv_common_hw_fini, 1121 .suspend = nv_common_suspend, 1122 .resume = nv_common_resume, 1123 .is_idle = nv_common_is_idle, 1124 .wait_for_idle = nv_common_wait_for_idle, 1125 .soft_reset = nv_common_soft_reset, 1126 .set_clockgating_state = nv_common_set_clockgating_state, 1127 .set_powergating_state = nv_common_set_powergating_state, 1128 .get_clockgating_state = nv_common_get_clockgating_state, 1129 }; 1130