1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 74 }; 75 76 static const struct amdgpu_video_codecs nv_video_codecs_encode = 77 { 78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 79 .codec_array = nv_video_codecs_encode_array, 80 }; 81 82 /* Navi1x */ 83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 92 }; 93 94 static const struct amdgpu_video_codecs nv_video_codecs_decode = 95 { 96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 97 .codec_array = nv_video_codecs_decode_array, 98 }; 99 100 /* Sienna Cichlid */ 101 static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = { 102 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)}, 103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)}, 104 }; 105 106 static const struct amdgpu_video_codecs sc_video_codecs_encode = { 107 .codec_count = ARRAY_SIZE(sc_video_codecs_encode_array), 108 .codec_array = sc_video_codecs_encode_array, 109 }; 110 111 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = 112 { 113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 114 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 115 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 116 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 117 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 118 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 119 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 121 }; 122 123 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = 124 { 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 132 }; 133 134 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = 135 { 136 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0), 137 .codec_array = sc_video_codecs_decode_array_vcn0, 138 }; 139 140 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = 141 { 142 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1), 143 .codec_array = sc_video_codecs_decode_array_vcn1, 144 }; 145 146 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 147 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 148 { 149 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)}, 150 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)}, 151 }; 152 153 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = 154 { 155 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 162 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 163 }; 164 165 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = 166 { 167 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 168 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 169 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 170 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 171 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 172 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 173 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 174 }; 175 176 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 177 { 178 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 179 .codec_array = sriov_sc_video_codecs_encode_array, 180 }; 181 182 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = 183 { 184 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0), 185 .codec_array = sriov_sc_video_codecs_decode_array_vcn0, 186 }; 187 188 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = 189 { 190 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1), 191 .codec_array = sriov_sc_video_codecs_decode_array_vcn1, 192 }; 193 194 /* Beige Goby*/ 195 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 196 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 197 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 198 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 199 }; 200 201 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 202 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 203 .codec_array = bg_video_codecs_decode_array, 204 }; 205 206 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 207 .codec_count = 0, 208 .codec_array = NULL, 209 }; 210 211 /* Yellow Carp*/ 212 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 213 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 214 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 215 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 216 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 217 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 218 }; 219 220 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 221 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 222 .codec_array = yc_video_codecs_decode_array, 223 }; 224 225 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 226 const struct amdgpu_video_codecs **codecs) 227 { 228 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 229 return -EINVAL; 230 231 switch (adev->ip_versions[UVD_HWIP][0]) { 232 case IP_VERSION(3, 0, 0): 233 case IP_VERSION(3, 0, 64): 234 case IP_VERSION(3, 0, 192): 235 if (amdgpu_sriov_vf(adev)) { 236 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 237 if (encode) 238 *codecs = &sriov_sc_video_codecs_encode; 239 else 240 *codecs = &sriov_sc_video_codecs_decode_vcn1; 241 } else { 242 if (encode) 243 *codecs = &sriov_sc_video_codecs_encode; 244 else 245 *codecs = &sriov_sc_video_codecs_decode_vcn0; 246 } 247 } else { 248 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 249 if (encode) 250 *codecs = &sc_video_codecs_encode; 251 else 252 *codecs = &sc_video_codecs_decode_vcn1; 253 } else { 254 if (encode) 255 *codecs = &sc_video_codecs_encode; 256 else 257 *codecs = &sc_video_codecs_decode_vcn0; 258 } 259 } 260 return 0; 261 case IP_VERSION(3, 0, 16): 262 case IP_VERSION(3, 0, 2): 263 if (encode) 264 *codecs = &sc_video_codecs_encode; 265 else 266 *codecs = &sc_video_codecs_decode_vcn0; 267 return 0; 268 case IP_VERSION(3, 1, 1): 269 case IP_VERSION(3, 1, 2): 270 if (encode) 271 *codecs = &sc_video_codecs_encode; 272 else 273 *codecs = &yc_video_codecs_decode; 274 return 0; 275 case IP_VERSION(3, 0, 33): 276 if (encode) 277 *codecs = &bg_video_codecs_encode; 278 else 279 *codecs = &bg_video_codecs_decode; 280 return 0; 281 case IP_VERSION(2, 0, 0): 282 case IP_VERSION(2, 0, 2): 283 if (encode) 284 *codecs = &nv_video_codecs_encode; 285 else 286 *codecs = &nv_video_codecs_decode; 287 return 0; 288 default: 289 return -EINVAL; 290 } 291 } 292 293 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 294 { 295 unsigned long flags, address, data; 296 u32 r; 297 298 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 299 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 300 301 spin_lock_irqsave(&adev->didt_idx_lock, flags); 302 WREG32(address, (reg)); 303 r = RREG32(data); 304 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 305 return r; 306 } 307 308 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 309 { 310 unsigned long flags, address, data; 311 312 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 313 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 314 315 spin_lock_irqsave(&adev->didt_idx_lock, flags); 316 WREG32(address, (reg)); 317 WREG32(data, (v)); 318 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 319 } 320 321 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 322 { 323 return adev->nbio.funcs->get_memsize(adev); 324 } 325 326 static u32 nv_get_xclk(struct amdgpu_device *adev) 327 { 328 return adev->clock.spll.reference_freq; 329 } 330 331 332 void nv_grbm_select(struct amdgpu_device *adev, 333 u32 me, u32 pipe, u32 queue, u32 vmid) 334 { 335 u32 grbm_gfx_cntl = 0; 336 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 337 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 338 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 339 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 340 341 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 342 } 343 344 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 345 { 346 /* todo */ 347 } 348 349 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 350 { 351 /* todo */ 352 return false; 353 } 354 355 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 356 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 357 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 358 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 359 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 360 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 361 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 362 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 363 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 364 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 365 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 366 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 367 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 368 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 369 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 370 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 371 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 372 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 373 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 374 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 375 }; 376 377 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 378 u32 sh_num, u32 reg_offset) 379 { 380 uint32_t val; 381 382 mutex_lock(&adev->grbm_idx_mutex); 383 if (se_num != 0xffffffff || sh_num != 0xffffffff) 384 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 385 386 val = RREG32(reg_offset); 387 388 if (se_num != 0xffffffff || sh_num != 0xffffffff) 389 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 390 mutex_unlock(&adev->grbm_idx_mutex); 391 return val; 392 } 393 394 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 395 bool indexed, u32 se_num, 396 u32 sh_num, u32 reg_offset) 397 { 398 if (indexed) { 399 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 400 } else { 401 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 402 return adev->gfx.config.gb_addr_config; 403 return RREG32(reg_offset); 404 } 405 } 406 407 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 408 u32 sh_num, u32 reg_offset, u32 *value) 409 { 410 uint32_t i; 411 struct soc15_allowed_register_entry *en; 412 413 *value = 0; 414 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 415 en = &nv_allowed_read_registers[i]; 416 if (!adev->reg_offset[en->hwip][en->inst]) 417 continue; 418 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 419 + en->reg_offset)) 420 continue; 421 422 *value = nv_get_register_value(adev, 423 nv_allowed_read_registers[i].grbm_indexed, 424 se_num, sh_num, reg_offset); 425 return 0; 426 } 427 return -EINVAL; 428 } 429 430 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 431 { 432 u32 i; 433 int ret = 0; 434 435 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 436 437 /* disable BM */ 438 pci_clear_master(adev->pdev); 439 440 amdgpu_device_cache_pci_state(adev->pdev); 441 442 ret = amdgpu_dpm_mode2_reset(adev); 443 if (ret) 444 dev_err(adev->dev, "GPU mode2 reset failed\n"); 445 446 amdgpu_device_load_pci_state(adev->pdev); 447 448 /* wait for asic to come out of reset */ 449 for (i = 0; i < adev->usec_timeout; i++) { 450 u32 memsize = adev->nbio.funcs->get_memsize(adev); 451 452 if (memsize != 0xffffffff) 453 break; 454 udelay(1); 455 } 456 457 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 458 459 return ret; 460 } 461 462 static enum amd_reset_method 463 nv_asic_reset_method(struct amdgpu_device *adev) 464 { 465 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 466 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 467 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 468 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 469 return amdgpu_reset_method; 470 471 if (amdgpu_reset_method != -1) 472 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 473 amdgpu_reset_method); 474 475 switch (adev->ip_versions[MP1_HWIP][0]) { 476 case IP_VERSION(11, 5, 0): 477 case IP_VERSION(13, 0, 1): 478 case IP_VERSION(13, 0, 3): 479 case IP_VERSION(13, 0, 5): 480 case IP_VERSION(13, 0, 8): 481 return AMD_RESET_METHOD_MODE2; 482 case IP_VERSION(11, 0, 7): 483 case IP_VERSION(11, 0, 11): 484 case IP_VERSION(11, 0, 12): 485 case IP_VERSION(11, 0, 13): 486 return AMD_RESET_METHOD_MODE1; 487 default: 488 if (amdgpu_dpm_is_baco_supported(adev)) 489 return AMD_RESET_METHOD_BACO; 490 else 491 return AMD_RESET_METHOD_MODE1; 492 } 493 } 494 495 static int nv_asic_reset(struct amdgpu_device *adev) 496 { 497 int ret = 0; 498 499 switch (nv_asic_reset_method(adev)) { 500 case AMD_RESET_METHOD_PCI: 501 dev_info(adev->dev, "PCI reset\n"); 502 ret = amdgpu_device_pci_reset(adev); 503 break; 504 case AMD_RESET_METHOD_BACO: 505 dev_info(adev->dev, "BACO reset\n"); 506 ret = amdgpu_dpm_baco_reset(adev); 507 break; 508 case AMD_RESET_METHOD_MODE2: 509 dev_info(adev->dev, "MODE2 reset\n"); 510 ret = nv_asic_mode2_reset(adev); 511 break; 512 default: 513 dev_info(adev->dev, "MODE1 reset\n"); 514 ret = amdgpu_device_mode1_reset(adev); 515 break; 516 } 517 518 return ret; 519 } 520 521 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 522 { 523 /* todo */ 524 return 0; 525 } 526 527 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 528 { 529 /* todo */ 530 return 0; 531 } 532 533 static void nv_program_aspm(struct amdgpu_device *adev) 534 { 535 if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_aspm_support_quirk()) 536 return; 537 538 if (!(adev->flags & AMD_IS_APU) && 539 (adev->nbio.funcs->program_aspm)) 540 adev->nbio.funcs->program_aspm(adev); 541 542 } 543 544 const struct amdgpu_ip_block_version nv_common_ip_block = 545 { 546 .type = AMD_IP_BLOCK_TYPE_COMMON, 547 .major = 1, 548 .minor = 0, 549 .rev = 0, 550 .funcs = &nv_common_ip_funcs, 551 }; 552 553 void nv_set_virt_ops(struct amdgpu_device *adev) 554 { 555 adev->virt.ops = &xgpu_nv_virt_ops; 556 } 557 558 static bool nv_need_full_reset(struct amdgpu_device *adev) 559 { 560 return true; 561 } 562 563 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 564 { 565 u32 sol_reg; 566 567 if (adev->flags & AMD_IS_APU) 568 return false; 569 570 /* Check sOS sign of life register to confirm sys driver and sOS 571 * are already been loaded. 572 */ 573 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 574 if (sol_reg) 575 return true; 576 577 return false; 578 } 579 580 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 581 { 582 583 /* TODO 584 * dummy implement for pcie_replay_count sysfs interface 585 * */ 586 587 return 0; 588 } 589 590 static void nv_init_doorbell_index(struct amdgpu_device *adev) 591 { 592 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 593 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 594 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 595 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 596 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 597 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 598 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 599 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 600 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 601 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 602 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 603 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 604 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 605 adev->doorbell_index.gfx_userqueue_start = 606 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 607 adev->doorbell_index.gfx_userqueue_end = 608 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 609 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 610 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 611 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 612 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 613 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 614 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 615 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 616 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 617 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 618 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 619 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 620 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 621 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 622 623 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 624 adev->doorbell_index.sdma_doorbell_range = 20; 625 } 626 627 static void nv_pre_asic_init(struct amdgpu_device *adev) 628 { 629 } 630 631 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 632 bool enter) 633 { 634 if (enter) 635 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 636 else 637 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 638 639 if (adev->gfx.funcs->update_perfmon_mgcg) 640 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 641 642 if (!(adev->flags & AMD_IS_APU) && 643 (adev->nbio.funcs->enable_aspm) && 644 amdgpu_device_should_use_aspm(adev)) 645 adev->nbio.funcs->enable_aspm(adev, !enter); 646 647 return 0; 648 } 649 650 static const struct amdgpu_asic_funcs nv_asic_funcs = 651 { 652 .read_disabled_bios = &nv_read_disabled_bios, 653 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 654 .read_register = &nv_read_register, 655 .reset = &nv_asic_reset, 656 .reset_method = &nv_asic_reset_method, 657 .set_vga_state = &nv_vga_set_state, 658 .get_xclk = &nv_get_xclk, 659 .set_uvd_clocks = &nv_set_uvd_clocks, 660 .set_vce_clocks = &nv_set_vce_clocks, 661 .get_config_memsize = &nv_get_config_memsize, 662 .init_doorbell_index = &nv_init_doorbell_index, 663 .need_full_reset = &nv_need_full_reset, 664 .need_reset_on_init = &nv_need_reset_on_init, 665 .get_pcie_replay_count = &nv_get_pcie_replay_count, 666 .supports_baco = &amdgpu_dpm_is_baco_supported, 667 .pre_asic_init = &nv_pre_asic_init, 668 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 669 .query_video_codecs = &nv_query_video_codecs, 670 }; 671 672 static int nv_common_early_init(void *handle) 673 { 674 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 675 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 676 677 if (!amdgpu_sriov_vf(adev)) { 678 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 679 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 680 } 681 adev->smc_rreg = NULL; 682 adev->smc_wreg = NULL; 683 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 684 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 685 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 686 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 687 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 688 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 689 690 /* TODO: will add them during VCN v2 implementation */ 691 adev->uvd_ctx_rreg = NULL; 692 adev->uvd_ctx_wreg = NULL; 693 694 adev->didt_rreg = &nv_didt_rreg; 695 adev->didt_wreg = &nv_didt_wreg; 696 697 adev->asic_funcs = &nv_asic_funcs; 698 699 adev->rev_id = amdgpu_device_get_rev_id(adev); 700 adev->external_rev_id = 0xff; 701 /* TODO: split the GC and PG flags based on the relevant IP version for which 702 * they are relevant. 703 */ 704 switch (adev->ip_versions[GC_HWIP][0]) { 705 case IP_VERSION(10, 1, 10): 706 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 707 AMD_CG_SUPPORT_GFX_CGCG | 708 AMD_CG_SUPPORT_IH_CG | 709 AMD_CG_SUPPORT_HDP_MGCG | 710 AMD_CG_SUPPORT_HDP_LS | 711 AMD_CG_SUPPORT_SDMA_MGCG | 712 AMD_CG_SUPPORT_SDMA_LS | 713 AMD_CG_SUPPORT_MC_MGCG | 714 AMD_CG_SUPPORT_MC_LS | 715 AMD_CG_SUPPORT_ATHUB_MGCG | 716 AMD_CG_SUPPORT_ATHUB_LS | 717 AMD_CG_SUPPORT_VCN_MGCG | 718 AMD_CG_SUPPORT_JPEG_MGCG | 719 AMD_CG_SUPPORT_BIF_MGCG | 720 AMD_CG_SUPPORT_BIF_LS; 721 adev->pg_flags = AMD_PG_SUPPORT_VCN | 722 AMD_PG_SUPPORT_VCN_DPG | 723 AMD_PG_SUPPORT_JPEG | 724 AMD_PG_SUPPORT_ATHUB; 725 adev->external_rev_id = adev->rev_id + 0x1; 726 break; 727 case IP_VERSION(10, 1, 1): 728 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 729 AMD_CG_SUPPORT_GFX_CGCG | 730 AMD_CG_SUPPORT_IH_CG | 731 AMD_CG_SUPPORT_HDP_MGCG | 732 AMD_CG_SUPPORT_HDP_LS | 733 AMD_CG_SUPPORT_SDMA_MGCG | 734 AMD_CG_SUPPORT_SDMA_LS | 735 AMD_CG_SUPPORT_MC_MGCG | 736 AMD_CG_SUPPORT_MC_LS | 737 AMD_CG_SUPPORT_ATHUB_MGCG | 738 AMD_CG_SUPPORT_ATHUB_LS | 739 AMD_CG_SUPPORT_VCN_MGCG | 740 AMD_CG_SUPPORT_JPEG_MGCG | 741 AMD_CG_SUPPORT_BIF_MGCG | 742 AMD_CG_SUPPORT_BIF_LS; 743 adev->pg_flags = AMD_PG_SUPPORT_VCN | 744 AMD_PG_SUPPORT_JPEG | 745 AMD_PG_SUPPORT_VCN_DPG; 746 adev->external_rev_id = adev->rev_id + 20; 747 break; 748 case IP_VERSION(10, 1, 2): 749 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 750 AMD_CG_SUPPORT_GFX_MGLS | 751 AMD_CG_SUPPORT_GFX_CGCG | 752 AMD_CG_SUPPORT_GFX_CP_LS | 753 AMD_CG_SUPPORT_GFX_RLC_LS | 754 AMD_CG_SUPPORT_IH_CG | 755 AMD_CG_SUPPORT_HDP_MGCG | 756 AMD_CG_SUPPORT_HDP_LS | 757 AMD_CG_SUPPORT_SDMA_MGCG | 758 AMD_CG_SUPPORT_SDMA_LS | 759 AMD_CG_SUPPORT_MC_MGCG | 760 AMD_CG_SUPPORT_MC_LS | 761 AMD_CG_SUPPORT_ATHUB_MGCG | 762 AMD_CG_SUPPORT_ATHUB_LS | 763 AMD_CG_SUPPORT_VCN_MGCG | 764 AMD_CG_SUPPORT_JPEG_MGCG; 765 adev->pg_flags = AMD_PG_SUPPORT_VCN | 766 AMD_PG_SUPPORT_VCN_DPG | 767 AMD_PG_SUPPORT_JPEG | 768 AMD_PG_SUPPORT_ATHUB; 769 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 770 * as a consequence, the rev_id and external_rev_id are wrong. 771 * workaround it by hardcoding rev_id to 0 (default value). 772 */ 773 if (amdgpu_sriov_vf(adev)) 774 adev->rev_id = 0; 775 adev->external_rev_id = adev->rev_id + 0xa; 776 break; 777 case IP_VERSION(10, 3, 0): 778 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 779 AMD_CG_SUPPORT_GFX_CGCG | 780 AMD_CG_SUPPORT_GFX_CGLS | 781 AMD_CG_SUPPORT_GFX_3D_CGCG | 782 AMD_CG_SUPPORT_MC_MGCG | 783 AMD_CG_SUPPORT_VCN_MGCG | 784 AMD_CG_SUPPORT_JPEG_MGCG | 785 AMD_CG_SUPPORT_HDP_MGCG | 786 AMD_CG_SUPPORT_HDP_LS | 787 AMD_CG_SUPPORT_IH_CG | 788 AMD_CG_SUPPORT_MC_LS; 789 adev->pg_flags = AMD_PG_SUPPORT_VCN | 790 AMD_PG_SUPPORT_VCN_DPG | 791 AMD_PG_SUPPORT_JPEG | 792 AMD_PG_SUPPORT_ATHUB | 793 AMD_PG_SUPPORT_MMHUB; 794 if (amdgpu_sriov_vf(adev)) { 795 /* hypervisor control CG and PG enablement */ 796 adev->cg_flags = 0; 797 adev->pg_flags = 0; 798 } 799 adev->external_rev_id = adev->rev_id + 0x28; 800 break; 801 case IP_VERSION(10, 3, 2): 802 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 803 AMD_CG_SUPPORT_GFX_CGCG | 804 AMD_CG_SUPPORT_GFX_CGLS | 805 AMD_CG_SUPPORT_GFX_3D_CGCG | 806 AMD_CG_SUPPORT_VCN_MGCG | 807 AMD_CG_SUPPORT_JPEG_MGCG | 808 AMD_CG_SUPPORT_MC_MGCG | 809 AMD_CG_SUPPORT_MC_LS | 810 AMD_CG_SUPPORT_HDP_MGCG | 811 AMD_CG_SUPPORT_HDP_LS | 812 AMD_CG_SUPPORT_IH_CG; 813 adev->pg_flags = AMD_PG_SUPPORT_VCN | 814 AMD_PG_SUPPORT_VCN_DPG | 815 AMD_PG_SUPPORT_JPEG | 816 AMD_PG_SUPPORT_ATHUB | 817 AMD_PG_SUPPORT_MMHUB; 818 adev->external_rev_id = adev->rev_id + 0x32; 819 break; 820 case IP_VERSION(10, 3, 1): 821 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 822 AMD_CG_SUPPORT_GFX_MGLS | 823 AMD_CG_SUPPORT_GFX_CP_LS | 824 AMD_CG_SUPPORT_GFX_RLC_LS | 825 AMD_CG_SUPPORT_GFX_CGCG | 826 AMD_CG_SUPPORT_GFX_CGLS | 827 AMD_CG_SUPPORT_GFX_3D_CGCG | 828 AMD_CG_SUPPORT_GFX_3D_CGLS | 829 AMD_CG_SUPPORT_MC_MGCG | 830 AMD_CG_SUPPORT_MC_LS | 831 AMD_CG_SUPPORT_GFX_FGCG | 832 AMD_CG_SUPPORT_VCN_MGCG | 833 AMD_CG_SUPPORT_SDMA_MGCG | 834 AMD_CG_SUPPORT_SDMA_LS | 835 AMD_CG_SUPPORT_JPEG_MGCG; 836 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 837 AMD_PG_SUPPORT_VCN | 838 AMD_PG_SUPPORT_VCN_DPG | 839 AMD_PG_SUPPORT_JPEG; 840 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 841 adev->external_rev_id = adev->rev_id + 0x01; 842 break; 843 case IP_VERSION(10, 3, 4): 844 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 845 AMD_CG_SUPPORT_GFX_CGCG | 846 AMD_CG_SUPPORT_GFX_CGLS | 847 AMD_CG_SUPPORT_GFX_3D_CGCG | 848 AMD_CG_SUPPORT_VCN_MGCG | 849 AMD_CG_SUPPORT_JPEG_MGCG | 850 AMD_CG_SUPPORT_MC_MGCG | 851 AMD_CG_SUPPORT_MC_LS | 852 AMD_CG_SUPPORT_HDP_MGCG | 853 AMD_CG_SUPPORT_HDP_LS | 854 AMD_CG_SUPPORT_IH_CG; 855 adev->pg_flags = AMD_PG_SUPPORT_VCN | 856 AMD_PG_SUPPORT_VCN_DPG | 857 AMD_PG_SUPPORT_JPEG | 858 AMD_PG_SUPPORT_ATHUB | 859 AMD_PG_SUPPORT_MMHUB; 860 adev->external_rev_id = adev->rev_id + 0x3c; 861 break; 862 case IP_VERSION(10, 3, 5): 863 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 864 AMD_CG_SUPPORT_GFX_CGCG | 865 AMD_CG_SUPPORT_GFX_CGLS | 866 AMD_CG_SUPPORT_GFX_3D_CGCG | 867 AMD_CG_SUPPORT_MC_MGCG | 868 AMD_CG_SUPPORT_MC_LS | 869 AMD_CG_SUPPORT_HDP_MGCG | 870 AMD_CG_SUPPORT_HDP_LS | 871 AMD_CG_SUPPORT_IH_CG | 872 AMD_CG_SUPPORT_VCN_MGCG; 873 adev->pg_flags = AMD_PG_SUPPORT_VCN | 874 AMD_PG_SUPPORT_VCN_DPG | 875 AMD_PG_SUPPORT_ATHUB | 876 AMD_PG_SUPPORT_MMHUB; 877 adev->external_rev_id = adev->rev_id + 0x46; 878 break; 879 case IP_VERSION(10, 3, 3): 880 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 881 AMD_CG_SUPPORT_GFX_MGLS | 882 AMD_CG_SUPPORT_GFX_CGCG | 883 AMD_CG_SUPPORT_GFX_CGLS | 884 AMD_CG_SUPPORT_GFX_3D_CGCG | 885 AMD_CG_SUPPORT_GFX_3D_CGLS | 886 AMD_CG_SUPPORT_GFX_RLC_LS | 887 AMD_CG_SUPPORT_GFX_CP_LS | 888 AMD_CG_SUPPORT_GFX_FGCG | 889 AMD_CG_SUPPORT_MC_MGCG | 890 AMD_CG_SUPPORT_MC_LS | 891 AMD_CG_SUPPORT_SDMA_LS | 892 AMD_CG_SUPPORT_HDP_MGCG | 893 AMD_CG_SUPPORT_HDP_LS | 894 AMD_CG_SUPPORT_ATHUB_MGCG | 895 AMD_CG_SUPPORT_ATHUB_LS | 896 AMD_CG_SUPPORT_IH_CG | 897 AMD_CG_SUPPORT_VCN_MGCG | 898 AMD_CG_SUPPORT_JPEG_MGCG; 899 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 900 AMD_PG_SUPPORT_VCN | 901 AMD_PG_SUPPORT_VCN_DPG | 902 AMD_PG_SUPPORT_JPEG; 903 if (adev->pdev->device == 0x1681) 904 adev->external_rev_id = 0x20; 905 else 906 adev->external_rev_id = adev->rev_id + 0x01; 907 break; 908 case IP_VERSION(10, 1, 3): 909 case IP_VERSION(10, 1, 4): 910 adev->cg_flags = 0; 911 adev->pg_flags = 0; 912 adev->external_rev_id = adev->rev_id + 0x82; 913 break; 914 case IP_VERSION(10, 3, 6): 915 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 916 AMD_CG_SUPPORT_GFX_MGLS | 917 AMD_CG_SUPPORT_GFX_CGCG | 918 AMD_CG_SUPPORT_GFX_CGLS | 919 AMD_CG_SUPPORT_GFX_3D_CGCG | 920 AMD_CG_SUPPORT_GFX_3D_CGLS | 921 AMD_CG_SUPPORT_GFX_RLC_LS | 922 AMD_CG_SUPPORT_GFX_CP_LS | 923 AMD_CG_SUPPORT_GFX_FGCG | 924 AMD_CG_SUPPORT_MC_MGCG | 925 AMD_CG_SUPPORT_MC_LS | 926 AMD_CG_SUPPORT_SDMA_LS | 927 AMD_CG_SUPPORT_HDP_MGCG | 928 AMD_CG_SUPPORT_HDP_LS | 929 AMD_CG_SUPPORT_ATHUB_MGCG | 930 AMD_CG_SUPPORT_ATHUB_LS | 931 AMD_CG_SUPPORT_IH_CG | 932 AMD_CG_SUPPORT_VCN_MGCG | 933 AMD_CG_SUPPORT_JPEG_MGCG; 934 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 935 AMD_PG_SUPPORT_VCN | 936 AMD_PG_SUPPORT_VCN_DPG | 937 AMD_PG_SUPPORT_JPEG; 938 adev->external_rev_id = adev->rev_id + 0x01; 939 break; 940 case IP_VERSION(10, 3, 7): 941 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 942 AMD_CG_SUPPORT_GFX_MGLS | 943 AMD_CG_SUPPORT_GFX_CGCG | 944 AMD_CG_SUPPORT_GFX_CGLS | 945 AMD_CG_SUPPORT_GFX_3D_CGCG | 946 AMD_CG_SUPPORT_GFX_3D_CGLS | 947 AMD_CG_SUPPORT_GFX_RLC_LS | 948 AMD_CG_SUPPORT_GFX_CP_LS | 949 AMD_CG_SUPPORT_GFX_FGCG | 950 AMD_CG_SUPPORT_MC_MGCG | 951 AMD_CG_SUPPORT_MC_LS | 952 AMD_CG_SUPPORT_SDMA_LS | 953 AMD_CG_SUPPORT_HDP_MGCG | 954 AMD_CG_SUPPORT_HDP_LS | 955 AMD_CG_SUPPORT_ATHUB_MGCG | 956 AMD_CG_SUPPORT_ATHUB_LS | 957 AMD_CG_SUPPORT_IH_CG | 958 AMD_CG_SUPPORT_VCN_MGCG | 959 AMD_CG_SUPPORT_JPEG_MGCG; 960 adev->pg_flags = AMD_PG_SUPPORT_VCN | 961 AMD_PG_SUPPORT_VCN_DPG | 962 AMD_PG_SUPPORT_JPEG | 963 AMD_PG_SUPPORT_GFX_PG; 964 adev->external_rev_id = adev->rev_id + 0x01; 965 break; 966 default: 967 /* FIXME: not supported yet */ 968 return -EINVAL; 969 } 970 971 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 972 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 973 AMD_PG_SUPPORT_VCN_DPG | 974 AMD_PG_SUPPORT_JPEG); 975 976 if (amdgpu_sriov_vf(adev)) { 977 amdgpu_virt_init_setting(adev); 978 xgpu_nv_mailbox_set_irq_funcs(adev); 979 } 980 981 return 0; 982 } 983 984 static int nv_common_late_init(void *handle) 985 { 986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 987 988 if (amdgpu_sriov_vf(adev)) { 989 xgpu_nv_mailbox_get_irq(adev); 990 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 991 amdgpu_virt_update_sriov_video_codec(adev, 992 sriov_sc_video_codecs_encode_array, 993 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 994 sriov_sc_video_codecs_decode_array_vcn1, 995 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1)); 996 } else { 997 amdgpu_virt_update_sriov_video_codec(adev, 998 sriov_sc_video_codecs_encode_array, 999 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 1000 sriov_sc_video_codecs_decode_array_vcn0, 1001 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0)); 1002 } 1003 } 1004 1005 /* Enable selfring doorbell aperture late because doorbell BAR 1006 * aperture will change if resize BAR successfully in gmc sw_init. 1007 */ 1008 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 1009 1010 return 0; 1011 } 1012 1013 static int nv_common_sw_init(void *handle) 1014 { 1015 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1016 1017 if (amdgpu_sriov_vf(adev)) 1018 xgpu_nv_mailbox_add_irq_id(adev); 1019 1020 return 0; 1021 } 1022 1023 static int nv_common_sw_fini(void *handle) 1024 { 1025 return 0; 1026 } 1027 1028 static int nv_common_hw_init(void *handle) 1029 { 1030 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1031 1032 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 1033 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 1034 1035 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1036 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1037 1038 /* enable aspm */ 1039 nv_program_aspm(adev); 1040 /* setup nbio registers */ 1041 adev->nbio.funcs->init_registers(adev); 1042 /* remap HDP registers to a hole in mmio space, 1043 * for the purpose of expose those registers 1044 * to process space 1045 */ 1046 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1047 adev->nbio.funcs->remap_hdp_registers(adev); 1048 /* enable the doorbell aperture */ 1049 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1050 1051 return 0; 1052 } 1053 1054 static int nv_common_hw_fini(void *handle) 1055 { 1056 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1057 1058 /* Disable the doorbell aperture and selfring doorbell aperture 1059 * separately in hw_fini because nv_enable_doorbell_aperture 1060 * has been removed and there is no need to delay disabling 1061 * selfring doorbell. 1062 */ 1063 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1064 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1065 1066 return 0; 1067 } 1068 1069 static int nv_common_suspend(void *handle) 1070 { 1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1072 1073 return nv_common_hw_fini(adev); 1074 } 1075 1076 static int nv_common_resume(void *handle) 1077 { 1078 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1079 1080 return nv_common_hw_init(adev); 1081 } 1082 1083 static bool nv_common_is_idle(void *handle) 1084 { 1085 return true; 1086 } 1087 1088 static int nv_common_wait_for_idle(void *handle) 1089 { 1090 return 0; 1091 } 1092 1093 static int nv_common_soft_reset(void *handle) 1094 { 1095 return 0; 1096 } 1097 1098 static int nv_common_set_clockgating_state(void *handle, 1099 enum amd_clockgating_state state) 1100 { 1101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1102 1103 if (amdgpu_sriov_vf(adev)) 1104 return 0; 1105 1106 switch (adev->ip_versions[NBIO_HWIP][0]) { 1107 case IP_VERSION(2, 3, 0): 1108 case IP_VERSION(2, 3, 1): 1109 case IP_VERSION(2, 3, 2): 1110 case IP_VERSION(3, 3, 0): 1111 case IP_VERSION(3, 3, 1): 1112 case IP_VERSION(3, 3, 2): 1113 case IP_VERSION(3, 3, 3): 1114 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1115 state == AMD_CG_STATE_GATE); 1116 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1117 state == AMD_CG_STATE_GATE); 1118 adev->hdp.funcs->update_clock_gating(adev, 1119 state == AMD_CG_STATE_GATE); 1120 adev->smuio.funcs->update_rom_clock_gating(adev, 1121 state == AMD_CG_STATE_GATE); 1122 break; 1123 default: 1124 break; 1125 } 1126 return 0; 1127 } 1128 1129 static int nv_common_set_powergating_state(void *handle, 1130 enum amd_powergating_state state) 1131 { 1132 /* TODO */ 1133 return 0; 1134 } 1135 1136 static void nv_common_get_clockgating_state(void *handle, u64 *flags) 1137 { 1138 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1139 1140 if (amdgpu_sriov_vf(adev)) 1141 *flags = 0; 1142 1143 adev->nbio.funcs->get_clockgating_state(adev, flags); 1144 1145 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1146 1147 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1148 1149 return; 1150 } 1151 1152 static const struct amd_ip_funcs nv_common_ip_funcs = { 1153 .name = "nv_common", 1154 .early_init = nv_common_early_init, 1155 .late_init = nv_common_late_init, 1156 .sw_init = nv_common_sw_init, 1157 .sw_fini = nv_common_sw_fini, 1158 .hw_init = nv_common_hw_init, 1159 .hw_fini = nv_common_hw_fini, 1160 .suspend = nv_common_suspend, 1161 .resume = nv_common_resume, 1162 .is_idle = nv_common_is_idle, 1163 .wait_for_idle = nv_common_wait_for_idle, 1164 .soft_reset = nv_common_soft_reset, 1165 .set_clockgating_state = nv_common_set_clockgating_state, 1166 .set_powergating_state = nv_common_set_powergating_state, 1167 .get_clockgating_state = nv_common_get_clockgating_state, 1168 }; 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