1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 74 }; 75 76 static const struct amdgpu_video_codecs nv_video_codecs_encode = 77 { 78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 79 .codec_array = nv_video_codecs_encode_array, 80 }; 81 82 /* Navi1x */ 83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 92 }; 93 94 static const struct amdgpu_video_codecs nv_video_codecs_decode = 95 { 96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 97 .codec_array = nv_video_codecs_decode_array, 98 }; 99 100 /* Sienna Cichlid */ 101 static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = { 102 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)}, 103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)}, 104 }; 105 106 static const struct amdgpu_video_codecs sc_video_codecs_encode = { 107 .codec_count = ARRAY_SIZE(sc_video_codecs_encode_array), 108 .codec_array = sc_video_codecs_encode_array, 109 }; 110 111 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = 112 { 113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 114 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 115 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 116 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 117 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 118 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 119 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 121 }; 122 123 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = 124 { 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 132 }; 133 134 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = 135 { 136 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0), 137 .codec_array = sc_video_codecs_decode_array_vcn0, 138 }; 139 140 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = 141 { 142 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1), 143 .codec_array = sc_video_codecs_decode_array_vcn1, 144 }; 145 146 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 147 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 148 { 149 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)}, 150 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)}, 151 }; 152 153 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = 154 { 155 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 162 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 163 }; 164 165 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = 166 { 167 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 168 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 169 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 170 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 171 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 172 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 173 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 174 }; 175 176 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 177 { 178 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 179 .codec_array = sriov_sc_video_codecs_encode_array, 180 }; 181 182 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = 183 { 184 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0), 185 .codec_array = sriov_sc_video_codecs_decode_array_vcn0, 186 }; 187 188 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = 189 { 190 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1), 191 .codec_array = sriov_sc_video_codecs_decode_array_vcn1, 192 }; 193 194 /* Beige Goby*/ 195 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 196 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 197 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 198 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 199 }; 200 201 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 202 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 203 .codec_array = bg_video_codecs_decode_array, 204 }; 205 206 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 207 .codec_count = 0, 208 .codec_array = NULL, 209 }; 210 211 /* Yellow Carp*/ 212 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 213 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 214 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 215 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 216 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 217 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 218 }; 219 220 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 221 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 222 .codec_array = yc_video_codecs_decode_array, 223 }; 224 225 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 226 const struct amdgpu_video_codecs **codecs) 227 { 228 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 229 return -EINVAL; 230 231 switch (adev->ip_versions[UVD_HWIP][0]) { 232 case IP_VERSION(3, 0, 0): 233 case IP_VERSION(3, 0, 64): 234 case IP_VERSION(3, 0, 192): 235 if (amdgpu_sriov_vf(adev)) { 236 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 237 if (encode) 238 *codecs = &sriov_sc_video_codecs_encode; 239 else 240 *codecs = &sriov_sc_video_codecs_decode_vcn1; 241 } else { 242 if (encode) 243 *codecs = &sriov_sc_video_codecs_encode; 244 else 245 *codecs = &sriov_sc_video_codecs_decode_vcn0; 246 } 247 } else { 248 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 249 if (encode) 250 *codecs = &sc_video_codecs_encode; 251 else 252 *codecs = &sc_video_codecs_decode_vcn1; 253 } else { 254 if (encode) 255 *codecs = &sc_video_codecs_encode; 256 else 257 *codecs = &sc_video_codecs_decode_vcn0; 258 } 259 } 260 return 0; 261 case IP_VERSION(3, 0, 16): 262 case IP_VERSION(3, 0, 2): 263 if (encode) 264 *codecs = &sc_video_codecs_encode; 265 else 266 *codecs = &sc_video_codecs_decode_vcn0; 267 return 0; 268 case IP_VERSION(3, 1, 1): 269 case IP_VERSION(3, 1, 2): 270 if (encode) 271 *codecs = &sc_video_codecs_encode; 272 else 273 *codecs = &yc_video_codecs_decode; 274 return 0; 275 case IP_VERSION(3, 0, 33): 276 if (encode) 277 *codecs = &bg_video_codecs_encode; 278 else 279 *codecs = &bg_video_codecs_decode; 280 return 0; 281 case IP_VERSION(2, 0, 0): 282 case IP_VERSION(2, 0, 2): 283 if (encode) 284 *codecs = &nv_video_codecs_encode; 285 else 286 *codecs = &nv_video_codecs_decode; 287 return 0; 288 default: 289 return -EINVAL; 290 } 291 } 292 293 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 294 { 295 unsigned long flags, address, data; 296 u32 r; 297 298 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 299 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 300 301 spin_lock_irqsave(&adev->didt_idx_lock, flags); 302 WREG32(address, (reg)); 303 r = RREG32(data); 304 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 305 return r; 306 } 307 308 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 309 { 310 unsigned long flags, address, data; 311 312 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 313 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 314 315 spin_lock_irqsave(&adev->didt_idx_lock, flags); 316 WREG32(address, (reg)); 317 WREG32(data, (v)); 318 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 319 } 320 321 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 322 { 323 return adev->nbio.funcs->get_memsize(adev); 324 } 325 326 static u32 nv_get_xclk(struct amdgpu_device *adev) 327 { 328 return adev->clock.spll.reference_freq; 329 } 330 331 332 void nv_grbm_select(struct amdgpu_device *adev, 333 u32 me, u32 pipe, u32 queue, u32 vmid) 334 { 335 u32 grbm_gfx_cntl = 0; 336 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 337 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 338 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 339 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 340 341 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 342 } 343 344 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 345 { 346 /* todo */ 347 return false; 348 } 349 350 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 351 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 352 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 353 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 354 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 355 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 356 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 357 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 358 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 359 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 360 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 361 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 362 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 363 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 364 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 365 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 366 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 367 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 368 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 369 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 370 }; 371 372 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 373 u32 sh_num, u32 reg_offset) 374 { 375 uint32_t val; 376 377 mutex_lock(&adev->grbm_idx_mutex); 378 if (se_num != 0xffffffff || sh_num != 0xffffffff) 379 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 380 381 val = RREG32(reg_offset); 382 383 if (se_num != 0xffffffff || sh_num != 0xffffffff) 384 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 385 mutex_unlock(&adev->grbm_idx_mutex); 386 return val; 387 } 388 389 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 390 bool indexed, u32 se_num, 391 u32 sh_num, u32 reg_offset) 392 { 393 if (indexed) { 394 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 395 } else { 396 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 397 return adev->gfx.config.gb_addr_config; 398 return RREG32(reg_offset); 399 } 400 } 401 402 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 403 u32 sh_num, u32 reg_offset, u32 *value) 404 { 405 uint32_t i; 406 struct soc15_allowed_register_entry *en; 407 408 *value = 0; 409 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 410 en = &nv_allowed_read_registers[i]; 411 if (!adev->reg_offset[en->hwip][en->inst]) 412 continue; 413 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 414 + en->reg_offset)) 415 continue; 416 417 *value = nv_get_register_value(adev, 418 nv_allowed_read_registers[i].grbm_indexed, 419 se_num, sh_num, reg_offset); 420 return 0; 421 } 422 return -EINVAL; 423 } 424 425 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 426 { 427 u32 i; 428 int ret = 0; 429 430 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 431 432 /* disable BM */ 433 pci_clear_master(adev->pdev); 434 435 amdgpu_device_cache_pci_state(adev->pdev); 436 437 ret = amdgpu_dpm_mode2_reset(adev); 438 if (ret) 439 dev_err(adev->dev, "GPU mode2 reset failed\n"); 440 441 amdgpu_device_load_pci_state(adev->pdev); 442 443 /* wait for asic to come out of reset */ 444 for (i = 0; i < adev->usec_timeout; i++) { 445 u32 memsize = adev->nbio.funcs->get_memsize(adev); 446 447 if (memsize != 0xffffffff) 448 break; 449 udelay(1); 450 } 451 452 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 453 454 return ret; 455 } 456 457 static enum amd_reset_method 458 nv_asic_reset_method(struct amdgpu_device *adev) 459 { 460 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 461 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 462 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 463 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 464 return amdgpu_reset_method; 465 466 if (amdgpu_reset_method != -1) 467 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 468 amdgpu_reset_method); 469 470 switch (adev->ip_versions[MP1_HWIP][0]) { 471 case IP_VERSION(11, 5, 0): 472 case IP_VERSION(13, 0, 1): 473 case IP_VERSION(13, 0, 3): 474 case IP_VERSION(13, 0, 5): 475 case IP_VERSION(13, 0, 8): 476 return AMD_RESET_METHOD_MODE2; 477 case IP_VERSION(11, 0, 7): 478 case IP_VERSION(11, 0, 11): 479 case IP_VERSION(11, 0, 12): 480 case IP_VERSION(11, 0, 13): 481 return AMD_RESET_METHOD_MODE1; 482 default: 483 if (amdgpu_dpm_is_baco_supported(adev)) 484 return AMD_RESET_METHOD_BACO; 485 else 486 return AMD_RESET_METHOD_MODE1; 487 } 488 } 489 490 static int nv_asic_reset(struct amdgpu_device *adev) 491 { 492 int ret = 0; 493 494 switch (nv_asic_reset_method(adev)) { 495 case AMD_RESET_METHOD_PCI: 496 dev_info(adev->dev, "PCI reset\n"); 497 ret = amdgpu_device_pci_reset(adev); 498 break; 499 case AMD_RESET_METHOD_BACO: 500 dev_info(adev->dev, "BACO reset\n"); 501 ret = amdgpu_dpm_baco_reset(adev); 502 break; 503 case AMD_RESET_METHOD_MODE2: 504 dev_info(adev->dev, "MODE2 reset\n"); 505 ret = nv_asic_mode2_reset(adev); 506 break; 507 default: 508 dev_info(adev->dev, "MODE1 reset\n"); 509 ret = amdgpu_device_mode1_reset(adev); 510 break; 511 } 512 513 return ret; 514 } 515 516 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 517 { 518 /* todo */ 519 return 0; 520 } 521 522 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 523 { 524 /* todo */ 525 return 0; 526 } 527 528 static void nv_program_aspm(struct amdgpu_device *adev) 529 { 530 if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_aspm_support_quirk()) 531 return; 532 533 if (!(adev->flags & AMD_IS_APU) && 534 (adev->nbio.funcs->program_aspm)) 535 adev->nbio.funcs->program_aspm(adev); 536 537 } 538 539 const struct amdgpu_ip_block_version nv_common_ip_block = 540 { 541 .type = AMD_IP_BLOCK_TYPE_COMMON, 542 .major = 1, 543 .minor = 0, 544 .rev = 0, 545 .funcs = &nv_common_ip_funcs, 546 }; 547 548 void nv_set_virt_ops(struct amdgpu_device *adev) 549 { 550 adev->virt.ops = &xgpu_nv_virt_ops; 551 } 552 553 static bool nv_need_full_reset(struct amdgpu_device *adev) 554 { 555 return true; 556 } 557 558 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 559 { 560 u32 sol_reg; 561 562 if (adev->flags & AMD_IS_APU) 563 return false; 564 565 /* Check sOS sign of life register to confirm sys driver and sOS 566 * are already been loaded. 567 */ 568 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 569 if (sol_reg) 570 return true; 571 572 return false; 573 } 574 575 static void nv_init_doorbell_index(struct amdgpu_device *adev) 576 { 577 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 578 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 579 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 580 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 581 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 582 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 583 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 584 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 585 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 586 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 587 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 588 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 589 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 590 adev->doorbell_index.gfx_userqueue_start = 591 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 592 adev->doorbell_index.gfx_userqueue_end = 593 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 594 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 595 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 596 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 597 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 598 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 599 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 600 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 601 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 602 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 603 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 604 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 605 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 606 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 607 608 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 609 adev->doorbell_index.sdma_doorbell_range = 20; 610 } 611 612 static void nv_pre_asic_init(struct amdgpu_device *adev) 613 { 614 } 615 616 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 617 bool enter) 618 { 619 if (enter) 620 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 621 else 622 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 623 624 if (adev->gfx.funcs->update_perfmon_mgcg) 625 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 626 627 if (!(adev->flags & AMD_IS_APU) && 628 (adev->nbio.funcs->enable_aspm) && 629 amdgpu_device_should_use_aspm(adev)) 630 adev->nbio.funcs->enable_aspm(adev, !enter); 631 632 return 0; 633 } 634 635 static const struct amdgpu_asic_funcs nv_asic_funcs = 636 { 637 .read_disabled_bios = &nv_read_disabled_bios, 638 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 639 .read_register = &nv_read_register, 640 .reset = &nv_asic_reset, 641 .reset_method = &nv_asic_reset_method, 642 .get_xclk = &nv_get_xclk, 643 .set_uvd_clocks = &nv_set_uvd_clocks, 644 .set_vce_clocks = &nv_set_vce_clocks, 645 .get_config_memsize = &nv_get_config_memsize, 646 .init_doorbell_index = &nv_init_doorbell_index, 647 .need_full_reset = &nv_need_full_reset, 648 .need_reset_on_init = &nv_need_reset_on_init, 649 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 650 .supports_baco = &amdgpu_dpm_is_baco_supported, 651 .pre_asic_init = &nv_pre_asic_init, 652 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 653 .query_video_codecs = &nv_query_video_codecs, 654 }; 655 656 static int nv_common_early_init(void *handle) 657 { 658 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 659 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 660 661 if (!amdgpu_sriov_vf(adev)) { 662 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 663 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 664 } 665 adev->smc_rreg = NULL; 666 adev->smc_wreg = NULL; 667 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 668 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 669 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 670 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 671 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 672 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 673 674 /* TODO: will add them during VCN v2 implementation */ 675 adev->uvd_ctx_rreg = NULL; 676 adev->uvd_ctx_wreg = NULL; 677 678 adev->didt_rreg = &nv_didt_rreg; 679 adev->didt_wreg = &nv_didt_wreg; 680 681 adev->asic_funcs = &nv_asic_funcs; 682 683 adev->rev_id = amdgpu_device_get_rev_id(adev); 684 adev->external_rev_id = 0xff; 685 /* TODO: split the GC and PG flags based on the relevant IP version for which 686 * they are relevant. 687 */ 688 switch (adev->ip_versions[GC_HWIP][0]) { 689 case IP_VERSION(10, 1, 10): 690 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 691 AMD_CG_SUPPORT_GFX_CGCG | 692 AMD_CG_SUPPORT_IH_CG | 693 AMD_CG_SUPPORT_HDP_MGCG | 694 AMD_CG_SUPPORT_HDP_LS | 695 AMD_CG_SUPPORT_SDMA_MGCG | 696 AMD_CG_SUPPORT_SDMA_LS | 697 AMD_CG_SUPPORT_MC_MGCG | 698 AMD_CG_SUPPORT_MC_LS | 699 AMD_CG_SUPPORT_ATHUB_MGCG | 700 AMD_CG_SUPPORT_ATHUB_LS | 701 AMD_CG_SUPPORT_VCN_MGCG | 702 AMD_CG_SUPPORT_JPEG_MGCG | 703 AMD_CG_SUPPORT_BIF_MGCG | 704 AMD_CG_SUPPORT_BIF_LS; 705 adev->pg_flags = AMD_PG_SUPPORT_VCN | 706 AMD_PG_SUPPORT_VCN_DPG | 707 AMD_PG_SUPPORT_JPEG | 708 AMD_PG_SUPPORT_ATHUB; 709 adev->external_rev_id = adev->rev_id + 0x1; 710 break; 711 case IP_VERSION(10, 1, 1): 712 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 713 AMD_CG_SUPPORT_GFX_CGCG | 714 AMD_CG_SUPPORT_IH_CG | 715 AMD_CG_SUPPORT_HDP_MGCG | 716 AMD_CG_SUPPORT_HDP_LS | 717 AMD_CG_SUPPORT_SDMA_MGCG | 718 AMD_CG_SUPPORT_SDMA_LS | 719 AMD_CG_SUPPORT_MC_MGCG | 720 AMD_CG_SUPPORT_MC_LS | 721 AMD_CG_SUPPORT_ATHUB_MGCG | 722 AMD_CG_SUPPORT_ATHUB_LS | 723 AMD_CG_SUPPORT_VCN_MGCG | 724 AMD_CG_SUPPORT_JPEG_MGCG | 725 AMD_CG_SUPPORT_BIF_MGCG | 726 AMD_CG_SUPPORT_BIF_LS; 727 adev->pg_flags = AMD_PG_SUPPORT_VCN | 728 AMD_PG_SUPPORT_JPEG | 729 AMD_PG_SUPPORT_VCN_DPG; 730 adev->external_rev_id = adev->rev_id + 20; 731 break; 732 case IP_VERSION(10, 1, 2): 733 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 734 AMD_CG_SUPPORT_GFX_MGLS | 735 AMD_CG_SUPPORT_GFX_CGCG | 736 AMD_CG_SUPPORT_GFX_CP_LS | 737 AMD_CG_SUPPORT_GFX_RLC_LS | 738 AMD_CG_SUPPORT_IH_CG | 739 AMD_CG_SUPPORT_HDP_MGCG | 740 AMD_CG_SUPPORT_HDP_LS | 741 AMD_CG_SUPPORT_SDMA_MGCG | 742 AMD_CG_SUPPORT_SDMA_LS | 743 AMD_CG_SUPPORT_MC_MGCG | 744 AMD_CG_SUPPORT_MC_LS | 745 AMD_CG_SUPPORT_ATHUB_MGCG | 746 AMD_CG_SUPPORT_ATHUB_LS | 747 AMD_CG_SUPPORT_VCN_MGCG | 748 AMD_CG_SUPPORT_JPEG_MGCG; 749 adev->pg_flags = AMD_PG_SUPPORT_VCN | 750 AMD_PG_SUPPORT_VCN_DPG | 751 AMD_PG_SUPPORT_JPEG | 752 AMD_PG_SUPPORT_ATHUB; 753 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 754 * as a consequence, the rev_id and external_rev_id are wrong. 755 * workaround it by hardcoding rev_id to 0 (default value). 756 */ 757 if (amdgpu_sriov_vf(adev)) 758 adev->rev_id = 0; 759 adev->external_rev_id = adev->rev_id + 0xa; 760 break; 761 case IP_VERSION(10, 3, 0): 762 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 763 AMD_CG_SUPPORT_GFX_CGCG | 764 AMD_CG_SUPPORT_GFX_CGLS | 765 AMD_CG_SUPPORT_GFX_3D_CGCG | 766 AMD_CG_SUPPORT_MC_MGCG | 767 AMD_CG_SUPPORT_VCN_MGCG | 768 AMD_CG_SUPPORT_JPEG_MGCG | 769 AMD_CG_SUPPORT_HDP_MGCG | 770 AMD_CG_SUPPORT_HDP_LS | 771 AMD_CG_SUPPORT_IH_CG | 772 AMD_CG_SUPPORT_MC_LS; 773 adev->pg_flags = AMD_PG_SUPPORT_VCN | 774 AMD_PG_SUPPORT_VCN_DPG | 775 AMD_PG_SUPPORT_JPEG | 776 AMD_PG_SUPPORT_ATHUB | 777 AMD_PG_SUPPORT_MMHUB; 778 if (amdgpu_sriov_vf(adev)) { 779 /* hypervisor control CG and PG enablement */ 780 adev->cg_flags = 0; 781 adev->pg_flags = 0; 782 } 783 adev->external_rev_id = adev->rev_id + 0x28; 784 break; 785 case IP_VERSION(10, 3, 2): 786 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 787 AMD_CG_SUPPORT_GFX_CGCG | 788 AMD_CG_SUPPORT_GFX_CGLS | 789 AMD_CG_SUPPORT_GFX_3D_CGCG | 790 AMD_CG_SUPPORT_VCN_MGCG | 791 AMD_CG_SUPPORT_JPEG_MGCG | 792 AMD_CG_SUPPORT_MC_MGCG | 793 AMD_CG_SUPPORT_MC_LS | 794 AMD_CG_SUPPORT_HDP_MGCG | 795 AMD_CG_SUPPORT_HDP_LS | 796 AMD_CG_SUPPORT_IH_CG; 797 adev->pg_flags = AMD_PG_SUPPORT_VCN | 798 AMD_PG_SUPPORT_VCN_DPG | 799 AMD_PG_SUPPORT_JPEG | 800 AMD_PG_SUPPORT_ATHUB | 801 AMD_PG_SUPPORT_MMHUB; 802 adev->external_rev_id = adev->rev_id + 0x32; 803 break; 804 case IP_VERSION(10, 3, 1): 805 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 806 AMD_CG_SUPPORT_GFX_MGLS | 807 AMD_CG_SUPPORT_GFX_CP_LS | 808 AMD_CG_SUPPORT_GFX_RLC_LS | 809 AMD_CG_SUPPORT_GFX_CGCG | 810 AMD_CG_SUPPORT_GFX_CGLS | 811 AMD_CG_SUPPORT_GFX_3D_CGCG | 812 AMD_CG_SUPPORT_GFX_3D_CGLS | 813 AMD_CG_SUPPORT_MC_MGCG | 814 AMD_CG_SUPPORT_MC_LS | 815 AMD_CG_SUPPORT_GFX_FGCG | 816 AMD_CG_SUPPORT_VCN_MGCG | 817 AMD_CG_SUPPORT_SDMA_MGCG | 818 AMD_CG_SUPPORT_SDMA_LS | 819 AMD_CG_SUPPORT_JPEG_MGCG; 820 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 821 AMD_PG_SUPPORT_VCN | 822 AMD_PG_SUPPORT_VCN_DPG | 823 AMD_PG_SUPPORT_JPEG; 824 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 825 adev->external_rev_id = adev->rev_id + 0x01; 826 break; 827 case IP_VERSION(10, 3, 4): 828 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 829 AMD_CG_SUPPORT_GFX_CGCG | 830 AMD_CG_SUPPORT_GFX_CGLS | 831 AMD_CG_SUPPORT_GFX_3D_CGCG | 832 AMD_CG_SUPPORT_VCN_MGCG | 833 AMD_CG_SUPPORT_JPEG_MGCG | 834 AMD_CG_SUPPORT_MC_MGCG | 835 AMD_CG_SUPPORT_MC_LS | 836 AMD_CG_SUPPORT_HDP_MGCG | 837 AMD_CG_SUPPORT_HDP_LS | 838 AMD_CG_SUPPORT_IH_CG; 839 adev->pg_flags = AMD_PG_SUPPORT_VCN | 840 AMD_PG_SUPPORT_VCN_DPG | 841 AMD_PG_SUPPORT_JPEG | 842 AMD_PG_SUPPORT_ATHUB | 843 AMD_PG_SUPPORT_MMHUB; 844 adev->external_rev_id = adev->rev_id + 0x3c; 845 break; 846 case IP_VERSION(10, 3, 5): 847 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 848 AMD_CG_SUPPORT_GFX_CGCG | 849 AMD_CG_SUPPORT_GFX_CGLS | 850 AMD_CG_SUPPORT_GFX_3D_CGCG | 851 AMD_CG_SUPPORT_MC_MGCG | 852 AMD_CG_SUPPORT_MC_LS | 853 AMD_CG_SUPPORT_HDP_MGCG | 854 AMD_CG_SUPPORT_HDP_LS | 855 AMD_CG_SUPPORT_IH_CG | 856 AMD_CG_SUPPORT_VCN_MGCG; 857 adev->pg_flags = AMD_PG_SUPPORT_VCN | 858 AMD_PG_SUPPORT_VCN_DPG | 859 AMD_PG_SUPPORT_ATHUB | 860 AMD_PG_SUPPORT_MMHUB; 861 adev->external_rev_id = adev->rev_id + 0x46; 862 break; 863 case IP_VERSION(10, 3, 3): 864 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 865 AMD_CG_SUPPORT_GFX_MGLS | 866 AMD_CG_SUPPORT_GFX_CGCG | 867 AMD_CG_SUPPORT_GFX_CGLS | 868 AMD_CG_SUPPORT_GFX_3D_CGCG | 869 AMD_CG_SUPPORT_GFX_3D_CGLS | 870 AMD_CG_SUPPORT_GFX_RLC_LS | 871 AMD_CG_SUPPORT_GFX_CP_LS | 872 AMD_CG_SUPPORT_GFX_FGCG | 873 AMD_CG_SUPPORT_MC_MGCG | 874 AMD_CG_SUPPORT_MC_LS | 875 AMD_CG_SUPPORT_SDMA_LS | 876 AMD_CG_SUPPORT_HDP_MGCG | 877 AMD_CG_SUPPORT_HDP_LS | 878 AMD_CG_SUPPORT_ATHUB_MGCG | 879 AMD_CG_SUPPORT_ATHUB_LS | 880 AMD_CG_SUPPORT_IH_CG | 881 AMD_CG_SUPPORT_VCN_MGCG | 882 AMD_CG_SUPPORT_JPEG_MGCG | 883 AMD_CG_SUPPORT_SDMA_MGCG; 884 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 885 AMD_PG_SUPPORT_VCN | 886 AMD_PG_SUPPORT_VCN_DPG | 887 AMD_PG_SUPPORT_JPEG; 888 if (adev->pdev->device == 0x1681) 889 adev->external_rev_id = 0x20; 890 else 891 adev->external_rev_id = adev->rev_id + 0x01; 892 break; 893 case IP_VERSION(10, 1, 3): 894 case IP_VERSION(10, 1, 4): 895 adev->cg_flags = 0; 896 adev->pg_flags = 0; 897 adev->external_rev_id = adev->rev_id + 0x82; 898 break; 899 case IP_VERSION(10, 3, 6): 900 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 901 AMD_CG_SUPPORT_GFX_MGLS | 902 AMD_CG_SUPPORT_GFX_CGCG | 903 AMD_CG_SUPPORT_GFX_CGLS | 904 AMD_CG_SUPPORT_GFX_3D_CGCG | 905 AMD_CG_SUPPORT_GFX_3D_CGLS | 906 AMD_CG_SUPPORT_GFX_RLC_LS | 907 AMD_CG_SUPPORT_GFX_CP_LS | 908 AMD_CG_SUPPORT_GFX_FGCG | 909 AMD_CG_SUPPORT_MC_MGCG | 910 AMD_CG_SUPPORT_MC_LS | 911 AMD_CG_SUPPORT_SDMA_LS | 912 AMD_CG_SUPPORT_HDP_MGCG | 913 AMD_CG_SUPPORT_HDP_LS | 914 AMD_CG_SUPPORT_ATHUB_MGCG | 915 AMD_CG_SUPPORT_ATHUB_LS | 916 AMD_CG_SUPPORT_IH_CG | 917 AMD_CG_SUPPORT_VCN_MGCG | 918 AMD_CG_SUPPORT_JPEG_MGCG; 919 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 920 AMD_PG_SUPPORT_VCN | 921 AMD_PG_SUPPORT_VCN_DPG | 922 AMD_PG_SUPPORT_JPEG; 923 adev->external_rev_id = adev->rev_id + 0x01; 924 break; 925 case IP_VERSION(10, 3, 7): 926 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 927 AMD_CG_SUPPORT_GFX_MGLS | 928 AMD_CG_SUPPORT_GFX_CGCG | 929 AMD_CG_SUPPORT_GFX_CGLS | 930 AMD_CG_SUPPORT_GFX_3D_CGCG | 931 AMD_CG_SUPPORT_GFX_3D_CGLS | 932 AMD_CG_SUPPORT_GFX_RLC_LS | 933 AMD_CG_SUPPORT_GFX_CP_LS | 934 AMD_CG_SUPPORT_GFX_FGCG | 935 AMD_CG_SUPPORT_MC_MGCG | 936 AMD_CG_SUPPORT_MC_LS | 937 AMD_CG_SUPPORT_SDMA_LS | 938 AMD_CG_SUPPORT_HDP_MGCG | 939 AMD_CG_SUPPORT_HDP_LS | 940 AMD_CG_SUPPORT_ATHUB_MGCG | 941 AMD_CG_SUPPORT_ATHUB_LS | 942 AMD_CG_SUPPORT_IH_CG | 943 AMD_CG_SUPPORT_VCN_MGCG | 944 AMD_CG_SUPPORT_JPEG_MGCG | 945 AMD_CG_SUPPORT_SDMA_MGCG; 946 adev->pg_flags = AMD_PG_SUPPORT_VCN | 947 AMD_PG_SUPPORT_VCN_DPG | 948 AMD_PG_SUPPORT_JPEG | 949 AMD_PG_SUPPORT_GFX_PG; 950 adev->external_rev_id = adev->rev_id + 0x01; 951 break; 952 default: 953 /* FIXME: not supported yet */ 954 return -EINVAL; 955 } 956 957 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 958 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 959 AMD_PG_SUPPORT_VCN_DPG | 960 AMD_PG_SUPPORT_JPEG); 961 962 if (amdgpu_sriov_vf(adev)) { 963 amdgpu_virt_init_setting(adev); 964 xgpu_nv_mailbox_set_irq_funcs(adev); 965 } 966 967 return 0; 968 } 969 970 static int nv_common_late_init(void *handle) 971 { 972 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 973 974 if (amdgpu_sriov_vf(adev)) { 975 xgpu_nv_mailbox_get_irq(adev); 976 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 977 amdgpu_virt_update_sriov_video_codec(adev, 978 sriov_sc_video_codecs_encode_array, 979 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 980 sriov_sc_video_codecs_decode_array_vcn1, 981 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1)); 982 } else { 983 amdgpu_virt_update_sriov_video_codec(adev, 984 sriov_sc_video_codecs_encode_array, 985 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 986 sriov_sc_video_codecs_decode_array_vcn0, 987 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0)); 988 } 989 } 990 991 /* Enable selfring doorbell aperture late because doorbell BAR 992 * aperture will change if resize BAR successfully in gmc sw_init. 993 */ 994 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 995 996 return 0; 997 } 998 999 static int nv_common_sw_init(void *handle) 1000 { 1001 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1002 1003 if (amdgpu_sriov_vf(adev)) 1004 xgpu_nv_mailbox_add_irq_id(adev); 1005 1006 return 0; 1007 } 1008 1009 static int nv_common_sw_fini(void *handle) 1010 { 1011 return 0; 1012 } 1013 1014 static int nv_common_hw_init(void *handle) 1015 { 1016 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1017 1018 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 1019 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 1020 1021 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1022 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1023 1024 /* enable aspm */ 1025 nv_program_aspm(adev); 1026 /* setup nbio registers */ 1027 adev->nbio.funcs->init_registers(adev); 1028 /* remap HDP registers to a hole in mmio space, 1029 * for the purpose of expose those registers 1030 * to process space 1031 */ 1032 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1033 adev->nbio.funcs->remap_hdp_registers(adev); 1034 /* enable the doorbell aperture */ 1035 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1036 1037 return 0; 1038 } 1039 1040 static int nv_common_hw_fini(void *handle) 1041 { 1042 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1043 1044 /* Disable the doorbell aperture and selfring doorbell aperture 1045 * separately in hw_fini because nv_enable_doorbell_aperture 1046 * has been removed and there is no need to delay disabling 1047 * selfring doorbell. 1048 */ 1049 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1050 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1051 1052 return 0; 1053 } 1054 1055 static int nv_common_suspend(void *handle) 1056 { 1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1058 1059 return nv_common_hw_fini(adev); 1060 } 1061 1062 static int nv_common_resume(void *handle) 1063 { 1064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1065 1066 return nv_common_hw_init(adev); 1067 } 1068 1069 static bool nv_common_is_idle(void *handle) 1070 { 1071 return true; 1072 } 1073 1074 static int nv_common_wait_for_idle(void *handle) 1075 { 1076 return 0; 1077 } 1078 1079 static int nv_common_soft_reset(void *handle) 1080 { 1081 return 0; 1082 } 1083 1084 static int nv_common_set_clockgating_state(void *handle, 1085 enum amd_clockgating_state state) 1086 { 1087 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1088 1089 if (amdgpu_sriov_vf(adev)) 1090 return 0; 1091 1092 switch (adev->ip_versions[NBIO_HWIP][0]) { 1093 case IP_VERSION(2, 3, 0): 1094 case IP_VERSION(2, 3, 1): 1095 case IP_VERSION(2, 3, 2): 1096 case IP_VERSION(3, 3, 0): 1097 case IP_VERSION(3, 3, 1): 1098 case IP_VERSION(3, 3, 2): 1099 case IP_VERSION(3, 3, 3): 1100 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1101 state == AMD_CG_STATE_GATE); 1102 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1103 state == AMD_CG_STATE_GATE); 1104 adev->hdp.funcs->update_clock_gating(adev, 1105 state == AMD_CG_STATE_GATE); 1106 adev->smuio.funcs->update_rom_clock_gating(adev, 1107 state == AMD_CG_STATE_GATE); 1108 break; 1109 default: 1110 break; 1111 } 1112 return 0; 1113 } 1114 1115 static int nv_common_set_powergating_state(void *handle, 1116 enum amd_powergating_state state) 1117 { 1118 /* TODO */ 1119 return 0; 1120 } 1121 1122 static void nv_common_get_clockgating_state(void *handle, u64 *flags) 1123 { 1124 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1125 1126 if (amdgpu_sriov_vf(adev)) 1127 *flags = 0; 1128 1129 adev->nbio.funcs->get_clockgating_state(adev, flags); 1130 1131 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1132 1133 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1134 1135 return; 1136 } 1137 1138 static const struct amd_ip_funcs nv_common_ip_funcs = { 1139 .name = "nv_common", 1140 .early_init = nv_common_early_init, 1141 .late_init = nv_common_late_init, 1142 .sw_init = nv_common_sw_init, 1143 .sw_fini = nv_common_sw_fini, 1144 .hw_init = nv_common_hw_init, 1145 .hw_fini = nv_common_hw_fini, 1146 .suspend = nv_common_suspend, 1147 .resume = nv_common_resume, 1148 .is_idle = nv_common_is_idle, 1149 .wait_for_idle = nv_common_wait_for_idle, 1150 .soft_reset = nv_common_soft_reset, 1151 .set_clockgating_state = nv_common_set_clockgating_state, 1152 .set_powergating_state = nv_common_set_powergating_state, 1153 .get_clockgating_state = nv_common_get_clockgating_state, 1154 }; 1155