1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "hdp/hdp_5_0_0_sh_mask.h" 43 #include "smuio/smuio_11_0_0_offset.h" 44 #include "mp/mp_11_0_offset.h" 45 46 #include "soc15.h" 47 #include "soc15_common.h" 48 #include "gmc_v10_0.h" 49 #include "gfxhub_v2_0.h" 50 #include "mmhub_v2_0.h" 51 #include "nbio_v2_3.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "dce_virtual.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 65 static const struct amd_ip_funcs nv_common_ip_funcs; 66 67 /* 68 * Indirect registers accessor 69 */ 70 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 71 { 72 unsigned long flags, address, data; 73 u32 r; 74 address = adev->nbio.funcs->get_pcie_index_offset(adev); 75 data = adev->nbio.funcs->get_pcie_data_offset(adev); 76 77 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 78 WREG32(address, reg); 79 (void)RREG32(address); 80 r = RREG32(data); 81 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 82 return r; 83 } 84 85 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 86 { 87 unsigned long flags, address, data; 88 89 address = adev->nbio.funcs->get_pcie_index_offset(adev); 90 data = adev->nbio.funcs->get_pcie_data_offset(adev); 91 92 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 93 WREG32(address, reg); 94 (void)RREG32(address); 95 WREG32(data, v); 96 (void)RREG32(data); 97 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 98 } 99 100 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 101 { 102 unsigned long flags, address, data; 103 u64 r; 104 address = adev->nbio.funcs->get_pcie_index_offset(adev); 105 data = adev->nbio.funcs->get_pcie_data_offset(adev); 106 107 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 108 /* read low 32 bit */ 109 WREG32(address, reg); 110 (void)RREG32(address); 111 r = RREG32(data); 112 113 /* read high 32 bit*/ 114 WREG32(address, reg + 4); 115 (void)RREG32(address); 116 r |= ((u64)RREG32(data) << 32); 117 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 118 return r; 119 } 120 121 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 122 { 123 unsigned long flags, address, data; 124 125 address = adev->nbio.funcs->get_pcie_index_offset(adev); 126 data = adev->nbio.funcs->get_pcie_data_offset(adev); 127 128 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 129 /* write low 32 bit */ 130 WREG32(address, reg); 131 (void)RREG32(address); 132 WREG32(data, (u32)(v & 0xffffffffULL)); 133 (void)RREG32(data); 134 135 /* write high 32 bit */ 136 WREG32(address, reg + 4); 137 (void)RREG32(address); 138 WREG32(data, (u32)(v >> 32)); 139 (void)RREG32(data); 140 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 141 } 142 143 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 144 { 145 unsigned long flags, address, data; 146 u32 r; 147 148 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 149 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 150 151 spin_lock_irqsave(&adev->didt_idx_lock, flags); 152 WREG32(address, (reg)); 153 r = RREG32(data); 154 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 155 return r; 156 } 157 158 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 159 { 160 unsigned long flags, address, data; 161 162 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 163 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 164 165 spin_lock_irqsave(&adev->didt_idx_lock, flags); 166 WREG32(address, (reg)); 167 WREG32(data, (v)); 168 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 169 } 170 171 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 172 { 173 return adev->nbio.funcs->get_memsize(adev); 174 } 175 176 static u32 nv_get_xclk(struct amdgpu_device *adev) 177 { 178 return adev->clock.spll.reference_freq; 179 } 180 181 182 void nv_grbm_select(struct amdgpu_device *adev, 183 u32 me, u32 pipe, u32 queue, u32 vmid) 184 { 185 u32 grbm_gfx_cntl = 0; 186 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 187 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 188 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 189 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 190 191 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 192 } 193 194 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 195 { 196 /* todo */ 197 } 198 199 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 200 { 201 /* todo */ 202 return false; 203 } 204 205 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 206 u8 *bios, u32 length_bytes) 207 { 208 u32 *dw_ptr; 209 u32 i, length_dw; 210 211 if (bios == NULL) 212 return false; 213 if (length_bytes == 0) 214 return false; 215 /* APU vbios image is part of sbios image */ 216 if (adev->flags & AMD_IS_APU) 217 return false; 218 219 dw_ptr = (u32 *)bios; 220 length_dw = ALIGN(length_bytes, 4) / 4; 221 222 /* set rom index to 0 */ 223 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 224 /* read out the rom data */ 225 for (i = 0; i < length_dw; i++) 226 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 227 228 return true; 229 } 230 231 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 232 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 233 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 234 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 235 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 236 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 237 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 238 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 239 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 240 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 241 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 242 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 243 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 244 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 245 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 246 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 247 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 248 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 249 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 250 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 251 }; 252 253 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 254 u32 sh_num, u32 reg_offset) 255 { 256 uint32_t val; 257 258 mutex_lock(&adev->grbm_idx_mutex); 259 if (se_num != 0xffffffff || sh_num != 0xffffffff) 260 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 261 262 val = RREG32(reg_offset); 263 264 if (se_num != 0xffffffff || sh_num != 0xffffffff) 265 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 266 mutex_unlock(&adev->grbm_idx_mutex); 267 return val; 268 } 269 270 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 271 bool indexed, u32 se_num, 272 u32 sh_num, u32 reg_offset) 273 { 274 if (indexed) { 275 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 276 } else { 277 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 278 return adev->gfx.config.gb_addr_config; 279 return RREG32(reg_offset); 280 } 281 } 282 283 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 284 u32 sh_num, u32 reg_offset, u32 *value) 285 { 286 uint32_t i; 287 struct soc15_allowed_register_entry *en; 288 289 *value = 0; 290 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 291 en = &nv_allowed_read_registers[i]; 292 if (reg_offset != 293 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 294 continue; 295 296 *value = nv_get_register_value(adev, 297 nv_allowed_read_registers[i].grbm_indexed, 298 se_num, sh_num, reg_offset); 299 return 0; 300 } 301 return -EINVAL; 302 } 303 304 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 305 { 306 u32 i; 307 int ret = 0; 308 309 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 310 311 /* disable BM */ 312 pci_clear_master(adev->pdev); 313 314 pci_save_state(adev->pdev); 315 316 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 317 dev_info(adev->dev, "GPU smu mode1 reset\n"); 318 ret = amdgpu_dpm_mode1_reset(adev); 319 } else { 320 dev_info(adev->dev, "GPU psp mode1 reset\n"); 321 ret = psp_gpu_reset(adev); 322 } 323 324 if (ret) 325 dev_err(adev->dev, "GPU mode1 reset failed\n"); 326 pci_restore_state(adev->pdev); 327 328 /* wait for asic to come out of reset */ 329 for (i = 0; i < adev->usec_timeout; i++) { 330 u32 memsize = adev->nbio.funcs->get_memsize(adev); 331 332 if (memsize != 0xffffffff) 333 break; 334 udelay(1); 335 } 336 337 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 338 339 return ret; 340 } 341 342 static bool nv_asic_supports_baco(struct amdgpu_device *adev) 343 { 344 struct smu_context *smu = &adev->smu; 345 346 if (smu_baco_is_support(smu)) 347 return true; 348 else 349 return false; 350 } 351 352 static enum amd_reset_method 353 nv_asic_reset_method(struct amdgpu_device *adev) 354 { 355 struct smu_context *smu = &adev->smu; 356 357 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 358 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 359 return amdgpu_reset_method; 360 361 if (amdgpu_reset_method != -1) 362 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 363 amdgpu_reset_method); 364 365 switch (adev->asic_type) { 366 case CHIP_SIENNA_CICHLID: 367 case CHIP_NAVY_FLOUNDER: 368 return AMD_RESET_METHOD_MODE1; 369 default: 370 if (smu_baco_is_support(smu)) 371 return AMD_RESET_METHOD_BACO; 372 else 373 return AMD_RESET_METHOD_MODE1; 374 } 375 } 376 377 static int nv_asic_reset(struct amdgpu_device *adev) 378 { 379 int ret = 0; 380 struct smu_context *smu = &adev->smu; 381 382 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 383 dev_info(adev->dev, "BACO reset\n"); 384 385 ret = smu_baco_enter(smu); 386 if (ret) 387 return ret; 388 ret = smu_baco_exit(smu); 389 if (ret) 390 return ret; 391 } else { 392 dev_info(adev->dev, "MODE1 reset\n"); 393 ret = nv_asic_mode1_reset(adev); 394 } 395 396 return ret; 397 } 398 399 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 400 { 401 /* todo */ 402 return 0; 403 } 404 405 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 406 { 407 /* todo */ 408 return 0; 409 } 410 411 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 412 { 413 if (pci_is_root_bus(adev->pdev->bus)) 414 return; 415 416 if (amdgpu_pcie_gen2 == 0) 417 return; 418 419 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 420 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 421 return; 422 423 /* todo */ 424 } 425 426 static void nv_program_aspm(struct amdgpu_device *adev) 427 { 428 429 if (amdgpu_aspm == 0) 430 return; 431 432 /* todo */ 433 } 434 435 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 436 bool enable) 437 { 438 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 439 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 440 } 441 442 static const struct amdgpu_ip_block_version nv_common_ip_block = 443 { 444 .type = AMD_IP_BLOCK_TYPE_COMMON, 445 .major = 1, 446 .minor = 0, 447 .rev = 0, 448 .funcs = &nv_common_ip_funcs, 449 }; 450 451 static int nv_reg_base_init(struct amdgpu_device *adev) 452 { 453 int r; 454 455 if (amdgpu_discovery) { 456 r = amdgpu_discovery_reg_base_init(adev); 457 if (r) { 458 DRM_WARN("failed to init reg base from ip discovery table, " 459 "fallback to legacy init method\n"); 460 goto legacy_init; 461 } 462 463 return 0; 464 } 465 466 legacy_init: 467 switch (adev->asic_type) { 468 case CHIP_NAVI10: 469 navi10_reg_base_init(adev); 470 break; 471 case CHIP_NAVI14: 472 navi14_reg_base_init(adev); 473 break; 474 case CHIP_NAVI12: 475 navi12_reg_base_init(adev); 476 break; 477 case CHIP_SIENNA_CICHLID: 478 case CHIP_NAVY_FLOUNDER: 479 sienna_cichlid_reg_base_init(adev); 480 break; 481 default: 482 return -EINVAL; 483 } 484 485 return 0; 486 } 487 488 void nv_set_virt_ops(struct amdgpu_device *adev) 489 { 490 adev->virt.ops = &xgpu_nv_virt_ops; 491 } 492 493 int nv_set_ip_blocks(struct amdgpu_device *adev) 494 { 495 int r; 496 497 adev->nbio.funcs = &nbio_v2_3_funcs; 498 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 499 500 if (adev->asic_type == CHIP_SIENNA_CICHLID) 501 adev->gmc.xgmi.supported = true; 502 503 /* Set IP register base before any HW register access */ 504 r = nv_reg_base_init(adev); 505 if (r) 506 return r; 507 508 switch (adev->asic_type) { 509 case CHIP_NAVI10: 510 case CHIP_NAVI14: 511 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 512 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 513 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 514 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 515 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 516 !amdgpu_sriov_vf(adev)) 517 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 518 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 519 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 520 #if defined(CONFIG_DRM_AMD_DC) 521 else if (amdgpu_device_has_dc_support(adev)) 522 amdgpu_device_ip_block_add(adev, &dm_ip_block); 523 #endif 524 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 525 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 526 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 527 !amdgpu_sriov_vf(adev)) 528 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 529 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 530 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 531 if (adev->enable_mes) 532 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 533 break; 534 case CHIP_NAVI12: 535 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 536 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 537 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 538 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 539 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 540 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 541 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 542 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 543 #if defined(CONFIG_DRM_AMD_DC) 544 else if (amdgpu_device_has_dc_support(adev)) 545 amdgpu_device_ip_block_add(adev, &dm_ip_block); 546 #endif 547 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 548 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 549 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 550 !amdgpu_sriov_vf(adev)) 551 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 552 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 553 if (!amdgpu_sriov_vf(adev)) 554 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 555 break; 556 case CHIP_SIENNA_CICHLID: 557 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 558 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 559 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 560 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 561 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 562 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 563 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 564 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 565 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 566 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 567 #if defined(CONFIG_DRM_AMD_DC) 568 else if (amdgpu_device_has_dc_support(adev)) 569 amdgpu_device_ip_block_add(adev, &dm_ip_block); 570 #endif 571 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 572 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 573 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 574 if (!amdgpu_sriov_vf(adev)) 575 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 576 577 if (adev->enable_mes) 578 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 579 break; 580 case CHIP_NAVY_FLOUNDER: 581 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 582 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 583 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 584 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 585 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 586 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 587 is_support_sw_smu(adev)) 588 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 589 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 590 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 591 #if defined(CONFIG_DRM_AMD_DC) 592 else if (amdgpu_device_has_dc_support(adev)) 593 amdgpu_device_ip_block_add(adev, &dm_ip_block); 594 #endif 595 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 596 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 597 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 598 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 599 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 600 is_support_sw_smu(adev)) 601 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 602 break; 603 default: 604 return -EINVAL; 605 } 606 607 return 0; 608 } 609 610 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 611 { 612 return adev->nbio.funcs->get_rev_id(adev); 613 } 614 615 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 616 { 617 adev->nbio.funcs->hdp_flush(adev, ring); 618 } 619 620 static void nv_invalidate_hdp(struct amdgpu_device *adev, 621 struct amdgpu_ring *ring) 622 { 623 if (!ring || !ring->funcs->emit_wreg) { 624 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 625 } else { 626 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 627 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 628 } 629 } 630 631 static bool nv_need_full_reset(struct amdgpu_device *adev) 632 { 633 return true; 634 } 635 636 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 637 { 638 u32 sol_reg; 639 640 if (adev->flags & AMD_IS_APU) 641 return false; 642 643 /* Check sOS sign of life register to confirm sys driver and sOS 644 * are already been loaded. 645 */ 646 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 647 if (sol_reg) 648 return true; 649 650 return false; 651 } 652 653 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 654 { 655 656 /* TODO 657 * dummy implement for pcie_replay_count sysfs interface 658 * */ 659 660 return 0; 661 } 662 663 static void nv_init_doorbell_index(struct amdgpu_device *adev) 664 { 665 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 666 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 667 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 668 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 669 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 670 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 671 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 672 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 673 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 674 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 675 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 676 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 677 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 678 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 679 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 680 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 681 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 682 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 683 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 684 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 685 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 686 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 687 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 688 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 689 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 690 691 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 692 adev->doorbell_index.sdma_doorbell_range = 20; 693 } 694 695 static void nv_pre_asic_init(struct amdgpu_device *adev) 696 { 697 } 698 699 static const struct amdgpu_asic_funcs nv_asic_funcs = 700 { 701 .read_disabled_bios = &nv_read_disabled_bios, 702 .read_bios_from_rom = &nv_read_bios_from_rom, 703 .read_register = &nv_read_register, 704 .reset = &nv_asic_reset, 705 .reset_method = &nv_asic_reset_method, 706 .set_vga_state = &nv_vga_set_state, 707 .get_xclk = &nv_get_xclk, 708 .set_uvd_clocks = &nv_set_uvd_clocks, 709 .set_vce_clocks = &nv_set_vce_clocks, 710 .get_config_memsize = &nv_get_config_memsize, 711 .flush_hdp = &nv_flush_hdp, 712 .invalidate_hdp = &nv_invalidate_hdp, 713 .init_doorbell_index = &nv_init_doorbell_index, 714 .need_full_reset = &nv_need_full_reset, 715 .need_reset_on_init = &nv_need_reset_on_init, 716 .get_pcie_replay_count = &nv_get_pcie_replay_count, 717 .supports_baco = &nv_asic_supports_baco, 718 .pre_asic_init = &nv_pre_asic_init, 719 }; 720 721 static int nv_common_early_init(void *handle) 722 { 723 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 724 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 725 726 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 727 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 728 adev->smc_rreg = NULL; 729 adev->smc_wreg = NULL; 730 adev->pcie_rreg = &nv_pcie_rreg; 731 adev->pcie_wreg = &nv_pcie_wreg; 732 adev->pcie_rreg64 = &nv_pcie_rreg64; 733 adev->pcie_wreg64 = &nv_pcie_wreg64; 734 735 /* TODO: will add them during VCN v2 implementation */ 736 adev->uvd_ctx_rreg = NULL; 737 adev->uvd_ctx_wreg = NULL; 738 739 adev->didt_rreg = &nv_didt_rreg; 740 adev->didt_wreg = &nv_didt_wreg; 741 742 adev->asic_funcs = &nv_asic_funcs; 743 744 adev->rev_id = nv_get_rev_id(adev); 745 adev->external_rev_id = 0xff; 746 switch (adev->asic_type) { 747 case CHIP_NAVI10: 748 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 749 AMD_CG_SUPPORT_GFX_CGCG | 750 AMD_CG_SUPPORT_IH_CG | 751 AMD_CG_SUPPORT_HDP_MGCG | 752 AMD_CG_SUPPORT_HDP_LS | 753 AMD_CG_SUPPORT_SDMA_MGCG | 754 AMD_CG_SUPPORT_SDMA_LS | 755 AMD_CG_SUPPORT_MC_MGCG | 756 AMD_CG_SUPPORT_MC_LS | 757 AMD_CG_SUPPORT_ATHUB_MGCG | 758 AMD_CG_SUPPORT_ATHUB_LS | 759 AMD_CG_SUPPORT_VCN_MGCG | 760 AMD_CG_SUPPORT_JPEG_MGCG | 761 AMD_CG_SUPPORT_BIF_MGCG | 762 AMD_CG_SUPPORT_BIF_LS; 763 adev->pg_flags = AMD_PG_SUPPORT_VCN | 764 AMD_PG_SUPPORT_VCN_DPG | 765 AMD_PG_SUPPORT_JPEG | 766 AMD_PG_SUPPORT_ATHUB; 767 adev->external_rev_id = adev->rev_id + 0x1; 768 break; 769 case CHIP_NAVI14: 770 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 771 AMD_CG_SUPPORT_GFX_CGCG | 772 AMD_CG_SUPPORT_IH_CG | 773 AMD_CG_SUPPORT_HDP_MGCG | 774 AMD_CG_SUPPORT_HDP_LS | 775 AMD_CG_SUPPORT_SDMA_MGCG | 776 AMD_CG_SUPPORT_SDMA_LS | 777 AMD_CG_SUPPORT_MC_MGCG | 778 AMD_CG_SUPPORT_MC_LS | 779 AMD_CG_SUPPORT_ATHUB_MGCG | 780 AMD_CG_SUPPORT_ATHUB_LS | 781 AMD_CG_SUPPORT_VCN_MGCG | 782 AMD_CG_SUPPORT_JPEG_MGCG | 783 AMD_CG_SUPPORT_BIF_MGCG | 784 AMD_CG_SUPPORT_BIF_LS; 785 adev->pg_flags = AMD_PG_SUPPORT_VCN | 786 AMD_PG_SUPPORT_JPEG | 787 AMD_PG_SUPPORT_VCN_DPG; 788 adev->external_rev_id = adev->rev_id + 20; 789 break; 790 case CHIP_NAVI12: 791 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 792 AMD_CG_SUPPORT_GFX_MGLS | 793 AMD_CG_SUPPORT_GFX_CGCG | 794 AMD_CG_SUPPORT_GFX_CP_LS | 795 AMD_CG_SUPPORT_GFX_RLC_LS | 796 AMD_CG_SUPPORT_IH_CG | 797 AMD_CG_SUPPORT_HDP_MGCG | 798 AMD_CG_SUPPORT_HDP_LS | 799 AMD_CG_SUPPORT_SDMA_MGCG | 800 AMD_CG_SUPPORT_SDMA_LS | 801 AMD_CG_SUPPORT_MC_MGCG | 802 AMD_CG_SUPPORT_MC_LS | 803 AMD_CG_SUPPORT_ATHUB_MGCG | 804 AMD_CG_SUPPORT_ATHUB_LS | 805 AMD_CG_SUPPORT_VCN_MGCG | 806 AMD_CG_SUPPORT_JPEG_MGCG; 807 adev->pg_flags = AMD_PG_SUPPORT_VCN | 808 AMD_PG_SUPPORT_VCN_DPG | 809 AMD_PG_SUPPORT_JPEG | 810 AMD_PG_SUPPORT_ATHUB; 811 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 812 * as a consequence, the rev_id and external_rev_id are wrong. 813 * workaround it by hardcoding rev_id to 0 (default value). 814 */ 815 if (amdgpu_sriov_vf(adev)) 816 adev->rev_id = 0; 817 adev->external_rev_id = adev->rev_id + 0xa; 818 break; 819 case CHIP_SIENNA_CICHLID: 820 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 821 AMD_CG_SUPPORT_GFX_CGCG | 822 AMD_CG_SUPPORT_GFX_3D_CGCG | 823 AMD_CG_SUPPORT_MC_MGCG | 824 AMD_CG_SUPPORT_VCN_MGCG | 825 AMD_CG_SUPPORT_JPEG_MGCG | 826 AMD_CG_SUPPORT_HDP_MGCG | 827 AMD_CG_SUPPORT_HDP_LS | 828 AMD_CG_SUPPORT_IH_CG | 829 AMD_CG_SUPPORT_MC_LS; 830 adev->pg_flags = AMD_PG_SUPPORT_VCN | 831 AMD_PG_SUPPORT_VCN_DPG | 832 AMD_PG_SUPPORT_JPEG | 833 AMD_PG_SUPPORT_ATHUB | 834 AMD_PG_SUPPORT_MMHUB; 835 if (amdgpu_sriov_vf(adev)) { 836 /* hypervisor control CG and PG enablement */ 837 adev->cg_flags = 0; 838 adev->pg_flags = 0; 839 } 840 adev->external_rev_id = adev->rev_id + 0x28; 841 break; 842 case CHIP_NAVY_FLOUNDER: 843 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 844 AMD_CG_SUPPORT_GFX_CGCG | 845 AMD_CG_SUPPORT_GFX_3D_CGCG | 846 AMD_CG_SUPPORT_VCN_MGCG | 847 AMD_CG_SUPPORT_JPEG_MGCG | 848 AMD_CG_SUPPORT_MC_MGCG | 849 AMD_CG_SUPPORT_MC_LS | 850 AMD_CG_SUPPORT_HDP_MGCG | 851 AMD_CG_SUPPORT_HDP_LS | 852 AMD_CG_SUPPORT_IH_CG; 853 adev->pg_flags = AMD_PG_SUPPORT_VCN | 854 AMD_PG_SUPPORT_VCN_DPG | 855 AMD_PG_SUPPORT_JPEG | 856 AMD_PG_SUPPORT_ATHUB | 857 AMD_PG_SUPPORT_MMHUB; 858 adev->external_rev_id = adev->rev_id + 0x32; 859 break; 860 861 default: 862 /* FIXME: not supported yet */ 863 return -EINVAL; 864 } 865 866 if (amdgpu_sriov_vf(adev)) { 867 amdgpu_virt_init_setting(adev); 868 xgpu_nv_mailbox_set_irq_funcs(adev); 869 } 870 871 return 0; 872 } 873 874 static int nv_common_late_init(void *handle) 875 { 876 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 877 878 if (amdgpu_sriov_vf(adev)) 879 xgpu_nv_mailbox_get_irq(adev); 880 881 return 0; 882 } 883 884 static int nv_common_sw_init(void *handle) 885 { 886 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 887 888 if (amdgpu_sriov_vf(adev)) 889 xgpu_nv_mailbox_add_irq_id(adev); 890 891 return 0; 892 } 893 894 static int nv_common_sw_fini(void *handle) 895 { 896 return 0; 897 } 898 899 static int nv_common_hw_init(void *handle) 900 { 901 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 902 903 /* enable pcie gen2/3 link */ 904 nv_pcie_gen3_enable(adev); 905 /* enable aspm */ 906 nv_program_aspm(adev); 907 /* setup nbio registers */ 908 adev->nbio.funcs->init_registers(adev); 909 /* remap HDP registers to a hole in mmio space, 910 * for the purpose of expose those registers 911 * to process space 912 */ 913 if (adev->nbio.funcs->remap_hdp_registers) 914 adev->nbio.funcs->remap_hdp_registers(adev); 915 /* enable the doorbell aperture */ 916 nv_enable_doorbell_aperture(adev, true); 917 918 return 0; 919 } 920 921 static int nv_common_hw_fini(void *handle) 922 { 923 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 924 925 /* disable the doorbell aperture */ 926 nv_enable_doorbell_aperture(adev, false); 927 928 return 0; 929 } 930 931 static int nv_common_suspend(void *handle) 932 { 933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 934 935 return nv_common_hw_fini(adev); 936 } 937 938 static int nv_common_resume(void *handle) 939 { 940 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 941 942 return nv_common_hw_init(adev); 943 } 944 945 static bool nv_common_is_idle(void *handle) 946 { 947 return true; 948 } 949 950 static int nv_common_wait_for_idle(void *handle) 951 { 952 return 0; 953 } 954 955 static int nv_common_soft_reset(void *handle) 956 { 957 return 0; 958 } 959 960 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 961 bool enable) 962 { 963 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 964 uint32_t hdp_mem_pwr_cntl; 965 966 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 967 AMD_CG_SUPPORT_HDP_DS | 968 AMD_CG_SUPPORT_HDP_SD))) 969 return; 970 971 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 972 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 973 974 /* Before doing clock/power mode switch, 975 * forced on IPH & RC clock */ 976 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 977 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 978 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 979 RC_MEM_CLK_SOFT_OVERRIDE, 1); 980 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 981 982 /* HDP 5.0 doesn't support dynamic power mode switch, 983 * disable clock and power gating before any changing */ 984 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 985 IPH_MEM_POWER_CTRL_EN, 0); 986 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 987 IPH_MEM_POWER_LS_EN, 0); 988 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 989 IPH_MEM_POWER_DS_EN, 0); 990 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 991 IPH_MEM_POWER_SD_EN, 0); 992 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 993 RC_MEM_POWER_CTRL_EN, 0); 994 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 995 RC_MEM_POWER_LS_EN, 0); 996 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 997 RC_MEM_POWER_DS_EN, 0); 998 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 999 RC_MEM_POWER_SD_EN, 0); 1000 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1001 1002 /* only one clock gating mode (LS/DS/SD) can be enabled */ 1003 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1004 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1005 HDP_MEM_POWER_CTRL, 1006 IPH_MEM_POWER_LS_EN, enable); 1007 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1008 HDP_MEM_POWER_CTRL, 1009 RC_MEM_POWER_LS_EN, enable); 1010 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 1011 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1012 HDP_MEM_POWER_CTRL, 1013 IPH_MEM_POWER_DS_EN, enable); 1014 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1015 HDP_MEM_POWER_CTRL, 1016 RC_MEM_POWER_DS_EN, enable); 1017 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 1018 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1019 HDP_MEM_POWER_CTRL, 1020 IPH_MEM_POWER_SD_EN, enable); 1021 /* RC should not use shut down mode, fallback to ds */ 1022 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1023 HDP_MEM_POWER_CTRL, 1024 RC_MEM_POWER_DS_EN, enable); 1025 } 1026 1027 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 1028 * be set for SRAM LS/DS/SD */ 1029 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 1030 AMD_CG_SUPPORT_HDP_SD)) { 1031 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1032 IPH_MEM_POWER_CTRL_EN, 1); 1033 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1034 RC_MEM_POWER_CTRL_EN, 1); 1035 } 1036 1037 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1038 1039 /* restore IPH & RC clock override after clock/power mode changing */ 1040 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 1041 } 1042 1043 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 1044 bool enable) 1045 { 1046 uint32_t hdp_clk_cntl; 1047 1048 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1049 return; 1050 1051 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1052 1053 if (enable) { 1054 hdp_clk_cntl &= 1055 ~(uint32_t) 1056 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1057 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1058 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1059 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1060 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1061 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 1062 } else { 1063 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1064 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1065 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1066 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1067 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1068 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 1069 } 1070 1071 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1072 } 1073 1074 static int nv_common_set_clockgating_state(void *handle, 1075 enum amd_clockgating_state state) 1076 { 1077 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1078 1079 if (amdgpu_sriov_vf(adev)) 1080 return 0; 1081 1082 switch (adev->asic_type) { 1083 case CHIP_NAVI10: 1084 case CHIP_NAVI14: 1085 case CHIP_NAVI12: 1086 case CHIP_SIENNA_CICHLID: 1087 case CHIP_NAVY_FLOUNDER: 1088 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1089 state == AMD_CG_STATE_GATE); 1090 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1091 state == AMD_CG_STATE_GATE); 1092 nv_update_hdp_mem_power_gating(adev, 1093 state == AMD_CG_STATE_GATE); 1094 nv_update_hdp_clock_gating(adev, 1095 state == AMD_CG_STATE_GATE); 1096 break; 1097 default: 1098 break; 1099 } 1100 return 0; 1101 } 1102 1103 static int nv_common_set_powergating_state(void *handle, 1104 enum amd_powergating_state state) 1105 { 1106 /* TODO */ 1107 return 0; 1108 } 1109 1110 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1111 { 1112 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1113 uint32_t tmp; 1114 1115 if (amdgpu_sriov_vf(adev)) 1116 *flags = 0; 1117 1118 adev->nbio.funcs->get_clockgating_state(adev, flags); 1119 1120 /* AMD_CG_SUPPORT_HDP_MGCG */ 1121 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1122 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1123 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1124 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1125 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1126 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1127 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 1128 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1129 1130 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 1131 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1132 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 1133 *flags |= AMD_CG_SUPPORT_HDP_LS; 1134 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1135 *flags |= AMD_CG_SUPPORT_HDP_DS; 1136 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1137 *flags |= AMD_CG_SUPPORT_HDP_SD; 1138 1139 return; 1140 } 1141 1142 static const struct amd_ip_funcs nv_common_ip_funcs = { 1143 .name = "nv_common", 1144 .early_init = nv_common_early_init, 1145 .late_init = nv_common_late_init, 1146 .sw_init = nv_common_sw_init, 1147 .sw_fini = nv_common_sw_fini, 1148 .hw_init = nv_common_hw_init, 1149 .hw_fini = nv_common_hw_fini, 1150 .suspend = nv_common_suspend, 1151 .resume = nv_common_resume, 1152 .is_idle = nv_common_is_idle, 1153 .wait_for_idle = nv_common_wait_for_idle, 1154 .soft_reset = nv_common_soft_reset, 1155 .set_clockgating_state = nv_common_set_clockgating_state, 1156 .set_powergating_state = nv_common_set_powergating_state, 1157 .get_clockgating_state = nv_common_get_clockgating_state, 1158 }; 1159