1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "dce_virtual.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 { 73 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 74 .max_width = 4096, 75 .max_height = 2304, 76 .max_pixels_per_frame = 4096 * 2304, 77 .max_level = 0, 78 }, 79 { 80 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 81 .max_width = 4096, 82 .max_height = 2304, 83 .max_pixels_per_frame = 4096 * 2304, 84 .max_level = 0, 85 }, 86 }; 87 88 static const struct amdgpu_video_codecs nv_video_codecs_encode = 89 { 90 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 91 .codec_array = nv_video_codecs_encode_array, 92 }; 93 94 /* Navi1x */ 95 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 96 { 97 { 98 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 99 .max_width = 4096, 100 .max_height = 4096, 101 .max_pixels_per_frame = 4096 * 4096, 102 .max_level = 3, 103 }, 104 { 105 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 106 .max_width = 4096, 107 .max_height = 4096, 108 .max_pixels_per_frame = 4096 * 4096, 109 .max_level = 5, 110 }, 111 { 112 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 113 .max_width = 4096, 114 .max_height = 4096, 115 .max_pixels_per_frame = 4096 * 4096, 116 .max_level = 52, 117 }, 118 { 119 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 120 .max_width = 4096, 121 .max_height = 4096, 122 .max_pixels_per_frame = 4096 * 4096, 123 .max_level = 4, 124 }, 125 { 126 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 127 .max_width = 8192, 128 .max_height = 4352, 129 .max_pixels_per_frame = 8192 * 4352, 130 .max_level = 186, 131 }, 132 { 133 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 134 .max_width = 4096, 135 .max_height = 4096, 136 .max_pixels_per_frame = 4096 * 4096, 137 .max_level = 0, 138 }, 139 { 140 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 141 .max_width = 8192, 142 .max_height = 4352, 143 .max_pixels_per_frame = 8192 * 4352, 144 .max_level = 0, 145 }, 146 }; 147 148 static const struct amdgpu_video_codecs nv_video_codecs_decode = 149 { 150 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 151 .codec_array = nv_video_codecs_decode_array, 152 }; 153 154 /* Sienna Cichlid */ 155 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 156 { 157 { 158 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 159 .max_width = 4096, 160 .max_height = 4096, 161 .max_pixels_per_frame = 4096 * 4096, 162 .max_level = 3, 163 }, 164 { 165 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 166 .max_width = 4096, 167 .max_height = 4096, 168 .max_pixels_per_frame = 4096 * 4096, 169 .max_level = 5, 170 }, 171 { 172 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 173 .max_width = 4096, 174 .max_height = 4096, 175 .max_pixels_per_frame = 4096 * 4096, 176 .max_level = 52, 177 }, 178 { 179 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 180 .max_width = 4096, 181 .max_height = 4096, 182 .max_pixels_per_frame = 4096 * 4096, 183 .max_level = 4, 184 }, 185 { 186 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 187 .max_width = 8192, 188 .max_height = 4352, 189 .max_pixels_per_frame = 8192 * 4352, 190 .max_level = 186, 191 }, 192 { 193 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 194 .max_width = 4096, 195 .max_height = 4096, 196 .max_pixels_per_frame = 4096 * 4096, 197 .max_level = 0, 198 }, 199 { 200 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 201 .max_width = 8192, 202 .max_height = 4352, 203 .max_pixels_per_frame = 8192 * 4352, 204 .max_level = 0, 205 }, 206 { 207 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 208 .max_width = 8192, 209 .max_height = 4352, 210 .max_pixels_per_frame = 8192 * 4352, 211 .max_level = 0, 212 }, 213 }; 214 215 static const struct amdgpu_video_codecs sc_video_codecs_decode = 216 { 217 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 218 .codec_array = sc_video_codecs_decode_array, 219 }; 220 221 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 222 const struct amdgpu_video_codecs **codecs) 223 { 224 switch (adev->asic_type) { 225 case CHIP_SIENNA_CICHLID: 226 case CHIP_NAVY_FLOUNDER: 227 case CHIP_DIMGREY_CAVEFISH: 228 case CHIP_VANGOGH: 229 if (encode) 230 *codecs = &nv_video_codecs_encode; 231 else 232 *codecs = &sc_video_codecs_decode; 233 return 0; 234 case CHIP_NAVI10: 235 case CHIP_NAVI14: 236 case CHIP_NAVI12: 237 if (encode) 238 *codecs = &nv_video_codecs_encode; 239 else 240 *codecs = &nv_video_codecs_decode; 241 return 0; 242 default: 243 return -EINVAL; 244 } 245 } 246 247 /* 248 * Indirect registers accessor 249 */ 250 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 251 { 252 unsigned long address, data; 253 address = adev->nbio.funcs->get_pcie_index_offset(adev); 254 data = adev->nbio.funcs->get_pcie_data_offset(adev); 255 256 return amdgpu_device_indirect_rreg(adev, address, data, reg); 257 } 258 259 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 260 { 261 unsigned long address, data; 262 263 address = adev->nbio.funcs->get_pcie_index_offset(adev); 264 data = adev->nbio.funcs->get_pcie_data_offset(adev); 265 266 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 267 } 268 269 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 270 { 271 unsigned long address, data; 272 address = adev->nbio.funcs->get_pcie_index_offset(adev); 273 data = adev->nbio.funcs->get_pcie_data_offset(adev); 274 275 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 276 } 277 278 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 279 { 280 unsigned long flags, address, data; 281 u32 r; 282 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 283 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 284 285 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 286 WREG32(address, reg * 4); 287 (void)RREG32(address); 288 r = RREG32(data); 289 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 290 return r; 291 } 292 293 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 294 { 295 unsigned long address, data; 296 297 address = adev->nbio.funcs->get_pcie_index_offset(adev); 298 data = adev->nbio.funcs->get_pcie_data_offset(adev); 299 300 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 301 } 302 303 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 304 { 305 unsigned long flags, address, data; 306 307 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 308 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 309 310 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 311 WREG32(address, reg * 4); 312 (void)RREG32(address); 313 WREG32(data, v); 314 (void)RREG32(data); 315 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 316 } 317 318 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 319 { 320 unsigned long flags, address, data; 321 u32 r; 322 323 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 324 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 325 326 spin_lock_irqsave(&adev->didt_idx_lock, flags); 327 WREG32(address, (reg)); 328 r = RREG32(data); 329 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 330 return r; 331 } 332 333 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 334 { 335 unsigned long flags, address, data; 336 337 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 338 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 339 340 spin_lock_irqsave(&adev->didt_idx_lock, flags); 341 WREG32(address, (reg)); 342 WREG32(data, (v)); 343 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 344 } 345 346 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 347 { 348 return adev->nbio.funcs->get_memsize(adev); 349 } 350 351 static u32 nv_get_xclk(struct amdgpu_device *adev) 352 { 353 return adev->clock.spll.reference_freq; 354 } 355 356 357 void nv_grbm_select(struct amdgpu_device *adev, 358 u32 me, u32 pipe, u32 queue, u32 vmid) 359 { 360 u32 grbm_gfx_cntl = 0; 361 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 362 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 363 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 364 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 365 366 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 367 } 368 369 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 370 { 371 /* todo */ 372 } 373 374 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 375 { 376 /* todo */ 377 return false; 378 } 379 380 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 381 u8 *bios, u32 length_bytes) 382 { 383 u32 *dw_ptr; 384 u32 i, length_dw; 385 u32 rom_index_offset, rom_data_offset; 386 387 if (bios == NULL) 388 return false; 389 if (length_bytes == 0) 390 return false; 391 /* APU vbios image is part of sbios image */ 392 if (adev->flags & AMD_IS_APU) 393 return false; 394 395 dw_ptr = (u32 *)bios; 396 length_dw = ALIGN(length_bytes, 4) / 4; 397 398 rom_index_offset = 399 adev->smuio.funcs->get_rom_index_offset(adev); 400 rom_data_offset = 401 adev->smuio.funcs->get_rom_data_offset(adev); 402 403 /* set rom index to 0 */ 404 WREG32(rom_index_offset, 0); 405 /* read out the rom data */ 406 for (i = 0; i < length_dw; i++) 407 dw_ptr[i] = RREG32(rom_data_offset); 408 409 return true; 410 } 411 412 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 413 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 414 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 415 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 416 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 417 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 418 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 419 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 420 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 421 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 422 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 423 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 424 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 425 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 426 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 427 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 428 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 429 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 430 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 431 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 432 }; 433 434 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 435 u32 sh_num, u32 reg_offset) 436 { 437 uint32_t val; 438 439 mutex_lock(&adev->grbm_idx_mutex); 440 if (se_num != 0xffffffff || sh_num != 0xffffffff) 441 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 442 443 val = RREG32(reg_offset); 444 445 if (se_num != 0xffffffff || sh_num != 0xffffffff) 446 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 447 mutex_unlock(&adev->grbm_idx_mutex); 448 return val; 449 } 450 451 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 452 bool indexed, u32 se_num, 453 u32 sh_num, u32 reg_offset) 454 { 455 if (indexed) { 456 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 457 } else { 458 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 459 return adev->gfx.config.gb_addr_config; 460 return RREG32(reg_offset); 461 } 462 } 463 464 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 465 u32 sh_num, u32 reg_offset, u32 *value) 466 { 467 uint32_t i; 468 struct soc15_allowed_register_entry *en; 469 470 *value = 0; 471 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 472 en = &nv_allowed_read_registers[i]; 473 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 474 reg_offset != 475 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 476 continue; 477 478 *value = nv_get_register_value(adev, 479 nv_allowed_read_registers[i].grbm_indexed, 480 se_num, sh_num, reg_offset); 481 return 0; 482 } 483 return -EINVAL; 484 } 485 486 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 487 { 488 u32 i; 489 int ret = 0; 490 491 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 492 493 /* disable BM */ 494 pci_clear_master(adev->pdev); 495 496 amdgpu_device_cache_pci_state(adev->pdev); 497 498 ret = amdgpu_dpm_mode2_reset(adev); 499 if (ret) 500 dev_err(adev->dev, "GPU mode2 reset failed\n"); 501 502 amdgpu_device_load_pci_state(adev->pdev); 503 504 /* wait for asic to come out of reset */ 505 for (i = 0; i < adev->usec_timeout; i++) { 506 u32 memsize = adev->nbio.funcs->get_memsize(adev); 507 508 if (memsize != 0xffffffff) 509 break; 510 udelay(1); 511 } 512 513 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 514 515 return ret; 516 } 517 518 static enum amd_reset_method 519 nv_asic_reset_method(struct amdgpu_device *adev) 520 { 521 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 522 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 523 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 524 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 525 return amdgpu_reset_method; 526 527 if (amdgpu_reset_method != -1) 528 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 529 amdgpu_reset_method); 530 531 switch (adev->asic_type) { 532 case CHIP_VANGOGH: 533 return AMD_RESET_METHOD_MODE2; 534 case CHIP_SIENNA_CICHLID: 535 case CHIP_NAVY_FLOUNDER: 536 case CHIP_DIMGREY_CAVEFISH: 537 return AMD_RESET_METHOD_MODE1; 538 default: 539 if (amdgpu_dpm_is_baco_supported(adev)) 540 return AMD_RESET_METHOD_BACO; 541 else 542 return AMD_RESET_METHOD_MODE1; 543 } 544 } 545 546 static int nv_asic_reset(struct amdgpu_device *adev) 547 { 548 int ret = 0; 549 550 switch (nv_asic_reset_method(adev)) { 551 case AMD_RESET_METHOD_PCI: 552 dev_info(adev->dev, "PCI reset\n"); 553 ret = amdgpu_device_pci_reset(adev); 554 break; 555 case AMD_RESET_METHOD_BACO: 556 dev_info(adev->dev, "BACO reset\n"); 557 ret = amdgpu_dpm_baco_reset(adev); 558 break; 559 case AMD_RESET_METHOD_MODE2: 560 dev_info(adev->dev, "MODE2 reset\n"); 561 ret = nv_asic_mode2_reset(adev); 562 break; 563 default: 564 dev_info(adev->dev, "MODE1 reset\n"); 565 ret = amdgpu_device_mode1_reset(adev); 566 break; 567 } 568 569 return ret; 570 } 571 572 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 573 { 574 /* todo */ 575 return 0; 576 } 577 578 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 579 { 580 /* todo */ 581 return 0; 582 } 583 584 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 585 { 586 if (pci_is_root_bus(adev->pdev->bus)) 587 return; 588 589 if (amdgpu_pcie_gen2 == 0) 590 return; 591 592 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 593 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 594 return; 595 596 /* todo */ 597 } 598 599 static void nv_program_aspm(struct amdgpu_device *adev) 600 { 601 if (amdgpu_aspm != 1) 602 return; 603 604 if (!(adev->flags & AMD_IS_APU) && 605 (adev->nbio.funcs->program_aspm)) 606 adev->nbio.funcs->program_aspm(adev); 607 608 } 609 610 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 611 bool enable) 612 { 613 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 614 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 615 } 616 617 static const struct amdgpu_ip_block_version nv_common_ip_block = 618 { 619 .type = AMD_IP_BLOCK_TYPE_COMMON, 620 .major = 1, 621 .minor = 0, 622 .rev = 0, 623 .funcs = &nv_common_ip_funcs, 624 }; 625 626 static int nv_reg_base_init(struct amdgpu_device *adev) 627 { 628 int r; 629 630 if (amdgpu_discovery) { 631 r = amdgpu_discovery_reg_base_init(adev); 632 if (r) { 633 DRM_WARN("failed to init reg base from ip discovery table, " 634 "fallback to legacy init method\n"); 635 goto legacy_init; 636 } 637 638 return 0; 639 } 640 641 legacy_init: 642 switch (adev->asic_type) { 643 case CHIP_NAVI10: 644 navi10_reg_base_init(adev); 645 break; 646 case CHIP_NAVI14: 647 navi14_reg_base_init(adev); 648 break; 649 case CHIP_NAVI12: 650 navi12_reg_base_init(adev); 651 break; 652 case CHIP_SIENNA_CICHLID: 653 case CHIP_NAVY_FLOUNDER: 654 sienna_cichlid_reg_base_init(adev); 655 break; 656 case CHIP_VANGOGH: 657 vangogh_reg_base_init(adev); 658 break; 659 case CHIP_DIMGREY_CAVEFISH: 660 dimgrey_cavefish_reg_base_init(adev); 661 break; 662 default: 663 return -EINVAL; 664 } 665 666 return 0; 667 } 668 669 void nv_set_virt_ops(struct amdgpu_device *adev) 670 { 671 adev->virt.ops = &xgpu_nv_virt_ops; 672 } 673 674 static bool nv_is_headless_sku(struct pci_dev *pdev) 675 { 676 if ((pdev->device == 0x731E && 677 (pdev->revision == 0xC6 || pdev->revision == 0xC7)) || 678 (pdev->device == 0x7340 && pdev->revision == 0xC9) || 679 (pdev->device == 0x7360 && pdev->revision == 0xC7)) 680 return true; 681 return false; 682 } 683 684 int nv_set_ip_blocks(struct amdgpu_device *adev) 685 { 686 int r; 687 688 if (adev->flags & AMD_IS_APU) { 689 adev->nbio.funcs = &nbio_v7_2_funcs; 690 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 691 } else { 692 adev->nbio.funcs = &nbio_v2_3_funcs; 693 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 694 } 695 adev->hdp.funcs = &hdp_v5_0_funcs; 696 697 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 698 adev->smuio.funcs = &smuio_v11_0_6_funcs; 699 else 700 adev->smuio.funcs = &smuio_v11_0_funcs; 701 702 if (adev->asic_type == CHIP_SIENNA_CICHLID) 703 adev->gmc.xgmi.supported = true; 704 705 /* Set IP register base before any HW register access */ 706 r = nv_reg_base_init(adev); 707 if (r) 708 return r; 709 710 switch (adev->asic_type) { 711 case CHIP_NAVI10: 712 case CHIP_NAVI14: 713 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 714 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 715 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 716 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 717 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 718 !amdgpu_sriov_vf(adev)) 719 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 720 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 721 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 722 #if defined(CONFIG_DRM_AMD_DC) 723 else if (amdgpu_device_has_dc_support(adev)) 724 amdgpu_device_ip_block_add(adev, &dm_ip_block); 725 #endif 726 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 727 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 728 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 729 !amdgpu_sriov_vf(adev)) 730 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 731 if (!nv_is_headless_sku(adev->pdev)) 732 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 733 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 734 if (adev->enable_mes) 735 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 736 break; 737 case CHIP_NAVI12: 738 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 739 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 740 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 741 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 742 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 743 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 744 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 745 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 746 #if defined(CONFIG_DRM_AMD_DC) 747 else if (amdgpu_device_has_dc_support(adev)) 748 amdgpu_device_ip_block_add(adev, &dm_ip_block); 749 #endif 750 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 751 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 752 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 753 !amdgpu_sriov_vf(adev)) 754 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 755 if (!nv_is_headless_sku(adev->pdev)) 756 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 757 if (!amdgpu_sriov_vf(adev)) 758 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 759 break; 760 case CHIP_SIENNA_CICHLID: 761 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 762 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 763 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 764 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 765 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 766 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 767 is_support_sw_smu(adev)) 768 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 769 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 770 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 771 #if defined(CONFIG_DRM_AMD_DC) 772 else if (amdgpu_device_has_dc_support(adev)) 773 amdgpu_device_ip_block_add(adev, &dm_ip_block); 774 #endif 775 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 776 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 777 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 778 if (!amdgpu_sriov_vf(adev)) 779 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 780 781 if (adev->enable_mes) 782 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 783 break; 784 case CHIP_NAVY_FLOUNDER: 785 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 786 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 787 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 788 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 789 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 790 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 791 is_support_sw_smu(adev)) 792 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 793 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 794 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 795 #if defined(CONFIG_DRM_AMD_DC) 796 else if (amdgpu_device_has_dc_support(adev)) 797 amdgpu_device_ip_block_add(adev, &dm_ip_block); 798 #endif 799 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 800 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 801 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 802 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 803 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 804 is_support_sw_smu(adev)) 805 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 806 break; 807 case CHIP_VANGOGH: 808 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 809 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 810 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 811 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 812 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 813 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 814 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 815 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 816 #if defined(CONFIG_DRM_AMD_DC) 817 else if (amdgpu_device_has_dc_support(adev)) 818 amdgpu_device_ip_block_add(adev, &dm_ip_block); 819 #endif 820 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 821 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 822 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 823 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 824 break; 825 case CHIP_DIMGREY_CAVEFISH: 826 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 827 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 828 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 829 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 830 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 831 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 832 is_support_sw_smu(adev)) 833 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 834 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 835 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 836 #if defined(CONFIG_DRM_AMD_DC) 837 else if (amdgpu_device_has_dc_support(adev)) 838 amdgpu_device_ip_block_add(adev, &dm_ip_block); 839 #endif 840 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 841 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 842 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 843 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 844 break; 845 default: 846 return -EINVAL; 847 } 848 849 return 0; 850 } 851 852 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 853 { 854 return adev->nbio.funcs->get_rev_id(adev); 855 } 856 857 static bool nv_need_full_reset(struct amdgpu_device *adev) 858 { 859 return true; 860 } 861 862 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 863 { 864 u32 sol_reg; 865 866 if (adev->flags & AMD_IS_APU) 867 return false; 868 869 /* Check sOS sign of life register to confirm sys driver and sOS 870 * are already been loaded. 871 */ 872 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 873 if (sol_reg) 874 return true; 875 876 return false; 877 } 878 879 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 880 { 881 882 /* TODO 883 * dummy implement for pcie_replay_count sysfs interface 884 * */ 885 886 return 0; 887 } 888 889 static void nv_init_doorbell_index(struct amdgpu_device *adev) 890 { 891 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 892 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 893 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 894 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 895 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 896 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 897 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 898 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 899 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 900 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 901 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 902 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 903 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 904 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 905 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 906 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 907 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 908 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 909 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 910 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 911 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 912 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 913 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 914 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 915 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 916 917 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 918 adev->doorbell_index.sdma_doorbell_range = 20; 919 } 920 921 static void nv_pre_asic_init(struct amdgpu_device *adev) 922 { 923 } 924 925 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 926 bool enter) 927 { 928 if (enter) 929 amdgpu_gfx_rlc_enter_safe_mode(adev); 930 else 931 amdgpu_gfx_rlc_exit_safe_mode(adev); 932 933 if (adev->gfx.funcs->update_perfmon_mgcg) 934 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 935 936 if (!(adev->flags & AMD_IS_APU) && 937 (adev->nbio.funcs->enable_aspm)) 938 adev->nbio.funcs->enable_aspm(adev, !enter); 939 940 return 0; 941 } 942 943 static const struct amdgpu_asic_funcs nv_asic_funcs = 944 { 945 .read_disabled_bios = &nv_read_disabled_bios, 946 .read_bios_from_rom = &nv_read_bios_from_rom, 947 .read_register = &nv_read_register, 948 .reset = &nv_asic_reset, 949 .reset_method = &nv_asic_reset_method, 950 .set_vga_state = &nv_vga_set_state, 951 .get_xclk = &nv_get_xclk, 952 .set_uvd_clocks = &nv_set_uvd_clocks, 953 .set_vce_clocks = &nv_set_vce_clocks, 954 .get_config_memsize = &nv_get_config_memsize, 955 .init_doorbell_index = &nv_init_doorbell_index, 956 .need_full_reset = &nv_need_full_reset, 957 .need_reset_on_init = &nv_need_reset_on_init, 958 .get_pcie_replay_count = &nv_get_pcie_replay_count, 959 .supports_baco = &amdgpu_dpm_is_baco_supported, 960 .pre_asic_init = &nv_pre_asic_init, 961 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 962 .query_video_codecs = &nv_query_video_codecs, 963 }; 964 965 static int nv_common_early_init(void *handle) 966 { 967 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 968 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 969 970 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 971 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 972 adev->smc_rreg = NULL; 973 adev->smc_wreg = NULL; 974 adev->pcie_rreg = &nv_pcie_rreg; 975 adev->pcie_wreg = &nv_pcie_wreg; 976 adev->pcie_rreg64 = &nv_pcie_rreg64; 977 adev->pcie_wreg64 = &nv_pcie_wreg64; 978 adev->pciep_rreg = &nv_pcie_port_rreg; 979 adev->pciep_wreg = &nv_pcie_port_wreg; 980 981 /* TODO: will add them during VCN v2 implementation */ 982 adev->uvd_ctx_rreg = NULL; 983 adev->uvd_ctx_wreg = NULL; 984 985 adev->didt_rreg = &nv_didt_rreg; 986 adev->didt_wreg = &nv_didt_wreg; 987 988 adev->asic_funcs = &nv_asic_funcs; 989 990 adev->rev_id = nv_get_rev_id(adev); 991 adev->external_rev_id = 0xff; 992 switch (adev->asic_type) { 993 case CHIP_NAVI10: 994 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 995 AMD_CG_SUPPORT_GFX_CGCG | 996 AMD_CG_SUPPORT_IH_CG | 997 AMD_CG_SUPPORT_HDP_MGCG | 998 AMD_CG_SUPPORT_HDP_LS | 999 AMD_CG_SUPPORT_SDMA_MGCG | 1000 AMD_CG_SUPPORT_SDMA_LS | 1001 AMD_CG_SUPPORT_MC_MGCG | 1002 AMD_CG_SUPPORT_MC_LS | 1003 AMD_CG_SUPPORT_ATHUB_MGCG | 1004 AMD_CG_SUPPORT_ATHUB_LS | 1005 AMD_CG_SUPPORT_VCN_MGCG | 1006 AMD_CG_SUPPORT_JPEG_MGCG | 1007 AMD_CG_SUPPORT_BIF_MGCG | 1008 AMD_CG_SUPPORT_BIF_LS; 1009 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1010 AMD_PG_SUPPORT_VCN_DPG | 1011 AMD_PG_SUPPORT_JPEG | 1012 AMD_PG_SUPPORT_ATHUB; 1013 adev->external_rev_id = adev->rev_id + 0x1; 1014 break; 1015 case CHIP_NAVI14: 1016 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1017 AMD_CG_SUPPORT_GFX_CGCG | 1018 AMD_CG_SUPPORT_IH_CG | 1019 AMD_CG_SUPPORT_HDP_MGCG | 1020 AMD_CG_SUPPORT_HDP_LS | 1021 AMD_CG_SUPPORT_SDMA_MGCG | 1022 AMD_CG_SUPPORT_SDMA_LS | 1023 AMD_CG_SUPPORT_MC_MGCG | 1024 AMD_CG_SUPPORT_MC_LS | 1025 AMD_CG_SUPPORT_ATHUB_MGCG | 1026 AMD_CG_SUPPORT_ATHUB_LS | 1027 AMD_CG_SUPPORT_VCN_MGCG | 1028 AMD_CG_SUPPORT_JPEG_MGCG | 1029 AMD_CG_SUPPORT_BIF_MGCG | 1030 AMD_CG_SUPPORT_BIF_LS; 1031 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1032 AMD_PG_SUPPORT_JPEG | 1033 AMD_PG_SUPPORT_VCN_DPG; 1034 adev->external_rev_id = adev->rev_id + 20; 1035 break; 1036 case CHIP_NAVI12: 1037 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1038 AMD_CG_SUPPORT_GFX_MGLS | 1039 AMD_CG_SUPPORT_GFX_CGCG | 1040 AMD_CG_SUPPORT_GFX_CP_LS | 1041 AMD_CG_SUPPORT_GFX_RLC_LS | 1042 AMD_CG_SUPPORT_IH_CG | 1043 AMD_CG_SUPPORT_HDP_MGCG | 1044 AMD_CG_SUPPORT_HDP_LS | 1045 AMD_CG_SUPPORT_SDMA_MGCG | 1046 AMD_CG_SUPPORT_SDMA_LS | 1047 AMD_CG_SUPPORT_MC_MGCG | 1048 AMD_CG_SUPPORT_MC_LS | 1049 AMD_CG_SUPPORT_ATHUB_MGCG | 1050 AMD_CG_SUPPORT_ATHUB_LS | 1051 AMD_CG_SUPPORT_VCN_MGCG | 1052 AMD_CG_SUPPORT_JPEG_MGCG; 1053 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1054 AMD_PG_SUPPORT_VCN_DPG | 1055 AMD_PG_SUPPORT_JPEG | 1056 AMD_PG_SUPPORT_ATHUB; 1057 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 1058 * as a consequence, the rev_id and external_rev_id are wrong. 1059 * workaround it by hardcoding rev_id to 0 (default value). 1060 */ 1061 if (amdgpu_sriov_vf(adev)) 1062 adev->rev_id = 0; 1063 adev->external_rev_id = adev->rev_id + 0xa; 1064 break; 1065 case CHIP_SIENNA_CICHLID: 1066 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1067 AMD_CG_SUPPORT_GFX_CGCG | 1068 AMD_CG_SUPPORT_GFX_3D_CGCG | 1069 AMD_CG_SUPPORT_MC_MGCG | 1070 AMD_CG_SUPPORT_VCN_MGCG | 1071 AMD_CG_SUPPORT_JPEG_MGCG | 1072 AMD_CG_SUPPORT_HDP_MGCG | 1073 AMD_CG_SUPPORT_HDP_LS | 1074 AMD_CG_SUPPORT_IH_CG | 1075 AMD_CG_SUPPORT_MC_LS; 1076 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1077 AMD_PG_SUPPORT_VCN_DPG | 1078 AMD_PG_SUPPORT_JPEG | 1079 AMD_PG_SUPPORT_ATHUB | 1080 AMD_PG_SUPPORT_MMHUB; 1081 if (amdgpu_sriov_vf(adev)) { 1082 /* hypervisor control CG and PG enablement */ 1083 adev->cg_flags = 0; 1084 adev->pg_flags = 0; 1085 } 1086 adev->external_rev_id = adev->rev_id + 0x28; 1087 break; 1088 case CHIP_NAVY_FLOUNDER: 1089 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1090 AMD_CG_SUPPORT_GFX_CGCG | 1091 AMD_CG_SUPPORT_GFX_3D_CGCG | 1092 AMD_CG_SUPPORT_VCN_MGCG | 1093 AMD_CG_SUPPORT_JPEG_MGCG | 1094 AMD_CG_SUPPORT_MC_MGCG | 1095 AMD_CG_SUPPORT_MC_LS | 1096 AMD_CG_SUPPORT_HDP_MGCG | 1097 AMD_CG_SUPPORT_HDP_LS | 1098 AMD_CG_SUPPORT_IH_CG; 1099 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1100 AMD_PG_SUPPORT_VCN_DPG | 1101 AMD_PG_SUPPORT_JPEG | 1102 AMD_PG_SUPPORT_ATHUB | 1103 AMD_PG_SUPPORT_MMHUB; 1104 adev->external_rev_id = adev->rev_id + 0x32; 1105 break; 1106 1107 case CHIP_VANGOGH: 1108 adev->apu_flags |= AMD_APU_IS_VANGOGH; 1109 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1110 AMD_CG_SUPPORT_GFX_MGLS | 1111 AMD_CG_SUPPORT_GFX_CP_LS | 1112 AMD_CG_SUPPORT_GFX_RLC_LS | 1113 AMD_CG_SUPPORT_GFX_CGCG | 1114 AMD_CG_SUPPORT_GFX_CGLS | 1115 AMD_CG_SUPPORT_GFX_3D_CGCG | 1116 AMD_CG_SUPPORT_GFX_3D_CGLS | 1117 AMD_CG_SUPPORT_MC_MGCG | 1118 AMD_CG_SUPPORT_MC_LS | 1119 AMD_CG_SUPPORT_GFX_FGCG | 1120 AMD_CG_SUPPORT_VCN_MGCG | 1121 AMD_CG_SUPPORT_JPEG_MGCG; 1122 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1123 AMD_PG_SUPPORT_VCN | 1124 AMD_PG_SUPPORT_VCN_DPG | 1125 AMD_PG_SUPPORT_JPEG; 1126 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 1127 adev->external_rev_id = adev->rev_id + 0x01; 1128 break; 1129 case CHIP_DIMGREY_CAVEFISH: 1130 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1131 AMD_CG_SUPPORT_GFX_CGCG | 1132 AMD_CG_SUPPORT_GFX_3D_CGCG | 1133 AMD_CG_SUPPORT_VCN_MGCG | 1134 AMD_CG_SUPPORT_JPEG_MGCG | 1135 AMD_CG_SUPPORT_MC_MGCG | 1136 AMD_CG_SUPPORT_MC_LS | 1137 AMD_CG_SUPPORT_HDP_MGCG | 1138 AMD_CG_SUPPORT_HDP_LS | 1139 AMD_CG_SUPPORT_IH_CG; 1140 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1141 AMD_PG_SUPPORT_VCN_DPG | 1142 AMD_PG_SUPPORT_JPEG | 1143 AMD_PG_SUPPORT_ATHUB | 1144 AMD_PG_SUPPORT_MMHUB; 1145 adev->external_rev_id = adev->rev_id + 0x3c; 1146 break; 1147 default: 1148 /* FIXME: not supported yet */ 1149 return -EINVAL; 1150 } 1151 1152 if (amdgpu_sriov_vf(adev)) { 1153 amdgpu_virt_init_setting(adev); 1154 xgpu_nv_mailbox_set_irq_funcs(adev); 1155 } 1156 1157 return 0; 1158 } 1159 1160 static int nv_common_late_init(void *handle) 1161 { 1162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1163 1164 if (amdgpu_sriov_vf(adev)) 1165 xgpu_nv_mailbox_get_irq(adev); 1166 1167 return 0; 1168 } 1169 1170 static int nv_common_sw_init(void *handle) 1171 { 1172 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1173 1174 if (amdgpu_sriov_vf(adev)) 1175 xgpu_nv_mailbox_add_irq_id(adev); 1176 1177 return 0; 1178 } 1179 1180 static int nv_common_sw_fini(void *handle) 1181 { 1182 return 0; 1183 } 1184 1185 static int nv_common_hw_init(void *handle) 1186 { 1187 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1188 1189 /* enable pcie gen2/3 link */ 1190 nv_pcie_gen3_enable(adev); 1191 /* enable aspm */ 1192 nv_program_aspm(adev); 1193 /* setup nbio registers */ 1194 adev->nbio.funcs->init_registers(adev); 1195 /* remap HDP registers to a hole in mmio space, 1196 * for the purpose of expose those registers 1197 * to process space 1198 */ 1199 if (adev->nbio.funcs->remap_hdp_registers) 1200 adev->nbio.funcs->remap_hdp_registers(adev); 1201 /* enable the doorbell aperture */ 1202 nv_enable_doorbell_aperture(adev, true); 1203 1204 return 0; 1205 } 1206 1207 static int nv_common_hw_fini(void *handle) 1208 { 1209 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1210 1211 /* disable the doorbell aperture */ 1212 nv_enable_doorbell_aperture(adev, false); 1213 1214 return 0; 1215 } 1216 1217 static int nv_common_suspend(void *handle) 1218 { 1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1220 1221 return nv_common_hw_fini(adev); 1222 } 1223 1224 static int nv_common_resume(void *handle) 1225 { 1226 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1227 1228 return nv_common_hw_init(adev); 1229 } 1230 1231 static bool nv_common_is_idle(void *handle) 1232 { 1233 return true; 1234 } 1235 1236 static int nv_common_wait_for_idle(void *handle) 1237 { 1238 return 0; 1239 } 1240 1241 static int nv_common_soft_reset(void *handle) 1242 { 1243 return 0; 1244 } 1245 1246 static int nv_common_set_clockgating_state(void *handle, 1247 enum amd_clockgating_state state) 1248 { 1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1250 1251 if (amdgpu_sriov_vf(adev)) 1252 return 0; 1253 1254 switch (adev->asic_type) { 1255 case CHIP_NAVI10: 1256 case CHIP_NAVI14: 1257 case CHIP_NAVI12: 1258 case CHIP_SIENNA_CICHLID: 1259 case CHIP_NAVY_FLOUNDER: 1260 case CHIP_DIMGREY_CAVEFISH: 1261 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1262 state == AMD_CG_STATE_GATE); 1263 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1264 state == AMD_CG_STATE_GATE); 1265 adev->hdp.funcs->update_clock_gating(adev, 1266 state == AMD_CG_STATE_GATE); 1267 adev->smuio.funcs->update_rom_clock_gating(adev, 1268 state == AMD_CG_STATE_GATE); 1269 break; 1270 default: 1271 break; 1272 } 1273 return 0; 1274 } 1275 1276 static int nv_common_set_powergating_state(void *handle, 1277 enum amd_powergating_state state) 1278 { 1279 /* TODO */ 1280 return 0; 1281 } 1282 1283 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1284 { 1285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1286 1287 if (amdgpu_sriov_vf(adev)) 1288 *flags = 0; 1289 1290 adev->nbio.funcs->get_clockgating_state(adev, flags); 1291 1292 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1293 1294 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1295 1296 return; 1297 } 1298 1299 static const struct amd_ip_funcs nv_common_ip_funcs = { 1300 .name = "nv_common", 1301 .early_init = nv_common_early_init, 1302 .late_init = nv_common_late_init, 1303 .sw_init = nv_common_sw_init, 1304 .sw_fini = nv_common_sw_fini, 1305 .hw_init = nv_common_hw_init, 1306 .hw_fini = nv_common_hw_fini, 1307 .suspend = nv_common_suspend, 1308 .resume = nv_common_resume, 1309 .is_idle = nv_common_is_idle, 1310 .wait_for_idle = nv_common_wait_for_idle, 1311 .soft_reset = nv_common_soft_reset, 1312 .set_clockgating_state = nv_common_set_clockgating_state, 1313 .set_powergating_state = nv_common_set_powergating_state, 1314 .get_clockgating_state = nv_common_get_clockgating_state, 1315 }; 1316