1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 74 }; 75 76 static const struct amdgpu_video_codecs nv_video_codecs_encode = 77 { 78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 79 .codec_array = nv_video_codecs_encode_array, 80 }; 81 82 /* Navi1x */ 83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 92 }; 93 94 static const struct amdgpu_video_codecs nv_video_codecs_decode = 95 { 96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 97 .codec_array = nv_video_codecs_decode_array, 98 }; 99 100 /* Sienna Cichlid */ 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = 102 { 103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 104 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 111 }; 112 113 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = 114 { 115 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 116 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 117 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 118 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 119 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 122 }; 123 124 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = 125 { 126 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0), 127 .codec_array = sc_video_codecs_decode_array_vcn0, 128 }; 129 130 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = 131 { 132 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1), 133 .codec_array = sc_video_codecs_decode_array_vcn1, 134 }; 135 136 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 137 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 138 { 139 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 141 }; 142 143 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = 144 { 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 148 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 149 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 150 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 151 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 153 }; 154 155 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = 156 { 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 162 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 163 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 164 }; 165 166 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 167 { 168 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 169 .codec_array = sriov_sc_video_codecs_encode_array, 170 }; 171 172 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = 173 { 174 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0), 175 .codec_array = sriov_sc_video_codecs_decode_array_vcn0, 176 }; 177 178 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = 179 { 180 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1), 181 .codec_array = sriov_sc_video_codecs_decode_array_vcn1, 182 }; 183 184 /* Beige Goby*/ 185 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 186 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 187 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 188 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 189 }; 190 191 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 192 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 193 .codec_array = bg_video_codecs_decode_array, 194 }; 195 196 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 197 .codec_count = 0, 198 .codec_array = NULL, 199 }; 200 201 /* Yellow Carp*/ 202 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 203 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 204 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 205 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 206 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 207 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 208 }; 209 210 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 211 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 212 .codec_array = yc_video_codecs_decode_array, 213 }; 214 215 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 216 const struct amdgpu_video_codecs **codecs) 217 { 218 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 219 return -EINVAL; 220 221 switch (adev->ip_versions[UVD_HWIP][0]) { 222 case IP_VERSION(3, 0, 0): 223 case IP_VERSION(3, 0, 64): 224 case IP_VERSION(3, 0, 192): 225 if (amdgpu_sriov_vf(adev)) { 226 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 227 if (encode) 228 *codecs = &sriov_sc_video_codecs_encode; 229 else 230 *codecs = &sriov_sc_video_codecs_decode_vcn1; 231 } else { 232 if (encode) 233 *codecs = &sriov_sc_video_codecs_encode; 234 else 235 *codecs = &sriov_sc_video_codecs_decode_vcn0; 236 } 237 } else { 238 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 239 if (encode) 240 *codecs = &nv_video_codecs_encode; 241 else 242 *codecs = &sc_video_codecs_decode_vcn1; 243 } else { 244 if (encode) 245 *codecs = &nv_video_codecs_encode; 246 else 247 *codecs = &sc_video_codecs_decode_vcn0; 248 } 249 } 250 return 0; 251 case IP_VERSION(3, 0, 16): 252 case IP_VERSION(3, 0, 2): 253 if (encode) 254 *codecs = &nv_video_codecs_encode; 255 else 256 *codecs = &sc_video_codecs_decode_vcn0; 257 return 0; 258 case IP_VERSION(3, 1, 1): 259 case IP_VERSION(3, 1, 2): 260 if (encode) 261 *codecs = &nv_video_codecs_encode; 262 else 263 *codecs = &yc_video_codecs_decode; 264 return 0; 265 case IP_VERSION(3, 0, 33): 266 if (encode) 267 *codecs = &bg_video_codecs_encode; 268 else 269 *codecs = &bg_video_codecs_decode; 270 return 0; 271 case IP_VERSION(2, 0, 0): 272 case IP_VERSION(2, 0, 2): 273 if (encode) 274 *codecs = &nv_video_codecs_encode; 275 else 276 *codecs = &nv_video_codecs_decode; 277 return 0; 278 default: 279 return -EINVAL; 280 } 281 } 282 283 /* 284 * Indirect registers accessor 285 */ 286 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 287 { 288 unsigned long address, data; 289 address = adev->nbio.funcs->get_pcie_index_offset(adev); 290 data = adev->nbio.funcs->get_pcie_data_offset(adev); 291 292 return amdgpu_device_indirect_rreg(adev, address, data, reg); 293 } 294 295 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 296 { 297 unsigned long address, data; 298 299 address = adev->nbio.funcs->get_pcie_index_offset(adev); 300 data = adev->nbio.funcs->get_pcie_data_offset(adev); 301 302 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 303 } 304 305 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 306 { 307 unsigned long address, data; 308 address = adev->nbio.funcs->get_pcie_index_offset(adev); 309 data = adev->nbio.funcs->get_pcie_data_offset(adev); 310 311 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 312 } 313 314 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 315 { 316 unsigned long address, data; 317 318 address = adev->nbio.funcs->get_pcie_index_offset(adev); 319 data = adev->nbio.funcs->get_pcie_data_offset(adev); 320 321 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 322 } 323 324 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 325 { 326 unsigned long flags, address, data; 327 u32 r; 328 329 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 330 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 331 332 spin_lock_irqsave(&adev->didt_idx_lock, flags); 333 WREG32(address, (reg)); 334 r = RREG32(data); 335 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 336 return r; 337 } 338 339 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 340 { 341 unsigned long flags, address, data; 342 343 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 344 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 345 346 spin_lock_irqsave(&adev->didt_idx_lock, flags); 347 WREG32(address, (reg)); 348 WREG32(data, (v)); 349 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 350 } 351 352 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 353 { 354 return adev->nbio.funcs->get_memsize(adev); 355 } 356 357 static u32 nv_get_xclk(struct amdgpu_device *adev) 358 { 359 return adev->clock.spll.reference_freq; 360 } 361 362 363 void nv_grbm_select(struct amdgpu_device *adev, 364 u32 me, u32 pipe, u32 queue, u32 vmid) 365 { 366 u32 grbm_gfx_cntl = 0; 367 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 368 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 369 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 370 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 371 372 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 373 } 374 375 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 376 { 377 /* todo */ 378 } 379 380 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 381 { 382 /* todo */ 383 return false; 384 } 385 386 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 387 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 388 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 389 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 390 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 391 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 392 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 393 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 394 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 395 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 396 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 397 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 398 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 399 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 400 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 401 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 402 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 403 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 404 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 405 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 406 }; 407 408 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 409 u32 sh_num, u32 reg_offset) 410 { 411 uint32_t val; 412 413 mutex_lock(&adev->grbm_idx_mutex); 414 if (se_num != 0xffffffff || sh_num != 0xffffffff) 415 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 416 417 val = RREG32(reg_offset); 418 419 if (se_num != 0xffffffff || sh_num != 0xffffffff) 420 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 421 mutex_unlock(&adev->grbm_idx_mutex); 422 return val; 423 } 424 425 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 426 bool indexed, u32 se_num, 427 u32 sh_num, u32 reg_offset) 428 { 429 if (indexed) { 430 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 431 } else { 432 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 433 return adev->gfx.config.gb_addr_config; 434 return RREG32(reg_offset); 435 } 436 } 437 438 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 439 u32 sh_num, u32 reg_offset, u32 *value) 440 { 441 uint32_t i; 442 struct soc15_allowed_register_entry *en; 443 444 *value = 0; 445 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 446 en = &nv_allowed_read_registers[i]; 447 if (!adev->reg_offset[en->hwip][en->inst]) 448 continue; 449 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 450 + en->reg_offset)) 451 continue; 452 453 *value = nv_get_register_value(adev, 454 nv_allowed_read_registers[i].grbm_indexed, 455 se_num, sh_num, reg_offset); 456 return 0; 457 } 458 return -EINVAL; 459 } 460 461 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 462 { 463 u32 i; 464 int ret = 0; 465 466 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 467 468 /* disable BM */ 469 pci_clear_master(adev->pdev); 470 471 amdgpu_device_cache_pci_state(adev->pdev); 472 473 ret = amdgpu_dpm_mode2_reset(adev); 474 if (ret) 475 dev_err(adev->dev, "GPU mode2 reset failed\n"); 476 477 amdgpu_device_load_pci_state(adev->pdev); 478 479 /* wait for asic to come out of reset */ 480 for (i = 0; i < adev->usec_timeout; i++) { 481 u32 memsize = adev->nbio.funcs->get_memsize(adev); 482 483 if (memsize != 0xffffffff) 484 break; 485 udelay(1); 486 } 487 488 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 489 490 return ret; 491 } 492 493 static enum amd_reset_method 494 nv_asic_reset_method(struct amdgpu_device *adev) 495 { 496 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 497 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 498 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 499 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 500 return amdgpu_reset_method; 501 502 if (amdgpu_reset_method != -1) 503 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 504 amdgpu_reset_method); 505 506 switch (adev->ip_versions[MP1_HWIP][0]) { 507 case IP_VERSION(11, 5, 0): 508 case IP_VERSION(13, 0, 1): 509 case IP_VERSION(13, 0, 3): 510 case IP_VERSION(13, 0, 5): 511 case IP_VERSION(13, 0, 8): 512 return AMD_RESET_METHOD_MODE2; 513 case IP_VERSION(11, 0, 7): 514 case IP_VERSION(11, 0, 11): 515 case IP_VERSION(11, 0, 12): 516 case IP_VERSION(11, 0, 13): 517 return AMD_RESET_METHOD_MODE1; 518 default: 519 if (amdgpu_dpm_is_baco_supported(adev)) 520 return AMD_RESET_METHOD_BACO; 521 else 522 return AMD_RESET_METHOD_MODE1; 523 } 524 } 525 526 static int nv_asic_reset(struct amdgpu_device *adev) 527 { 528 int ret = 0; 529 530 switch (nv_asic_reset_method(adev)) { 531 case AMD_RESET_METHOD_PCI: 532 dev_info(adev->dev, "PCI reset\n"); 533 ret = amdgpu_device_pci_reset(adev); 534 break; 535 case AMD_RESET_METHOD_BACO: 536 dev_info(adev->dev, "BACO reset\n"); 537 ret = amdgpu_dpm_baco_reset(adev); 538 break; 539 case AMD_RESET_METHOD_MODE2: 540 dev_info(adev->dev, "MODE2 reset\n"); 541 ret = nv_asic_mode2_reset(adev); 542 break; 543 default: 544 dev_info(adev->dev, "MODE1 reset\n"); 545 ret = amdgpu_device_mode1_reset(adev); 546 break; 547 } 548 549 return ret; 550 } 551 552 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 553 { 554 /* todo */ 555 return 0; 556 } 557 558 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 559 { 560 /* todo */ 561 return 0; 562 } 563 564 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 565 { 566 if (pci_is_root_bus(adev->pdev->bus)) 567 return; 568 569 if (amdgpu_pcie_gen2 == 0) 570 return; 571 572 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 573 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 574 return; 575 576 /* todo */ 577 } 578 579 static void nv_program_aspm(struct amdgpu_device *adev) 580 { 581 if (!amdgpu_device_should_use_aspm(adev)) 582 return; 583 584 if (!(adev->flags & AMD_IS_APU) && 585 (adev->nbio.funcs->program_aspm)) 586 adev->nbio.funcs->program_aspm(adev); 587 588 } 589 590 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 591 bool enable) 592 { 593 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 594 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 595 } 596 597 const struct amdgpu_ip_block_version nv_common_ip_block = 598 { 599 .type = AMD_IP_BLOCK_TYPE_COMMON, 600 .major = 1, 601 .minor = 0, 602 .rev = 0, 603 .funcs = &nv_common_ip_funcs, 604 }; 605 606 void nv_set_virt_ops(struct amdgpu_device *adev) 607 { 608 adev->virt.ops = &xgpu_nv_virt_ops; 609 } 610 611 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 612 { 613 return adev->nbio.funcs->get_rev_id(adev); 614 } 615 616 static bool nv_need_full_reset(struct amdgpu_device *adev) 617 { 618 return true; 619 } 620 621 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 622 { 623 u32 sol_reg; 624 625 if (adev->flags & AMD_IS_APU) 626 return false; 627 628 /* Check sOS sign of life register to confirm sys driver and sOS 629 * are already been loaded. 630 */ 631 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 632 if (sol_reg) 633 return true; 634 635 return false; 636 } 637 638 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 639 { 640 641 /* TODO 642 * dummy implement for pcie_replay_count sysfs interface 643 * */ 644 645 return 0; 646 } 647 648 static void nv_init_doorbell_index(struct amdgpu_device *adev) 649 { 650 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 651 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 652 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 653 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 654 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 655 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 656 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 657 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 658 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 659 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 660 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 661 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 662 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 663 adev->doorbell_index.gfx_userqueue_start = 664 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 665 adev->doorbell_index.gfx_userqueue_end = 666 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 667 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 668 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 669 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 670 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 671 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 672 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 673 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 674 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 675 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 676 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 677 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 678 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 679 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 680 681 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 682 adev->doorbell_index.sdma_doorbell_range = 20; 683 } 684 685 static void nv_pre_asic_init(struct amdgpu_device *adev) 686 { 687 } 688 689 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 690 bool enter) 691 { 692 if (enter) 693 amdgpu_gfx_rlc_enter_safe_mode(adev); 694 else 695 amdgpu_gfx_rlc_exit_safe_mode(adev); 696 697 if (adev->gfx.funcs->update_perfmon_mgcg) 698 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 699 700 if (!(adev->flags & AMD_IS_APU) && 701 (adev->nbio.funcs->enable_aspm) && 702 amdgpu_device_should_use_aspm(adev)) 703 adev->nbio.funcs->enable_aspm(adev, !enter); 704 705 return 0; 706 } 707 708 static const struct amdgpu_asic_funcs nv_asic_funcs = 709 { 710 .read_disabled_bios = &nv_read_disabled_bios, 711 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 712 .read_register = &nv_read_register, 713 .reset = &nv_asic_reset, 714 .reset_method = &nv_asic_reset_method, 715 .set_vga_state = &nv_vga_set_state, 716 .get_xclk = &nv_get_xclk, 717 .set_uvd_clocks = &nv_set_uvd_clocks, 718 .set_vce_clocks = &nv_set_vce_clocks, 719 .get_config_memsize = &nv_get_config_memsize, 720 .init_doorbell_index = &nv_init_doorbell_index, 721 .need_full_reset = &nv_need_full_reset, 722 .need_reset_on_init = &nv_need_reset_on_init, 723 .get_pcie_replay_count = &nv_get_pcie_replay_count, 724 .supports_baco = &amdgpu_dpm_is_baco_supported, 725 .pre_asic_init = &nv_pre_asic_init, 726 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 727 .query_video_codecs = &nv_query_video_codecs, 728 }; 729 730 static int nv_common_early_init(void *handle) 731 { 732 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 733 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 734 735 if (!amdgpu_sriov_vf(adev)) { 736 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 737 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 738 } 739 adev->smc_rreg = NULL; 740 adev->smc_wreg = NULL; 741 adev->pcie_rreg = &nv_pcie_rreg; 742 adev->pcie_wreg = &nv_pcie_wreg; 743 adev->pcie_rreg64 = &nv_pcie_rreg64; 744 adev->pcie_wreg64 = &nv_pcie_wreg64; 745 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 746 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 747 748 /* TODO: will add them during VCN v2 implementation */ 749 adev->uvd_ctx_rreg = NULL; 750 adev->uvd_ctx_wreg = NULL; 751 752 adev->didt_rreg = &nv_didt_rreg; 753 adev->didt_wreg = &nv_didt_wreg; 754 755 adev->asic_funcs = &nv_asic_funcs; 756 757 adev->rev_id = nv_get_rev_id(adev); 758 adev->external_rev_id = 0xff; 759 /* TODO: split the GC and PG flags based on the relevant IP version for which 760 * they are relevant. 761 */ 762 switch (adev->ip_versions[GC_HWIP][0]) { 763 case IP_VERSION(10, 1, 10): 764 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 765 AMD_CG_SUPPORT_GFX_CGCG | 766 AMD_CG_SUPPORT_IH_CG | 767 AMD_CG_SUPPORT_HDP_MGCG | 768 AMD_CG_SUPPORT_HDP_LS | 769 AMD_CG_SUPPORT_SDMA_MGCG | 770 AMD_CG_SUPPORT_SDMA_LS | 771 AMD_CG_SUPPORT_MC_MGCG | 772 AMD_CG_SUPPORT_MC_LS | 773 AMD_CG_SUPPORT_ATHUB_MGCG | 774 AMD_CG_SUPPORT_ATHUB_LS | 775 AMD_CG_SUPPORT_VCN_MGCG | 776 AMD_CG_SUPPORT_JPEG_MGCG | 777 AMD_CG_SUPPORT_BIF_MGCG | 778 AMD_CG_SUPPORT_BIF_LS; 779 adev->pg_flags = AMD_PG_SUPPORT_VCN | 780 AMD_PG_SUPPORT_VCN_DPG | 781 AMD_PG_SUPPORT_JPEG | 782 AMD_PG_SUPPORT_ATHUB; 783 adev->external_rev_id = adev->rev_id + 0x1; 784 break; 785 case IP_VERSION(10, 1, 1): 786 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 787 AMD_CG_SUPPORT_GFX_CGCG | 788 AMD_CG_SUPPORT_IH_CG | 789 AMD_CG_SUPPORT_HDP_MGCG | 790 AMD_CG_SUPPORT_HDP_LS | 791 AMD_CG_SUPPORT_SDMA_MGCG | 792 AMD_CG_SUPPORT_SDMA_LS | 793 AMD_CG_SUPPORT_MC_MGCG | 794 AMD_CG_SUPPORT_MC_LS | 795 AMD_CG_SUPPORT_ATHUB_MGCG | 796 AMD_CG_SUPPORT_ATHUB_LS | 797 AMD_CG_SUPPORT_VCN_MGCG | 798 AMD_CG_SUPPORT_JPEG_MGCG | 799 AMD_CG_SUPPORT_BIF_MGCG | 800 AMD_CG_SUPPORT_BIF_LS; 801 adev->pg_flags = AMD_PG_SUPPORT_VCN | 802 AMD_PG_SUPPORT_JPEG | 803 AMD_PG_SUPPORT_VCN_DPG; 804 adev->external_rev_id = adev->rev_id + 20; 805 break; 806 case IP_VERSION(10, 1, 2): 807 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 808 AMD_CG_SUPPORT_GFX_MGLS | 809 AMD_CG_SUPPORT_GFX_CGCG | 810 AMD_CG_SUPPORT_GFX_CP_LS | 811 AMD_CG_SUPPORT_GFX_RLC_LS | 812 AMD_CG_SUPPORT_IH_CG | 813 AMD_CG_SUPPORT_HDP_MGCG | 814 AMD_CG_SUPPORT_HDP_LS | 815 AMD_CG_SUPPORT_SDMA_MGCG | 816 AMD_CG_SUPPORT_SDMA_LS | 817 AMD_CG_SUPPORT_MC_MGCG | 818 AMD_CG_SUPPORT_MC_LS | 819 AMD_CG_SUPPORT_ATHUB_MGCG | 820 AMD_CG_SUPPORT_ATHUB_LS | 821 AMD_CG_SUPPORT_VCN_MGCG | 822 AMD_CG_SUPPORT_JPEG_MGCG; 823 adev->pg_flags = AMD_PG_SUPPORT_VCN | 824 AMD_PG_SUPPORT_VCN_DPG | 825 AMD_PG_SUPPORT_JPEG | 826 AMD_PG_SUPPORT_ATHUB; 827 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 828 * as a consequence, the rev_id and external_rev_id are wrong. 829 * workaround it by hardcoding rev_id to 0 (default value). 830 */ 831 if (amdgpu_sriov_vf(adev)) 832 adev->rev_id = 0; 833 adev->external_rev_id = adev->rev_id + 0xa; 834 break; 835 case IP_VERSION(10, 3, 0): 836 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 837 AMD_CG_SUPPORT_GFX_CGCG | 838 AMD_CG_SUPPORT_GFX_CGLS | 839 AMD_CG_SUPPORT_GFX_3D_CGCG | 840 AMD_CG_SUPPORT_MC_MGCG | 841 AMD_CG_SUPPORT_VCN_MGCG | 842 AMD_CG_SUPPORT_JPEG_MGCG | 843 AMD_CG_SUPPORT_HDP_MGCG | 844 AMD_CG_SUPPORT_HDP_LS | 845 AMD_CG_SUPPORT_IH_CG | 846 AMD_CG_SUPPORT_MC_LS; 847 adev->pg_flags = AMD_PG_SUPPORT_VCN | 848 AMD_PG_SUPPORT_VCN_DPG | 849 AMD_PG_SUPPORT_JPEG | 850 AMD_PG_SUPPORT_ATHUB | 851 AMD_PG_SUPPORT_MMHUB; 852 if (amdgpu_sriov_vf(adev)) { 853 /* hypervisor control CG and PG enablement */ 854 adev->cg_flags = 0; 855 adev->pg_flags = 0; 856 } 857 adev->external_rev_id = adev->rev_id + 0x28; 858 break; 859 case IP_VERSION(10, 3, 2): 860 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 861 AMD_CG_SUPPORT_GFX_CGCG | 862 AMD_CG_SUPPORT_GFX_CGLS | 863 AMD_CG_SUPPORT_GFX_3D_CGCG | 864 AMD_CG_SUPPORT_VCN_MGCG | 865 AMD_CG_SUPPORT_JPEG_MGCG | 866 AMD_CG_SUPPORT_MC_MGCG | 867 AMD_CG_SUPPORT_MC_LS | 868 AMD_CG_SUPPORT_HDP_MGCG | 869 AMD_CG_SUPPORT_HDP_LS | 870 AMD_CG_SUPPORT_IH_CG; 871 adev->pg_flags = AMD_PG_SUPPORT_VCN | 872 AMD_PG_SUPPORT_VCN_DPG | 873 AMD_PG_SUPPORT_JPEG | 874 AMD_PG_SUPPORT_ATHUB | 875 AMD_PG_SUPPORT_MMHUB; 876 adev->external_rev_id = adev->rev_id + 0x32; 877 break; 878 case IP_VERSION(10, 3, 1): 879 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 880 AMD_CG_SUPPORT_GFX_MGLS | 881 AMD_CG_SUPPORT_GFX_CP_LS | 882 AMD_CG_SUPPORT_GFX_RLC_LS | 883 AMD_CG_SUPPORT_GFX_CGCG | 884 AMD_CG_SUPPORT_GFX_CGLS | 885 AMD_CG_SUPPORT_GFX_3D_CGCG | 886 AMD_CG_SUPPORT_GFX_3D_CGLS | 887 AMD_CG_SUPPORT_MC_MGCG | 888 AMD_CG_SUPPORT_MC_LS | 889 AMD_CG_SUPPORT_GFX_FGCG | 890 AMD_CG_SUPPORT_VCN_MGCG | 891 AMD_CG_SUPPORT_SDMA_MGCG | 892 AMD_CG_SUPPORT_SDMA_LS | 893 AMD_CG_SUPPORT_JPEG_MGCG; 894 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 895 AMD_PG_SUPPORT_VCN | 896 AMD_PG_SUPPORT_VCN_DPG | 897 AMD_PG_SUPPORT_JPEG; 898 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 899 adev->external_rev_id = adev->rev_id + 0x01; 900 break; 901 case IP_VERSION(10, 3, 4): 902 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 903 AMD_CG_SUPPORT_GFX_CGCG | 904 AMD_CG_SUPPORT_GFX_CGLS | 905 AMD_CG_SUPPORT_GFX_3D_CGCG | 906 AMD_CG_SUPPORT_VCN_MGCG | 907 AMD_CG_SUPPORT_JPEG_MGCG | 908 AMD_CG_SUPPORT_MC_MGCG | 909 AMD_CG_SUPPORT_MC_LS | 910 AMD_CG_SUPPORT_HDP_MGCG | 911 AMD_CG_SUPPORT_HDP_LS | 912 AMD_CG_SUPPORT_IH_CG; 913 adev->pg_flags = AMD_PG_SUPPORT_VCN | 914 AMD_PG_SUPPORT_VCN_DPG | 915 AMD_PG_SUPPORT_JPEG | 916 AMD_PG_SUPPORT_ATHUB | 917 AMD_PG_SUPPORT_MMHUB; 918 adev->external_rev_id = adev->rev_id + 0x3c; 919 break; 920 case IP_VERSION(10, 3, 5): 921 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 922 AMD_CG_SUPPORT_GFX_CGCG | 923 AMD_CG_SUPPORT_GFX_CGLS | 924 AMD_CG_SUPPORT_GFX_3D_CGCG | 925 AMD_CG_SUPPORT_MC_MGCG | 926 AMD_CG_SUPPORT_MC_LS | 927 AMD_CG_SUPPORT_HDP_MGCG | 928 AMD_CG_SUPPORT_HDP_LS | 929 AMD_CG_SUPPORT_IH_CG | 930 AMD_CG_SUPPORT_VCN_MGCG; 931 adev->pg_flags = AMD_PG_SUPPORT_VCN | 932 AMD_PG_SUPPORT_VCN_DPG | 933 AMD_PG_SUPPORT_ATHUB | 934 AMD_PG_SUPPORT_MMHUB; 935 adev->external_rev_id = adev->rev_id + 0x46; 936 break; 937 case IP_VERSION(10, 3, 3): 938 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 939 AMD_CG_SUPPORT_GFX_MGLS | 940 AMD_CG_SUPPORT_GFX_CGCG | 941 AMD_CG_SUPPORT_GFX_CGLS | 942 AMD_CG_SUPPORT_GFX_3D_CGCG | 943 AMD_CG_SUPPORT_GFX_3D_CGLS | 944 AMD_CG_SUPPORT_GFX_RLC_LS | 945 AMD_CG_SUPPORT_GFX_CP_LS | 946 AMD_CG_SUPPORT_GFX_FGCG | 947 AMD_CG_SUPPORT_MC_MGCG | 948 AMD_CG_SUPPORT_MC_LS | 949 AMD_CG_SUPPORT_SDMA_LS | 950 AMD_CG_SUPPORT_HDP_MGCG | 951 AMD_CG_SUPPORT_HDP_LS | 952 AMD_CG_SUPPORT_ATHUB_MGCG | 953 AMD_CG_SUPPORT_ATHUB_LS | 954 AMD_CG_SUPPORT_IH_CG | 955 AMD_CG_SUPPORT_VCN_MGCG | 956 AMD_CG_SUPPORT_JPEG_MGCG; 957 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 958 AMD_PG_SUPPORT_VCN | 959 AMD_PG_SUPPORT_VCN_DPG | 960 AMD_PG_SUPPORT_JPEG; 961 if (adev->pdev->device == 0x1681) 962 adev->external_rev_id = 0x20; 963 else 964 adev->external_rev_id = adev->rev_id + 0x01; 965 break; 966 case IP_VERSION(10, 1, 3): 967 case IP_VERSION(10, 1, 4): 968 adev->cg_flags = 0; 969 adev->pg_flags = 0; 970 adev->external_rev_id = adev->rev_id + 0x82; 971 break; 972 case IP_VERSION(10, 3, 6): 973 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 974 AMD_CG_SUPPORT_GFX_MGLS | 975 AMD_CG_SUPPORT_GFX_CGCG | 976 AMD_CG_SUPPORT_GFX_CGLS | 977 AMD_CG_SUPPORT_GFX_3D_CGCG | 978 AMD_CG_SUPPORT_GFX_3D_CGLS | 979 AMD_CG_SUPPORT_GFX_RLC_LS | 980 AMD_CG_SUPPORT_GFX_CP_LS | 981 AMD_CG_SUPPORT_GFX_FGCG | 982 AMD_CG_SUPPORT_MC_MGCG | 983 AMD_CG_SUPPORT_MC_LS | 984 AMD_CG_SUPPORT_SDMA_LS | 985 AMD_CG_SUPPORT_HDP_MGCG | 986 AMD_CG_SUPPORT_HDP_LS | 987 AMD_CG_SUPPORT_ATHUB_MGCG | 988 AMD_CG_SUPPORT_ATHUB_LS | 989 AMD_CG_SUPPORT_IH_CG | 990 AMD_CG_SUPPORT_VCN_MGCG | 991 AMD_CG_SUPPORT_JPEG_MGCG; 992 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 993 AMD_PG_SUPPORT_VCN | 994 AMD_PG_SUPPORT_VCN_DPG | 995 AMD_PG_SUPPORT_JPEG; 996 adev->external_rev_id = adev->rev_id + 0x01; 997 break; 998 case IP_VERSION(10, 3, 7): 999 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1000 AMD_CG_SUPPORT_GFX_MGLS | 1001 AMD_CG_SUPPORT_GFX_CGCG | 1002 AMD_CG_SUPPORT_GFX_CGLS | 1003 AMD_CG_SUPPORT_GFX_3D_CGCG | 1004 AMD_CG_SUPPORT_GFX_3D_CGLS | 1005 AMD_CG_SUPPORT_GFX_RLC_LS | 1006 AMD_CG_SUPPORT_GFX_CP_LS | 1007 AMD_CG_SUPPORT_GFX_FGCG | 1008 AMD_CG_SUPPORT_MC_MGCG | 1009 AMD_CG_SUPPORT_MC_LS | 1010 AMD_CG_SUPPORT_SDMA_LS | 1011 AMD_CG_SUPPORT_HDP_MGCG | 1012 AMD_CG_SUPPORT_HDP_LS | 1013 AMD_CG_SUPPORT_ATHUB_MGCG | 1014 AMD_CG_SUPPORT_ATHUB_LS | 1015 AMD_CG_SUPPORT_IH_CG | 1016 AMD_CG_SUPPORT_VCN_MGCG | 1017 AMD_CG_SUPPORT_JPEG_MGCG; 1018 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1019 AMD_PG_SUPPORT_VCN_DPG | 1020 AMD_PG_SUPPORT_JPEG | 1021 AMD_PG_SUPPORT_GFX_PG; 1022 adev->external_rev_id = adev->rev_id + 0x01; 1023 break; 1024 default: 1025 /* FIXME: not supported yet */ 1026 return -EINVAL; 1027 } 1028 1029 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 1030 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 1031 AMD_PG_SUPPORT_VCN_DPG | 1032 AMD_PG_SUPPORT_JPEG); 1033 1034 if (amdgpu_sriov_vf(adev)) { 1035 amdgpu_virt_init_setting(adev); 1036 xgpu_nv_mailbox_set_irq_funcs(adev); 1037 } 1038 1039 return 0; 1040 } 1041 1042 static int nv_common_late_init(void *handle) 1043 { 1044 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1045 1046 if (amdgpu_sriov_vf(adev)) { 1047 xgpu_nv_mailbox_get_irq(adev); 1048 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 1049 amdgpu_virt_update_sriov_video_codec(adev, 1050 sriov_sc_video_codecs_encode_array, 1051 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 1052 sriov_sc_video_codecs_decode_array_vcn1, 1053 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1)); 1054 } else { 1055 amdgpu_virt_update_sriov_video_codec(adev, 1056 sriov_sc_video_codecs_encode_array, 1057 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 1058 sriov_sc_video_codecs_decode_array_vcn1, 1059 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1)); 1060 } 1061 } 1062 1063 return 0; 1064 } 1065 1066 static int nv_common_sw_init(void *handle) 1067 { 1068 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1069 1070 if (amdgpu_sriov_vf(adev)) 1071 xgpu_nv_mailbox_add_irq_id(adev); 1072 1073 return 0; 1074 } 1075 1076 static int nv_common_sw_fini(void *handle) 1077 { 1078 return 0; 1079 } 1080 1081 static int nv_common_hw_init(void *handle) 1082 { 1083 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1084 1085 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 1086 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 1087 1088 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1089 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1090 1091 /* enable pcie gen2/3 link */ 1092 nv_pcie_gen3_enable(adev); 1093 /* enable aspm */ 1094 nv_program_aspm(adev); 1095 /* setup nbio registers */ 1096 adev->nbio.funcs->init_registers(adev); 1097 /* remap HDP registers to a hole in mmio space, 1098 * for the purpose of expose those registers 1099 * to process space 1100 */ 1101 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1102 adev->nbio.funcs->remap_hdp_registers(adev); 1103 /* enable the doorbell aperture */ 1104 nv_enable_doorbell_aperture(adev, true); 1105 1106 return 0; 1107 } 1108 1109 static int nv_common_hw_fini(void *handle) 1110 { 1111 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1112 1113 /* disable the doorbell aperture */ 1114 nv_enable_doorbell_aperture(adev, false); 1115 1116 return 0; 1117 } 1118 1119 static int nv_common_suspend(void *handle) 1120 { 1121 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1122 1123 return nv_common_hw_fini(adev); 1124 } 1125 1126 static int nv_common_resume(void *handle) 1127 { 1128 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1129 1130 return nv_common_hw_init(adev); 1131 } 1132 1133 static bool nv_common_is_idle(void *handle) 1134 { 1135 return true; 1136 } 1137 1138 static int nv_common_wait_for_idle(void *handle) 1139 { 1140 return 0; 1141 } 1142 1143 static int nv_common_soft_reset(void *handle) 1144 { 1145 return 0; 1146 } 1147 1148 static int nv_common_set_clockgating_state(void *handle, 1149 enum amd_clockgating_state state) 1150 { 1151 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1152 1153 if (amdgpu_sriov_vf(adev)) 1154 return 0; 1155 1156 switch (adev->ip_versions[NBIO_HWIP][0]) { 1157 case IP_VERSION(2, 3, 0): 1158 case IP_VERSION(2, 3, 1): 1159 case IP_VERSION(2, 3, 2): 1160 case IP_VERSION(3, 3, 0): 1161 case IP_VERSION(3, 3, 1): 1162 case IP_VERSION(3, 3, 2): 1163 case IP_VERSION(3, 3, 3): 1164 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1165 state == AMD_CG_STATE_GATE); 1166 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1167 state == AMD_CG_STATE_GATE); 1168 adev->hdp.funcs->update_clock_gating(adev, 1169 state == AMD_CG_STATE_GATE); 1170 adev->smuio.funcs->update_rom_clock_gating(adev, 1171 state == AMD_CG_STATE_GATE); 1172 break; 1173 default: 1174 break; 1175 } 1176 return 0; 1177 } 1178 1179 static int nv_common_set_powergating_state(void *handle, 1180 enum amd_powergating_state state) 1181 { 1182 /* TODO */ 1183 return 0; 1184 } 1185 1186 static void nv_common_get_clockgating_state(void *handle, u64 *flags) 1187 { 1188 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1189 1190 if (amdgpu_sriov_vf(adev)) 1191 *flags = 0; 1192 1193 adev->nbio.funcs->get_clockgating_state(adev, flags); 1194 1195 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1196 1197 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1198 1199 return; 1200 } 1201 1202 static const struct amd_ip_funcs nv_common_ip_funcs = { 1203 .name = "nv_common", 1204 .early_init = nv_common_early_init, 1205 .late_init = nv_common_late_init, 1206 .sw_init = nv_common_sw_init, 1207 .sw_fini = nv_common_sw_fini, 1208 .hw_init = nv_common_hw_init, 1209 .hw_fini = nv_common_hw_fini, 1210 .suspend = nv_common_suspend, 1211 .resume = nv_common_resume, 1212 .is_idle = nv_common_is_idle, 1213 .wait_for_idle = nv_common_wait_for_idle, 1214 .soft_reset = nv_common_soft_reset, 1215 .set_clockgating_state = nv_common_set_clockgating_state, 1216 .set_powergating_state = nv_common_set_powergating_state, 1217 .get_clockgating_state = nv_common_get_clockgating_state, 1218 }; 1219