1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "hdp/hdp_5_0_0_sh_mask.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nv.h" 50 #include "navi10_ih.h" 51 #include "gfx_v10_0.h" 52 #include "sdma_v5_0.h" 53 #include "vcn_v2_0.h" 54 #include "dce_virtual.h" 55 #include "mes_v10_1.h" 56 57 static const struct amd_ip_funcs nv_common_ip_funcs; 58 59 /* 60 * Indirect registers accessor 61 */ 62 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 63 { 64 unsigned long flags, address, data; 65 u32 r; 66 address = adev->nbio_funcs->get_pcie_index_offset(adev); 67 data = adev->nbio_funcs->get_pcie_data_offset(adev); 68 69 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 70 WREG32(address, reg); 71 (void)RREG32(address); 72 r = RREG32(data); 73 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 74 return r; 75 } 76 77 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 78 { 79 unsigned long flags, address, data; 80 81 address = adev->nbio_funcs->get_pcie_index_offset(adev); 82 data = adev->nbio_funcs->get_pcie_data_offset(adev); 83 84 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 85 WREG32(address, reg); 86 (void)RREG32(address); 87 WREG32(data, v); 88 (void)RREG32(data); 89 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 90 } 91 92 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 93 { 94 unsigned long flags, address, data; 95 u32 r; 96 97 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 98 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 99 100 spin_lock_irqsave(&adev->didt_idx_lock, flags); 101 WREG32(address, (reg)); 102 r = RREG32(data); 103 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 104 return r; 105 } 106 107 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 108 { 109 unsigned long flags, address, data; 110 111 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 112 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 113 114 spin_lock_irqsave(&adev->didt_idx_lock, flags); 115 WREG32(address, (reg)); 116 WREG32(data, (v)); 117 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 118 } 119 120 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 121 { 122 return adev->nbio_funcs->get_memsize(adev); 123 } 124 125 static u32 nv_get_xclk(struct amdgpu_device *adev) 126 { 127 return adev->clock.spll.reference_freq; 128 } 129 130 131 void nv_grbm_select(struct amdgpu_device *adev, 132 u32 me, u32 pipe, u32 queue, u32 vmid) 133 { 134 u32 grbm_gfx_cntl = 0; 135 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 136 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 137 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 138 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 139 140 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 141 } 142 143 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 144 { 145 /* todo */ 146 } 147 148 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 149 { 150 /* todo */ 151 return false; 152 } 153 154 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 155 u8 *bios, u32 length_bytes) 156 { 157 /* TODO: will implement it when SMU header is available */ 158 return false; 159 } 160 161 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 162 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 163 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 164 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 165 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 166 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 167 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 168 #if 0 /* TODO: will set it when SDMA header is available */ 169 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 170 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 171 #endif 172 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 173 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 174 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 175 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 176 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 177 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 178 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 179 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 180 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 181 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 182 }; 183 184 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 185 u32 sh_num, u32 reg_offset) 186 { 187 uint32_t val; 188 189 mutex_lock(&adev->grbm_idx_mutex); 190 if (se_num != 0xffffffff || sh_num != 0xffffffff) 191 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 192 193 val = RREG32(reg_offset); 194 195 if (se_num != 0xffffffff || sh_num != 0xffffffff) 196 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 197 mutex_unlock(&adev->grbm_idx_mutex); 198 return val; 199 } 200 201 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 202 bool indexed, u32 se_num, 203 u32 sh_num, u32 reg_offset) 204 { 205 if (indexed) { 206 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 207 } else { 208 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 209 return adev->gfx.config.gb_addr_config; 210 return RREG32(reg_offset); 211 } 212 } 213 214 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 215 u32 sh_num, u32 reg_offset, u32 *value) 216 { 217 uint32_t i; 218 struct soc15_allowed_register_entry *en; 219 220 *value = 0; 221 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 222 en = &nv_allowed_read_registers[i]; 223 if (reg_offset != 224 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 225 continue; 226 227 *value = nv_get_register_value(adev, 228 nv_allowed_read_registers[i].grbm_indexed, 229 se_num, sh_num, reg_offset); 230 return 0; 231 } 232 return -EINVAL; 233 } 234 235 #if 0 236 static void nv_gpu_pci_config_reset(struct amdgpu_device *adev) 237 { 238 u32 i; 239 240 dev_info(adev->dev, "GPU pci config reset\n"); 241 242 /* disable BM */ 243 pci_clear_master(adev->pdev); 244 /* reset */ 245 amdgpu_pci_config_reset(adev); 246 247 udelay(100); 248 249 /* wait for asic to come out of reset */ 250 for (i = 0; i < adev->usec_timeout; i++) { 251 u32 memsize = nbio_v2_3_get_memsize(adev); 252 if (memsize != 0xffffffff) 253 break; 254 udelay(1); 255 } 256 257 } 258 #endif 259 260 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 261 { 262 u32 i; 263 int ret = 0; 264 265 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 266 267 dev_info(adev->dev, "GPU mode1 reset\n"); 268 269 /* disable BM */ 270 pci_clear_master(adev->pdev); 271 272 pci_save_state(adev->pdev); 273 274 ret = psp_gpu_reset(adev); 275 if (ret) 276 dev_err(adev->dev, "GPU mode1 reset failed\n"); 277 278 pci_restore_state(adev->pdev); 279 280 /* wait for asic to come out of reset */ 281 for (i = 0; i < adev->usec_timeout; i++) { 282 u32 memsize = adev->nbio_funcs->get_memsize(adev); 283 284 if (memsize != 0xffffffff) 285 break; 286 udelay(1); 287 } 288 289 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 290 291 return ret; 292 } 293 294 static enum amd_reset_method 295 nv_asic_reset_method(struct amdgpu_device *adev) 296 { 297 struct smu_context *smu = &adev->smu; 298 299 if (smu_baco_is_support(smu)) 300 return AMD_RESET_METHOD_BACO; 301 else 302 return AMD_RESET_METHOD_MODE1; 303 } 304 305 static int nv_asic_reset(struct amdgpu_device *adev) 306 { 307 308 /* FIXME: it doesn't work since vega10 */ 309 #if 0 310 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 311 312 nv_gpu_pci_config_reset(adev); 313 314 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 315 #endif 316 int ret = 0; 317 struct smu_context *smu = &adev->smu; 318 319 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) 320 ret = smu_baco_reset(smu); 321 else 322 ret = nv_asic_mode1_reset(adev); 323 324 return ret; 325 } 326 327 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 328 { 329 /* todo */ 330 return 0; 331 } 332 333 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 334 { 335 /* todo */ 336 return 0; 337 } 338 339 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 340 { 341 if (pci_is_root_bus(adev->pdev->bus)) 342 return; 343 344 if (amdgpu_pcie_gen2 == 0) 345 return; 346 347 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 348 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 349 return; 350 351 /* todo */ 352 } 353 354 static void nv_program_aspm(struct amdgpu_device *adev) 355 { 356 357 if (amdgpu_aspm == 0) 358 return; 359 360 /* todo */ 361 } 362 363 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 364 bool enable) 365 { 366 adev->nbio_funcs->enable_doorbell_aperture(adev, enable); 367 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable); 368 } 369 370 static const struct amdgpu_ip_block_version nv_common_ip_block = 371 { 372 .type = AMD_IP_BLOCK_TYPE_COMMON, 373 .major = 1, 374 .minor = 0, 375 .rev = 0, 376 .funcs = &nv_common_ip_funcs, 377 }; 378 379 int nv_set_ip_blocks(struct amdgpu_device *adev) 380 { 381 /* Set IP register base before any HW register access */ 382 switch (adev->asic_type) { 383 case CHIP_NAVI10: 384 navi10_reg_base_init(adev); 385 break; 386 case CHIP_NAVI14: 387 navi14_reg_base_init(adev); 388 break; 389 default: 390 return -EINVAL; 391 } 392 393 adev->nbio_funcs = &nbio_v2_3_funcs; 394 395 adev->nbio_funcs->detect_hw_virt(adev); 396 397 switch (adev->asic_type) { 398 case CHIP_NAVI10: 399 case CHIP_NAVI14: 400 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 401 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 402 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 403 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 404 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 405 is_support_sw_smu(adev)) 406 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 407 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 408 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 409 #if defined(CONFIG_DRM_AMD_DC) 410 else if (amdgpu_device_has_dc_support(adev)) 411 amdgpu_device_ip_block_add(adev, &dm_ip_block); 412 #endif 413 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 414 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 415 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 416 is_support_sw_smu(adev)) 417 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 418 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 419 if (adev->enable_mes) 420 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 421 break; 422 default: 423 return -EINVAL; 424 } 425 426 return 0; 427 } 428 429 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 430 { 431 return adev->nbio_funcs->get_rev_id(adev); 432 } 433 434 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 435 { 436 adev->nbio_funcs->hdp_flush(adev, ring); 437 } 438 439 static void nv_invalidate_hdp(struct amdgpu_device *adev, 440 struct amdgpu_ring *ring) 441 { 442 if (!ring || !ring->funcs->emit_wreg) { 443 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 444 } else { 445 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 446 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 447 } 448 } 449 450 static bool nv_need_full_reset(struct amdgpu_device *adev) 451 { 452 return true; 453 } 454 455 static void nv_get_pcie_usage(struct amdgpu_device *adev, 456 uint64_t *count0, 457 uint64_t *count1) 458 { 459 /*TODO*/ 460 } 461 462 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 463 { 464 #if 0 465 u32 sol_reg; 466 467 if (adev->flags & AMD_IS_APU) 468 return false; 469 470 /* Check sOS sign of life register to confirm sys driver and sOS 471 * are already been loaded. 472 */ 473 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 474 if (sol_reg) 475 return true; 476 #endif 477 /* TODO: re-enable it when mode1 reset is functional */ 478 return false; 479 } 480 481 static void nv_init_doorbell_index(struct amdgpu_device *adev) 482 { 483 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 484 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 485 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 486 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 487 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 488 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 489 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 490 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 491 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 492 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 493 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 494 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 495 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 496 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 497 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 498 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 499 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 500 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 501 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 502 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 503 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 504 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 505 506 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 507 adev->doorbell_index.sdma_doorbell_range = 20; 508 } 509 510 static const struct amdgpu_asic_funcs nv_asic_funcs = 511 { 512 .read_disabled_bios = &nv_read_disabled_bios, 513 .read_bios_from_rom = &nv_read_bios_from_rom, 514 .read_register = &nv_read_register, 515 .reset = &nv_asic_reset, 516 .reset_method = &nv_asic_reset_method, 517 .set_vga_state = &nv_vga_set_state, 518 .get_xclk = &nv_get_xclk, 519 .set_uvd_clocks = &nv_set_uvd_clocks, 520 .set_vce_clocks = &nv_set_vce_clocks, 521 .get_config_memsize = &nv_get_config_memsize, 522 .flush_hdp = &nv_flush_hdp, 523 .invalidate_hdp = &nv_invalidate_hdp, 524 .init_doorbell_index = &nv_init_doorbell_index, 525 .need_full_reset = &nv_need_full_reset, 526 .get_pcie_usage = &nv_get_pcie_usage, 527 .need_reset_on_init = &nv_need_reset_on_init, 528 }; 529 530 static int nv_common_early_init(void *handle) 531 { 532 bool psp_enabled = false; 533 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 534 535 adev->smc_rreg = NULL; 536 adev->smc_wreg = NULL; 537 adev->pcie_rreg = &nv_pcie_rreg; 538 adev->pcie_wreg = &nv_pcie_wreg; 539 540 /* TODO: will add them during VCN v2 implementation */ 541 adev->uvd_ctx_rreg = NULL; 542 adev->uvd_ctx_wreg = NULL; 543 544 adev->didt_rreg = &nv_didt_rreg; 545 adev->didt_wreg = &nv_didt_wreg; 546 547 adev->asic_funcs = &nv_asic_funcs; 548 549 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && 550 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) 551 psp_enabled = true; 552 553 adev->rev_id = nv_get_rev_id(adev); 554 adev->external_rev_id = 0xff; 555 switch (adev->asic_type) { 556 case CHIP_NAVI10: 557 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 558 AMD_CG_SUPPORT_GFX_CGCG | 559 AMD_CG_SUPPORT_IH_CG | 560 AMD_CG_SUPPORT_HDP_MGCG | 561 AMD_CG_SUPPORT_HDP_LS | 562 AMD_CG_SUPPORT_SDMA_MGCG | 563 AMD_CG_SUPPORT_SDMA_LS | 564 AMD_CG_SUPPORT_MC_MGCG | 565 AMD_CG_SUPPORT_MC_LS | 566 AMD_CG_SUPPORT_ATHUB_MGCG | 567 AMD_CG_SUPPORT_ATHUB_LS | 568 AMD_CG_SUPPORT_VCN_MGCG | 569 AMD_CG_SUPPORT_BIF_MGCG | 570 AMD_CG_SUPPORT_BIF_LS; 571 adev->pg_flags = AMD_PG_SUPPORT_VCN | 572 AMD_PG_SUPPORT_VCN_DPG | 573 AMD_PG_SUPPORT_MMHUB | 574 AMD_PG_SUPPORT_ATHUB; 575 adev->external_rev_id = adev->rev_id + 0x1; 576 break; 577 case CHIP_NAVI14: 578 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 579 AMD_CG_SUPPORT_GFX_CGCG | 580 AMD_CG_SUPPORT_IH_CG | 581 AMD_CG_SUPPORT_HDP_MGCG | 582 AMD_CG_SUPPORT_HDP_LS | 583 AMD_CG_SUPPORT_SDMA_MGCG | 584 AMD_CG_SUPPORT_SDMA_LS | 585 AMD_CG_SUPPORT_MC_MGCG | 586 AMD_CG_SUPPORT_MC_LS | 587 AMD_CG_SUPPORT_ATHUB_MGCG | 588 AMD_CG_SUPPORT_ATHUB_LS | 589 AMD_CG_SUPPORT_VCN_MGCG | 590 AMD_CG_SUPPORT_BIF_MGCG | 591 AMD_CG_SUPPORT_BIF_LS; 592 adev->pg_flags = AMD_PG_SUPPORT_VCN | 593 AMD_PG_SUPPORT_VCN_DPG; 594 adev->external_rev_id = adev->rev_id + 0x1; /* ??? */ 595 break; 596 default: 597 /* FIXME: not supported yet */ 598 return -EINVAL; 599 } 600 601 return 0; 602 } 603 604 static int nv_common_late_init(void *handle) 605 { 606 return 0; 607 } 608 609 static int nv_common_sw_init(void *handle) 610 { 611 return 0; 612 } 613 614 static int nv_common_sw_fini(void *handle) 615 { 616 return 0; 617 } 618 619 static int nv_common_hw_init(void *handle) 620 { 621 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 622 623 /* enable pcie gen2/3 link */ 624 nv_pcie_gen3_enable(adev); 625 /* enable aspm */ 626 nv_program_aspm(adev); 627 /* setup nbio registers */ 628 adev->nbio_funcs->init_registers(adev); 629 /* enable the doorbell aperture */ 630 nv_enable_doorbell_aperture(adev, true); 631 632 return 0; 633 } 634 635 static int nv_common_hw_fini(void *handle) 636 { 637 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 638 639 /* disable the doorbell aperture */ 640 nv_enable_doorbell_aperture(adev, false); 641 642 return 0; 643 } 644 645 static int nv_common_suspend(void *handle) 646 { 647 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 648 649 return nv_common_hw_fini(adev); 650 } 651 652 static int nv_common_resume(void *handle) 653 { 654 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 655 656 return nv_common_hw_init(adev); 657 } 658 659 static bool nv_common_is_idle(void *handle) 660 { 661 return true; 662 } 663 664 static int nv_common_wait_for_idle(void *handle) 665 { 666 return 0; 667 } 668 669 static int nv_common_soft_reset(void *handle) 670 { 671 return 0; 672 } 673 674 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 675 bool enable) 676 { 677 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 678 uint32_t hdp_mem_pwr_cntl; 679 680 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 681 AMD_CG_SUPPORT_HDP_DS | 682 AMD_CG_SUPPORT_HDP_SD))) 683 return; 684 685 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 686 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 687 688 /* Before doing clock/power mode switch, 689 * forced on IPH & RC clock */ 690 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 691 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 692 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 693 RC_MEM_CLK_SOFT_OVERRIDE, 1); 694 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 695 696 /* HDP 5.0 doesn't support dynamic power mode switch, 697 * disable clock and power gating before any changing */ 698 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 699 IPH_MEM_POWER_CTRL_EN, 0); 700 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 701 IPH_MEM_POWER_LS_EN, 0); 702 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 703 IPH_MEM_POWER_DS_EN, 0); 704 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 705 IPH_MEM_POWER_SD_EN, 0); 706 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 707 RC_MEM_POWER_CTRL_EN, 0); 708 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 709 RC_MEM_POWER_LS_EN, 0); 710 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 711 RC_MEM_POWER_DS_EN, 0); 712 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 713 RC_MEM_POWER_SD_EN, 0); 714 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 715 716 /* only one clock gating mode (LS/DS/SD) can be enabled */ 717 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 718 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 719 HDP_MEM_POWER_CTRL, 720 IPH_MEM_POWER_LS_EN, enable); 721 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 722 HDP_MEM_POWER_CTRL, 723 RC_MEM_POWER_LS_EN, enable); 724 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 725 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 726 HDP_MEM_POWER_CTRL, 727 IPH_MEM_POWER_DS_EN, enable); 728 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 729 HDP_MEM_POWER_CTRL, 730 RC_MEM_POWER_DS_EN, enable); 731 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 732 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 733 HDP_MEM_POWER_CTRL, 734 IPH_MEM_POWER_SD_EN, enable); 735 /* RC should not use shut down mode, fallback to ds */ 736 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 737 HDP_MEM_POWER_CTRL, 738 RC_MEM_POWER_DS_EN, enable); 739 } 740 741 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 742 743 /* restore IPH & RC clock override after clock/power mode changing */ 744 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 745 } 746 747 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 748 bool enable) 749 { 750 uint32_t hdp_clk_cntl; 751 752 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 753 return; 754 755 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 756 757 if (enable) { 758 hdp_clk_cntl &= 759 ~(uint32_t) 760 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 761 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 762 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 763 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 764 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 765 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 766 } else { 767 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 768 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 769 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 770 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 771 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 772 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 773 } 774 775 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 776 } 777 778 static int nv_common_set_clockgating_state(void *handle, 779 enum amd_clockgating_state state) 780 { 781 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 782 783 if (amdgpu_sriov_vf(adev)) 784 return 0; 785 786 switch (adev->asic_type) { 787 case CHIP_NAVI10: 788 case CHIP_NAVI14: 789 adev->nbio_funcs->update_medium_grain_clock_gating(adev, 790 state == AMD_CG_STATE_GATE ? true : false); 791 adev->nbio_funcs->update_medium_grain_light_sleep(adev, 792 state == AMD_CG_STATE_GATE ? true : false); 793 nv_update_hdp_mem_power_gating(adev, 794 state == AMD_CG_STATE_GATE ? true : false); 795 nv_update_hdp_clock_gating(adev, 796 state == AMD_CG_STATE_GATE ? true : false); 797 break; 798 default: 799 break; 800 } 801 return 0; 802 } 803 804 static int nv_common_set_powergating_state(void *handle, 805 enum amd_powergating_state state) 806 { 807 /* TODO */ 808 return 0; 809 } 810 811 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 812 { 813 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 814 uint32_t tmp; 815 816 if (amdgpu_sriov_vf(adev)) 817 *flags = 0; 818 819 adev->nbio_funcs->get_clockgating_state(adev, flags); 820 821 /* AMD_CG_SUPPORT_HDP_MGCG */ 822 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 823 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 824 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 825 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 826 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 827 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 828 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 829 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 830 831 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 832 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 833 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 834 *flags |= AMD_CG_SUPPORT_HDP_LS; 835 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 836 *flags |= AMD_CG_SUPPORT_HDP_DS; 837 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 838 *flags |= AMD_CG_SUPPORT_HDP_SD; 839 840 return; 841 } 842 843 static const struct amd_ip_funcs nv_common_ip_funcs = { 844 .name = "nv_common", 845 .early_init = nv_common_early_init, 846 .late_init = nv_common_late_init, 847 .sw_init = nv_common_sw_init, 848 .sw_fini = nv_common_sw_fini, 849 .hw_init = nv_common_hw_init, 850 .hw_fini = nv_common_hw_fini, 851 .suspend = nv_common_suspend, 852 .resume = nv_common_resume, 853 .is_idle = nv_common_is_idle, 854 .wait_for_idle = nv_common_wait_for_idle, 855 .soft_reset = nv_common_soft_reset, 856 .set_clockgating_state = nv_common_set_clockgating_state, 857 .set_powergating_state = nv_common_set_powergating_state, 858 .get_clockgating_state = nv_common_get_clockgating_state, 859 }; 860