1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 286f786950SAlex Deucher #include <drm/amdgpu_drm.h> 296f786950SAlex Deucher 30c6b6a421SHawking Zhang #include "amdgpu.h" 31c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 32c6b6a421SHawking Zhang #include "amdgpu_ih.h" 33c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 34c6b6a421SHawking Zhang #include "amdgpu_vce.h" 35c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 36c6b6a421SHawking Zhang #include "amdgpu_psp.h" 37c6b6a421SHawking Zhang #include "atom.h" 38c6b6a421SHawking Zhang #include "amd_pcie.h" 39c6b6a421SHawking Zhang 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 41c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 423967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 43c6b6a421SHawking Zhang 44c6b6a421SHawking Zhang #include "soc15.h" 45c6b6a421SHawking Zhang #include "soc15_common.h" 46c6b6a421SHawking Zhang #include "gmc_v10_0.h" 47c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 48c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 49bebc0762SHawking Zhang #include "nbio_v2_3.h" 50a7e91bd7SHuang Rui #include "nbio_v7_2.h" 51bf087285SLikun Gao #include "hdp_v5_0.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59b8f10585SLeo Liu #include "vcn_v3_0.h" 604d72dd12SLeo Liu #include "jpeg_v3_0.h" 61733ee71aSRyan Taylor #include "amdgpu_vkms.h" 62c6b6a421SHawking Zhang #include "mes_v10_1.h" 63b05b6903SJiange Zhao #include "mxgpu_nv.h" 640bf7f2dcSLikun Gao #include "smuio_v11_0.h" 650bf7f2dcSLikun Gao #include "smuio_v11_0_6.h" 66c6b6a421SHawking Zhang 67c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 68c6b6a421SHawking Zhang 693b246e8bSAlex Deucher /* Navi */ 703b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 713b246e8bSAlex Deucher { 729075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 739075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 743b246e8bSAlex Deucher }; 753b246e8bSAlex Deucher 763b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_encode = 773b246e8bSAlex Deucher { 783b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 793b246e8bSAlex Deucher .codec_array = nv_video_codecs_encode_array, 803b246e8bSAlex Deucher }; 813b246e8bSAlex Deucher 823b246e8bSAlex Deucher /* Navi1x */ 833b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 843b246e8bSAlex Deucher { 8565009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 8665009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 8765009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 8865009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 899075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 909075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 919075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 923b246e8bSAlex Deucher }; 933b246e8bSAlex Deucher 943b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_decode = 953b246e8bSAlex Deucher { 963b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 973b246e8bSAlex Deucher .codec_array = nv_video_codecs_decode_array, 983b246e8bSAlex Deucher }; 993b246e8bSAlex Deucher 1003b246e8bSAlex Deucher /* Sienna Cichlid */ 101c6fa6fe9SThong Thai static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = { 102c6fa6fe9SThong Thai {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)}, 103c6fa6fe9SThong Thai {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)}, 104c6fa6fe9SThong Thai }; 105c6fa6fe9SThong Thai 106c6fa6fe9SThong Thai static const struct amdgpu_video_codecs sc_video_codecs_encode = { 107c6fa6fe9SThong Thai .codec_count = ARRAY_SIZE(sc_video_codecs_encode_array), 108c6fa6fe9SThong Thai .codec_array = sc_video_codecs_encode_array, 109c6fa6fe9SThong Thai }; 110c6fa6fe9SThong Thai 11138433412SAlex Deucher static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = 1123b246e8bSAlex Deucher { 11365009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 11465009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 11565009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 11665009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 1179075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 1189075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 1199075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 1209075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 1213b246e8bSAlex Deucher }; 1223b246e8bSAlex Deucher 12338433412SAlex Deucher static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = 1243b246e8bSAlex Deucher { 12538433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 12638433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 12738433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 12838433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 12938433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 13038433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 13138433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 13238433412SAlex Deucher }; 13338433412SAlex Deucher 13438433412SAlex Deucher static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = 13538433412SAlex Deucher { 13638433412SAlex Deucher .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0), 13738433412SAlex Deucher .codec_array = sc_video_codecs_decode_array_vcn0, 13838433412SAlex Deucher }; 13938433412SAlex Deucher 14038433412SAlex Deucher static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = 14138433412SAlex Deucher { 14238433412SAlex Deucher .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1), 14338433412SAlex Deucher .codec_array = sc_video_codecs_decode_array_vcn1, 1443b246e8bSAlex Deucher }; 1453b246e8bSAlex Deucher 146ed9d2053SBokun Zhang /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 147ed9d2053SBokun Zhang static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 148ed9d2053SBokun Zhang { 149c6fa6fe9SThong Thai {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)}, 150c6fa6fe9SThong Thai {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)}, 151ed9d2053SBokun Zhang }; 152ed9d2053SBokun Zhang 15338433412SAlex Deucher static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = 154ed9d2053SBokun Zhang { 15565009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 15665009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 15765009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 15865009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 1599075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 1609075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 1619075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 1629075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 163ed9d2053SBokun Zhang }; 164ed9d2053SBokun Zhang 16538433412SAlex Deucher static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = 16638433412SAlex Deucher { 16738433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 16838433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 16938433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 17038433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 17138433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 17238433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 17338433412SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 17438433412SAlex Deucher }; 17538433412SAlex Deucher 176ed9d2053SBokun Zhang static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 177ed9d2053SBokun Zhang { 178ed9d2053SBokun Zhang .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 179ed9d2053SBokun Zhang .codec_array = sriov_sc_video_codecs_encode_array, 180ed9d2053SBokun Zhang }; 181ed9d2053SBokun Zhang 18238433412SAlex Deucher static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = 183ed9d2053SBokun Zhang { 18438433412SAlex Deucher .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0), 18538433412SAlex Deucher .codec_array = sriov_sc_video_codecs_decode_array_vcn0, 18638433412SAlex Deucher }; 18738433412SAlex Deucher 18838433412SAlex Deucher static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = 18938433412SAlex Deucher { 19038433412SAlex Deucher .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1), 19138433412SAlex Deucher .codec_array = sriov_sc_video_codecs_decode_array_vcn1, 192ed9d2053SBokun Zhang }; 193ed9d2053SBokun Zhang 194b3a24461SVeerabadhran Gopalakrishnan /* Beige Goby*/ 195b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 19665009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 197b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 198b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 199b3a24461SVeerabadhran Gopalakrishnan }; 200b3a24461SVeerabadhran Gopalakrishnan 201b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs bg_video_codecs_decode = { 202b3a24461SVeerabadhran Gopalakrishnan .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 203b3a24461SVeerabadhran Gopalakrishnan .codec_array = bg_video_codecs_decode_array, 204b3a24461SVeerabadhran Gopalakrishnan }; 205b3a24461SVeerabadhran Gopalakrishnan 206b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs bg_video_codecs_encode = { 207b3a24461SVeerabadhran Gopalakrishnan .codec_count = 0, 208b3a24461SVeerabadhran Gopalakrishnan .codec_array = NULL, 209b3a24461SVeerabadhran Gopalakrishnan }; 210b3a24461SVeerabadhran Gopalakrishnan 21155439817SVeerabadhran Gopalakrishnan /* Yellow Carp*/ 21255439817SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 21365009bf2SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 21455439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 21555439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 21655439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 21797e50305SAlex Deucher {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 21855439817SVeerabadhran Gopalakrishnan }; 21955439817SVeerabadhran Gopalakrishnan 22055439817SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs yc_video_codecs_decode = { 221f72ac409SVeerabadhran Gopalakrishnan .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 222f72ac409SVeerabadhran Gopalakrishnan .codec_array = yc_video_codecs_decode_array, 22355439817SVeerabadhran Gopalakrishnan }; 22455439817SVeerabadhran Gopalakrishnan 2253b246e8bSAlex Deucher static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 2263b246e8bSAlex Deucher const struct amdgpu_video_codecs **codecs) 2273b246e8bSAlex Deucher { 22838433412SAlex Deucher if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 22938433412SAlex Deucher return -EINVAL; 23038433412SAlex Deucher 2311d789535SAlex Deucher switch (adev->ip_versions[UVD_HWIP][0]) { 2323e67f4f2SAlex Deucher case IP_VERSION(3, 0, 0): 2334d395f93SGuchun Chen case IP_VERSION(3, 0, 64): 234da3b36a2SJane Jian case IP_VERSION(3, 0, 192): 235ed9d2053SBokun Zhang if (amdgpu_sriov_vf(adev)) { 23638433412SAlex Deucher if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 237ed9d2053SBokun Zhang if (encode) 238ed9d2053SBokun Zhang *codecs = &sriov_sc_video_codecs_encode; 239ed9d2053SBokun Zhang else 24038433412SAlex Deucher *codecs = &sriov_sc_video_codecs_decode_vcn1; 24138433412SAlex Deucher } else { 24238433412SAlex Deucher if (encode) 24338433412SAlex Deucher *codecs = &sriov_sc_video_codecs_encode; 24438433412SAlex Deucher else 24538433412SAlex Deucher *codecs = &sriov_sc_video_codecs_decode_vcn0; 24638433412SAlex Deucher } 24738433412SAlex Deucher } else { 24838433412SAlex Deucher if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 24938433412SAlex Deucher if (encode) 250c6fa6fe9SThong Thai *codecs = &sc_video_codecs_encode; 25138433412SAlex Deucher else 25238433412SAlex Deucher *codecs = &sc_video_codecs_decode_vcn1; 253ed9d2053SBokun Zhang } else { 254ed9d2053SBokun Zhang if (encode) 255c6fa6fe9SThong Thai *codecs = &sc_video_codecs_encode; 256ed9d2053SBokun Zhang else 25738433412SAlex Deucher *codecs = &sc_video_codecs_decode_vcn0; 25838433412SAlex Deucher } 259ed9d2053SBokun Zhang } 260ed9d2053SBokun Zhang return 0; 2613e67f4f2SAlex Deucher case IP_VERSION(3, 0, 16): 2623e67f4f2SAlex Deucher case IP_VERSION(3, 0, 2): 2633b246e8bSAlex Deucher if (encode) 264c6fa6fe9SThong Thai *codecs = &sc_video_codecs_encode; 2653b246e8bSAlex Deucher else 26638433412SAlex Deucher *codecs = &sc_video_codecs_decode_vcn0; 2673b246e8bSAlex Deucher return 0; 2683e67f4f2SAlex Deucher case IP_VERSION(3, 1, 1): 269afc2f276SBoyuan Zhang case IP_VERSION(3, 1, 2): 27055439817SVeerabadhran Gopalakrishnan if (encode) 271c6fa6fe9SThong Thai *codecs = &sc_video_codecs_encode; 27255439817SVeerabadhran Gopalakrishnan else 27355439817SVeerabadhran Gopalakrishnan *codecs = &yc_video_codecs_decode; 27455439817SVeerabadhran Gopalakrishnan return 0; 2753e67f4f2SAlex Deucher case IP_VERSION(3, 0, 33): 276b3a24461SVeerabadhran Gopalakrishnan if (encode) 277b3a24461SVeerabadhran Gopalakrishnan *codecs = &bg_video_codecs_encode; 278b3a24461SVeerabadhran Gopalakrishnan else 279b3a24461SVeerabadhran Gopalakrishnan *codecs = &bg_video_codecs_decode; 280b3a24461SVeerabadhran Gopalakrishnan return 0; 2813e67f4f2SAlex Deucher case IP_VERSION(2, 0, 0): 2823e67f4f2SAlex Deucher case IP_VERSION(2, 0, 2): 2833b246e8bSAlex Deucher if (encode) 2843b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2853b246e8bSAlex Deucher else 2863b246e8bSAlex Deucher *codecs = &nv_video_codecs_decode; 2873b246e8bSAlex Deucher return 0; 2883b246e8bSAlex Deucher default: 2893b246e8bSAlex Deucher return -EINVAL; 2903b246e8bSAlex Deucher } 2913b246e8bSAlex Deucher } 2923b246e8bSAlex Deucher 293c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 294c6b6a421SHawking Zhang { 295c6b6a421SHawking Zhang unsigned long flags, address, data; 296c6b6a421SHawking Zhang u32 r; 297c6b6a421SHawking Zhang 298c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 299c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 300c6b6a421SHawking Zhang 301c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 302c6b6a421SHawking Zhang WREG32(address, (reg)); 303c6b6a421SHawking Zhang r = RREG32(data); 304c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 305c6b6a421SHawking Zhang return r; 306c6b6a421SHawking Zhang } 307c6b6a421SHawking Zhang 308c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 309c6b6a421SHawking Zhang { 310c6b6a421SHawking Zhang unsigned long flags, address, data; 311c6b6a421SHawking Zhang 312c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 313c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 314c6b6a421SHawking Zhang 315c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 316c6b6a421SHawking Zhang WREG32(address, (reg)); 317c6b6a421SHawking Zhang WREG32(data, (v)); 318c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 319c6b6a421SHawking Zhang } 320c6b6a421SHawking Zhang 321c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 322c6b6a421SHawking Zhang { 323bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 324c6b6a421SHawking Zhang } 325c6b6a421SHawking Zhang 326c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 327c6b6a421SHawking Zhang { 328462a70d8STao Zhou return adev->clock.spll.reference_freq; 329c6b6a421SHawking Zhang } 330c6b6a421SHawking Zhang 331c6b6a421SHawking Zhang 332c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 333c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 334c6b6a421SHawking Zhang { 335c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 336c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 337c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 338c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 339c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 340c6b6a421SHawking Zhang 341f2958a8bSPeng Ju Zhou WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 342c6b6a421SHawking Zhang } 343c6b6a421SHawking Zhang 344c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 345c6b6a421SHawking Zhang { 346c6b6a421SHawking Zhang /* todo */ 347c6b6a421SHawking Zhang return false; 348c6b6a421SHawking Zhang } 349c6b6a421SHawking Zhang 350c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 351c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 352c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 353c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 354c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 355c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 356c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 357c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 358c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 359c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 360c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 361c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 362c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 363c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 364c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 365c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 366664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 367c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 368c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 369c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 370c6b6a421SHawking Zhang }; 371c6b6a421SHawking Zhang 372c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 373c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 374c6b6a421SHawking Zhang { 375c6b6a421SHawking Zhang uint32_t val; 376c6b6a421SHawking Zhang 377c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 378c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 379d51ac6d0SLe Ma amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 380c6b6a421SHawking Zhang 381c6b6a421SHawking Zhang val = RREG32(reg_offset); 382c6b6a421SHawking Zhang 383c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 384d51ac6d0SLe Ma amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 385c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 386c6b6a421SHawking Zhang return val; 387c6b6a421SHawking Zhang } 388c6b6a421SHawking Zhang 389c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 390c6b6a421SHawking Zhang bool indexed, u32 se_num, 391c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 392c6b6a421SHawking Zhang { 393c6b6a421SHawking Zhang if (indexed) { 394c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 395c6b6a421SHawking Zhang } else { 396c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 397c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 398c6b6a421SHawking Zhang return RREG32(reg_offset); 399c6b6a421SHawking Zhang } 400c6b6a421SHawking Zhang } 401c6b6a421SHawking Zhang 402c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 403c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 404c6b6a421SHawking Zhang { 405c6b6a421SHawking Zhang uint32_t i; 406c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 407c6b6a421SHawking Zhang 408c6b6a421SHawking Zhang *value = 0; 409c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 410c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 411920da947SAlex Deucher if (!adev->reg_offset[en->hwip][en->inst]) 412920da947SAlex Deucher continue; 413920da947SAlex Deucher else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 414bf1781e1SAlex Deucher + en->reg_offset)) 415c6b6a421SHawking Zhang continue; 416c6b6a421SHawking Zhang 417c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 418c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 419c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 420c6b6a421SHawking Zhang return 0; 421c6b6a421SHawking Zhang } 422c6b6a421SHawking Zhang return -EINVAL; 423c6b6a421SHawking Zhang } 424c6b6a421SHawking Zhang 425b913ec62SAlex Deucher static int nv_asic_mode2_reset(struct amdgpu_device *adev) 426b913ec62SAlex Deucher { 427b913ec62SAlex Deucher u32 i; 428b913ec62SAlex Deucher int ret = 0; 429b913ec62SAlex Deucher 430b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, true); 431b913ec62SAlex Deucher 432b913ec62SAlex Deucher /* disable BM */ 433b913ec62SAlex Deucher pci_clear_master(adev->pdev); 434b913ec62SAlex Deucher 435b913ec62SAlex Deucher amdgpu_device_cache_pci_state(adev->pdev); 436b913ec62SAlex Deucher 437b913ec62SAlex Deucher ret = amdgpu_dpm_mode2_reset(adev); 438b913ec62SAlex Deucher if (ret) 439b913ec62SAlex Deucher dev_err(adev->dev, "GPU mode2 reset failed\n"); 440b913ec62SAlex Deucher 441b913ec62SAlex Deucher amdgpu_device_load_pci_state(adev->pdev); 442b913ec62SAlex Deucher 443b913ec62SAlex Deucher /* wait for asic to come out of reset */ 444b913ec62SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 445b913ec62SAlex Deucher u32 memsize = adev->nbio.funcs->get_memsize(adev); 446b913ec62SAlex Deucher 447b913ec62SAlex Deucher if (memsize != 0xffffffff) 448b913ec62SAlex Deucher break; 449b913ec62SAlex Deucher udelay(1); 450b913ec62SAlex Deucher } 451b913ec62SAlex Deucher 452b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, false); 453b913ec62SAlex Deucher 454b913ec62SAlex Deucher return ret; 455b913ec62SAlex Deucher } 456b913ec62SAlex Deucher 4572ddc6c3eSAlex Deucher static enum amd_reset_method 4582ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 4592ddc6c3eSAlex Deucher { 460273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 46116086355SAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 462f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_BACO || 463f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_PCI) 464273da6ffSWenhui Sheng return amdgpu_reset_method; 465273da6ffSWenhui Sheng 466273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 467273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 468273da6ffSWenhui Sheng amdgpu_reset_method); 469273da6ffSWenhui Sheng 4701d789535SAlex Deucher switch (adev->ip_versions[MP1_HWIP][0]) { 4713e67f4f2SAlex Deucher case IP_VERSION(11, 5, 0): 4723e67f4f2SAlex Deucher case IP_VERSION(13, 0, 1): 4733e67f4f2SAlex Deucher case IP_VERSION(13, 0, 3): 47450439060SYifan Zhang case IP_VERSION(13, 0, 5): 475db749b76SPrike Liang case IP_VERSION(13, 0, 8): 47616086355SAlex Deucher return AMD_RESET_METHOD_MODE2; 4773e67f4f2SAlex Deucher case IP_VERSION(11, 0, 7): 4783e67f4f2SAlex Deucher case IP_VERSION(11, 0, 11): 4793e67f4f2SAlex Deucher case IP_VERSION(11, 0, 12): 4803e67f4f2SAlex Deucher case IP_VERSION(11, 0, 13): 481ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 482ca6fd7a6SLikun Gao default: 483181e772fSEvan Quan if (amdgpu_dpm_is_baco_supported(adev)) 4842ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 4852ddc6c3eSAlex Deucher else 4862ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 4872ddc6c3eSAlex Deucher } 488ca6fd7a6SLikun Gao } 4892ddc6c3eSAlex Deucher 490c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 491c6b6a421SHawking Zhang { 492767acabdSKevin Wang int ret = 0; 493c6b6a421SHawking Zhang 49416086355SAlex Deucher switch (nv_asic_reset_method(adev)) { 495f172865aSAlex Deucher case AMD_RESET_METHOD_PCI: 496f172865aSAlex Deucher dev_info(adev->dev, "PCI reset\n"); 497f172865aSAlex Deucher ret = amdgpu_device_pci_reset(adev); 498f172865aSAlex Deucher break; 49916086355SAlex Deucher case AMD_RESET_METHOD_BACO: 50011043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 501181e772fSEvan Quan ret = amdgpu_dpm_baco_reset(adev); 50216086355SAlex Deucher break; 50316086355SAlex Deucher case AMD_RESET_METHOD_MODE2: 50416086355SAlex Deucher dev_info(adev->dev, "MODE2 reset\n"); 505b913ec62SAlex Deucher ret = nv_asic_mode2_reset(adev); 50616086355SAlex Deucher break; 50716086355SAlex Deucher default: 50811043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 5095c03e584SFeifei Xu ret = amdgpu_device_mode1_reset(adev); 51016086355SAlex Deucher break; 51111043b7aSAlex Deucher } 512767acabdSKevin Wang 513767acabdSKevin Wang return ret; 514c6b6a421SHawking Zhang } 515c6b6a421SHawking Zhang 516c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 517c6b6a421SHawking Zhang { 518c6b6a421SHawking Zhang /* todo */ 519c6b6a421SHawking Zhang return 0; 520c6b6a421SHawking Zhang } 521c6b6a421SHawking Zhang 522c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 523c6b6a421SHawking Zhang { 524c6b6a421SHawking Zhang /* todo */ 525c6b6a421SHawking Zhang return 0; 526c6b6a421SHawking Zhang } 527c6b6a421SHawking Zhang 528c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 529c6b6a421SHawking Zhang { 5302b072442SKai-Heng Feng if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_aspm_support_quirk()) 531c6b6a421SHawking Zhang return; 532c6b6a421SHawking Zhang 5333273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 534e1edaeafSLikun Gao (adev->nbio.funcs->program_aspm)) 535e1edaeafSLikun Gao adev->nbio.funcs->program_aspm(adev); 536e1edaeafSLikun Gao 537c6b6a421SHawking Zhang } 538c6b6a421SHawking Zhang 539a1f62df7SAlex Deucher const struct amdgpu_ip_block_version nv_common_ip_block = 540c6b6a421SHawking Zhang { 541c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 542c6b6a421SHawking Zhang .major = 1, 543c6b6a421SHawking Zhang .minor = 0, 544c6b6a421SHawking Zhang .rev = 0, 545c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 546c6b6a421SHawking Zhang }; 547c6b6a421SHawking Zhang 548c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 549c1299461SWenhui Sheng { 550c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 551c1299461SWenhui Sheng } 552c1299461SWenhui Sheng 553c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 554c6b6a421SHawking Zhang { 555c6b6a421SHawking Zhang return true; 556c6b6a421SHawking Zhang } 557c6b6a421SHawking Zhang 558c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 559c6b6a421SHawking Zhang { 560c6b6a421SHawking Zhang u32 sol_reg; 561c6b6a421SHawking Zhang 562c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 563c6b6a421SHawking Zhang return false; 564c6b6a421SHawking Zhang 565c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 566c6b6a421SHawking Zhang * are already been loaded. 567c6b6a421SHawking Zhang */ 568c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 569c6b6a421SHawking Zhang if (sol_reg) 570c6b6a421SHawking Zhang return true; 5713967ae6dSAlex Deucher 572c6b6a421SHawking Zhang return false; 573c6b6a421SHawking Zhang } 574c6b6a421SHawking Zhang 5752af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 5762af81531SKevin Wang { 5772af81531SKevin Wang 5782af81531SKevin Wang /* TODO 5792af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 5802af81531SKevin Wang * */ 5812af81531SKevin Wang 5822af81531SKevin Wang return 0; 5832af81531SKevin Wang } 5842af81531SKevin Wang 585c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 586c6b6a421SHawking Zhang { 587c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 588c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 589c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 590c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 591c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 592c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 593c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 594c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 595c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 596c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 597c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 598c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 599c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 600fd0ed91aSJack Xiao adev->doorbell_index.gfx_userqueue_start = 601fd0ed91aSJack Xiao AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 602fd0ed91aSJack Xiao adev->doorbell_index.gfx_userqueue_end = 603fd0ed91aSJack Xiao AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 604b608e785SJack Xiao adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 605b608e785SJack Xiao adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 606c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 607c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 608157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 609157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 610c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 611c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 612c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 613c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 614c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 615c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 616c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 617c6b6a421SHawking Zhang 618c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 619c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 620c6b6a421SHawking Zhang } 621c6b6a421SHawking Zhang 622a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 623a7173731SAlex Deucher { 624a7173731SAlex Deucher } 625a7173731SAlex Deucher 62627747293SEvan Quan static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 62727747293SEvan Quan bool enter) 62827747293SEvan Quan { 62927747293SEvan Quan if (enter) 63086b20703SLe Ma amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 63127747293SEvan Quan else 63286b20703SLe Ma amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 63327747293SEvan Quan 63427747293SEvan Quan if (adev->gfx.funcs->update_perfmon_mgcg) 63527747293SEvan Quan adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 63627747293SEvan Quan 6373273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 638d01899d3SMario Limonciello (adev->nbio.funcs->enable_aspm) && 639d01899d3SMario Limonciello amdgpu_device_should_use_aspm(adev)) 64027747293SEvan Quan adev->nbio.funcs->enable_aspm(adev, !enter); 64127747293SEvan Quan 64227747293SEvan Quan return 0; 64327747293SEvan Quan } 64427747293SEvan Quan 645c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 646c6b6a421SHawking Zhang { 647c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 64804022982SHawking Zhang .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 649c6b6a421SHawking Zhang .read_register = &nv_read_register, 650c6b6a421SHawking Zhang .reset = &nv_asic_reset, 6512ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 652c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 653c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 654c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 655c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 656c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 657c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 658c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 6592af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 660181e772fSEvan Quan .supports_baco = &amdgpu_dpm_is_baco_supported, 661a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 66227747293SEvan Quan .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 6633b246e8bSAlex Deucher .query_video_codecs = &nv_query_video_codecs, 664c6b6a421SHawking Zhang }; 665c6b6a421SHawking Zhang 666c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 667c6b6a421SHawking Zhang { 668923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 669c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 670c6b6a421SHawking Zhang 671d3a21f7eSFelix Kuehling if (!amdgpu_sriov_vf(adev)) { 672923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 673923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 674d3a21f7eSFelix Kuehling } 675c6b6a421SHawking Zhang adev->smc_rreg = NULL; 676c6b6a421SHawking Zhang adev->smc_wreg = NULL; 67765ba96e9SHawking Zhang adev->pcie_rreg = &amdgpu_device_indirect_rreg; 67865ba96e9SHawking Zhang adev->pcie_wreg = &amdgpu_device_indirect_wreg; 67965ba96e9SHawking Zhang adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 68065ba96e9SHawking Zhang adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 68186700a40SXiaojian Du adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 68286700a40SXiaojian Du adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 683c6b6a421SHawking Zhang 684c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 685c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 686c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 687c6b6a421SHawking Zhang 688c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 689c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 690c6b6a421SHawking Zhang 691c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 692c6b6a421SHawking Zhang 693dabc114eSHawking Zhang adev->rev_id = amdgpu_device_get_rev_id(adev); 694c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 6953e67f4f2SAlex Deucher /* TODO: split the GC and PG flags based on the relevant IP version for which 6963e67f4f2SAlex Deucher * they are relevant. 6973e67f4f2SAlex Deucher */ 6981d789535SAlex Deucher switch (adev->ip_versions[GC_HWIP][0]) { 6993e67f4f2SAlex Deucher case IP_VERSION(10, 1, 10): 700c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 701c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 702c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 703c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 704c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 705c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 706c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 707c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 708c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 709c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 710c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 711c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 712099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 713c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 714c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 715157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 716c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 717099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 718a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 719c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 720c6b6a421SHawking Zhang break; 7213e67f4f2SAlex Deucher case IP_VERSION(10, 1, 1): 722d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 723d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 724d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 725d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 726d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 727d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 728d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 729d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 730d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 731d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 732d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 733d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 734099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 735d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 736d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 7370377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 738099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7390377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 74035ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 7415e71e011SXiaojie Yuan break; 7423e67f4f2SAlex Deucher case IP_VERSION(10, 1, 2): 743dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 744dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 745dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 746dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 7475211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 748fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 7495211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 750358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 751358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 7528b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 7538b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 754ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 755ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 75665872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 757099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 758099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 759c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 7605ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 761099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7621b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 763df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 764df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 765df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 766df5e984cSTiecheng Zhou */ 767df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 768df5e984cSTiecheng Zhou adev->rev_id = 0; 76974b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 77074b5e509SXiaojie Yuan break; 7713e67f4f2SAlex Deucher case IP_VERSION(10, 3, 0): 77200194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 77300194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 7741d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 77500194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 77698f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 77700194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 778ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 779ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 7803a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 781bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 782bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 783b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 784d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 785b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 7861b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 7871b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 788c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 789c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 790c45fbe1bSJack Zhang adev->cg_flags = 0; 791c45fbe1bSJack Zhang adev->pg_flags = 0; 792c45fbe1bSJack Zhang } 793117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 794117910edSLikun Gao break; 7953e67f4f2SAlex Deucher case IP_VERSION(10, 3, 2): 79640582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 79740582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 7981d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 79940582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 80040582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 80192c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 80292c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 8034759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 8044759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 80585e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 80685e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 807c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 80800740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 80947fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 81047fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 81147fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 812543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 813543aa259SJiansong Chen break; 8143e67f4f2SAlex Deucher case IP_VERSION(10, 3, 1): 81551a7e938SJinzhou.Su adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 81651a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_MGLS | 81751a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CP_LS | 81851a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_RLC_LS | 81951a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CGCG | 820ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_CGLS | 821ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_3D_CGCG | 82207f9c22fSBoyuan Zhang AMD_CG_SUPPORT_GFX_3D_CGLS | 8230ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_MGCG | 8240ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_LS | 825a3964ec4SJinzhou.Su AMD_CG_SUPPORT_GFX_FGCG | 82607f9c22fSBoyuan Zhang AMD_CG_SUPPORT_VCN_MGCG | 827ef9bcfdeSJinzhou Su AMD_CG_SUPPORT_SDMA_MGCG | 828ec0f72cbSJinzhou Su AMD_CG_SUPPORT_SDMA_LS | 82907f9c22fSBoyuan Zhang AMD_CG_SUPPORT_JPEG_MGCG; 83007f9c22fSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 83107f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN | 83207f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 83307f9c22fSBoyuan Zhang AMD_PG_SUPPORT_JPEG; 834c345c89bSHuang Rui if (adev->apu_flags & AMD_APU_IS_VANGOGH) 835026570e6SHuang Rui adev->external_rev_id = adev->rev_id + 0x01; 836026570e6SHuang Rui break; 8373e67f4f2SAlex Deucher case IP_VERSION(10, 3, 4): 838583e5a5eSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 839583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 8401d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 841583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 842583e5a5eSTao Zhou AMD_CG_SUPPORT_VCN_MGCG | 843135333a0STao Zhou AMD_CG_SUPPORT_JPEG_MGCG | 844135333a0STao Zhou AMD_CG_SUPPORT_MC_MGCG | 8452c70c332STao Zhou AMD_CG_SUPPORT_MC_LS | 8462c70c332STao Zhou AMD_CG_SUPPORT_HDP_MGCG | 8478e3bfb99STao Zhou AMD_CG_SUPPORT_HDP_LS | 8488e3bfb99STao Zhou AMD_CG_SUPPORT_IH_CG; 849d5bc1579SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_VCN | 850cc6161aaSJames Zhu AMD_PG_SUPPORT_VCN_DPG | 85173da8e86STao Zhou AMD_PG_SUPPORT_JPEG | 85273da8e86STao Zhou AMD_PG_SUPPORT_ATHUB | 85373da8e86STao Zhou AMD_PG_SUPPORT_MMHUB; 854550c58e0STao Zhou adev->external_rev_id = adev->rev_id + 0x3c; 855550c58e0STao Zhou break; 8563e67f4f2SAlex Deucher case IP_VERSION(10, 3, 5): 857bc6bd46bSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 858bc6bd46bSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 859d69d278fSTao Zhou AMD_CG_SUPPORT_GFX_CGLS | 8605d36b865STao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 8615d36b865STao Zhou AMD_CG_SUPPORT_MC_MGCG | 862170c193fSTao Zhou AMD_CG_SUPPORT_MC_LS | 863170c193fSTao Zhou AMD_CG_SUPPORT_HDP_MGCG | 864a764bef3STao Zhou AMD_CG_SUPPORT_HDP_LS | 865e47e4c0eSVeerabadhran Gopalakrishnan AMD_CG_SUPPORT_IH_CG | 866e47e4c0eSVeerabadhran Gopalakrishnan AMD_CG_SUPPORT_VCN_MGCG; 867f703d4b6SVeerabadhran Gopalakrishnan adev->pg_flags = AMD_PG_SUPPORT_VCN | 868147de218STao Zhou AMD_PG_SUPPORT_VCN_DPG | 869147de218STao Zhou AMD_PG_SUPPORT_ATHUB | 870147de218STao Zhou AMD_PG_SUPPORT_MMHUB; 8718573035aSChengming Gui adev->external_rev_id = adev->rev_id + 0x46; 8728573035aSChengming Gui break; 8733e67f4f2SAlex Deucher case IP_VERSION(10, 3, 3): 8749c6c48e6SAaron Liu adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 8759c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_MGLS | 8769c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CGCG | 8779c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CGLS | 8789c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_3D_CGCG | 8799c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_3D_CGLS | 8809c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_RLC_LS | 8819c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CP_LS | 88283ae09b5SAaron Liu AMD_CG_SUPPORT_GFX_FGCG | 88383ae09b5SAaron Liu AMD_CG_SUPPORT_MC_MGCG | 884f1e9aa65SAaron Liu AMD_CG_SUPPORT_MC_LS | 8856bd95572SAaron Liu AMD_CG_SUPPORT_SDMA_LS | 8866bd95572SAaron Liu AMD_CG_SUPPORT_HDP_MGCG | 887b7dd14c7SAaron Liu AMD_CG_SUPPORT_HDP_LS | 888b7dd14c7SAaron Liu AMD_CG_SUPPORT_ATHUB_MGCG | 889db72c3faSAaron Liu AMD_CG_SUPPORT_ATHUB_LS | 890948b1216SAaron Liu AMD_CG_SUPPORT_IH_CG | 891948b1216SAaron Liu AMD_CG_SUPPORT_VCN_MGCG | 892*f05f4fe6SPrike Liang AMD_CG_SUPPORT_JPEG_MGCG | 893*f05f4fe6SPrike Liang AMD_CG_SUPPORT_SDMA_MGCG; 89454f4f6f3SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 895948b1216SAaron Liu AMD_PG_SUPPORT_VCN | 896948b1216SAaron Liu AMD_PG_SUPPORT_VCN_DPG | 897948b1216SAaron Liu AMD_PG_SUPPORT_JPEG; 898e97c8d86SAaron Liu if (adev->pdev->device == 0x1681) 8995efacdf0SAaron Liu adev->external_rev_id = 0x20; 900e97c8d86SAaron Liu else 901e7990721SAaron Liu adev->external_rev_id = adev->rev_id + 0x01; 902e7990721SAaron Liu break; 9033e67f4f2SAlex Deucher case IP_VERSION(10, 1, 3): 904f9ed188dSLang Yu case IP_VERSION(10, 1, 4): 905b515937bSTao Zhou adev->cg_flags = 0; 906b515937bSTao Zhou adev->pg_flags = 0; 907b515937bSTao Zhou adev->external_rev_id = adev->rev_id + 0x82; 908b515937bSTao Zhou break; 9091957f27dSYifan Zhang case IP_VERSION(10, 3, 6): 91050e14a62SYifan Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 91150e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_MGLS | 91250e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_CGCG | 91350e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_CGLS | 91450e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_3D_CGCG | 91550e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_3D_CGLS | 91650e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_RLC_LS | 91750e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_CP_LS | 91850e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_FGCG | 91950e14a62SYifan Zhang AMD_CG_SUPPORT_MC_MGCG | 92050e14a62SYifan Zhang AMD_CG_SUPPORT_MC_LS | 92150e14a62SYifan Zhang AMD_CG_SUPPORT_SDMA_LS | 92250e14a62SYifan Zhang AMD_CG_SUPPORT_HDP_MGCG | 92350e14a62SYifan Zhang AMD_CG_SUPPORT_HDP_LS | 92450e14a62SYifan Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 92550e14a62SYifan Zhang AMD_CG_SUPPORT_ATHUB_LS | 92687b5e77fSBoyuan Zhang AMD_CG_SUPPORT_IH_CG | 92787b5e77fSBoyuan Zhang AMD_CG_SUPPORT_VCN_MGCG | 92887b5e77fSBoyuan Zhang AMD_CG_SUPPORT_JPEG_MGCG; 92987b5e77fSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 93087b5e77fSBoyuan Zhang AMD_PG_SUPPORT_VCN | 93187b5e77fSBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 93287b5e77fSBoyuan Zhang AMD_PG_SUPPORT_JPEG; 9331957f27dSYifan Zhang adev->external_rev_id = adev->rev_id + 0x01; 9341957f27dSYifan Zhang break; 935b67f00e0SPrike Liang case IP_VERSION(10, 3, 7): 9369e148e8cSPrike Liang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 9379e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_MGLS | 9389e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_CGCG | 9399e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_CGLS | 9409e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_3D_CGCG | 9419e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_3D_CGLS | 9429e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_RLC_LS | 9439e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_CP_LS | 9449a1358bbSPrike Liang AMD_CG_SUPPORT_GFX_FGCG | 9459a1358bbSPrike Liang AMD_CG_SUPPORT_MC_MGCG | 9469a1358bbSPrike Liang AMD_CG_SUPPORT_MC_LS | 9479a1358bbSPrike Liang AMD_CG_SUPPORT_SDMA_LS | 9489a1358bbSPrike Liang AMD_CG_SUPPORT_HDP_MGCG | 9499a1358bbSPrike Liang AMD_CG_SUPPORT_HDP_LS | 9509a1358bbSPrike Liang AMD_CG_SUPPORT_ATHUB_MGCG | 9519a1358bbSPrike Liang AMD_CG_SUPPORT_ATHUB_LS | 9529a1358bbSPrike Liang AMD_CG_SUPPORT_IH_CG | 9539a1358bbSPrike Liang AMD_CG_SUPPORT_VCN_MGCG | 954*f05f4fe6SPrike Liang AMD_CG_SUPPORT_JPEG_MGCG | 955*f05f4fe6SPrike Liang AMD_CG_SUPPORT_SDMA_MGCG; 95635c27d95SSathishkumar S adev->pg_flags = AMD_PG_SUPPORT_VCN | 95735c27d95SSathishkumar S AMD_PG_SUPPORT_VCN_DPG | 958fabe1753SPrike Liang AMD_PG_SUPPORT_JPEG | 959fabe1753SPrike Liang AMD_PG_SUPPORT_GFX_PG; 960b67f00e0SPrike Liang adev->external_rev_id = adev->rev_id + 0x01; 961b67f00e0SPrike Liang break; 962c6b6a421SHawking Zhang default: 963c6b6a421SHawking Zhang /* FIXME: not supported yet */ 964c6b6a421SHawking Zhang return -EINVAL; 965c6b6a421SHawking Zhang } 966c6b6a421SHawking Zhang 9677bd939d0SLikun GAO if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 9687bd939d0SLikun GAO adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 9697bd939d0SLikun GAO AMD_PG_SUPPORT_VCN_DPG | 9707bd939d0SLikun GAO AMD_PG_SUPPORT_JPEG); 9717bd939d0SLikun GAO 972b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 973b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 974b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 975b05b6903SJiange Zhao } 976b05b6903SJiange Zhao 977c6b6a421SHawking Zhang return 0; 978c6b6a421SHawking Zhang } 979c6b6a421SHawking Zhang 980c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 981c6b6a421SHawking Zhang { 982b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 983b05b6903SJiange Zhao 984ed9d2053SBokun Zhang if (amdgpu_sriov_vf(adev)) { 985b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 98638433412SAlex Deucher if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 987ed9d2053SBokun Zhang amdgpu_virt_update_sriov_video_codec(adev, 98838433412SAlex Deucher sriov_sc_video_codecs_encode_array, 98938433412SAlex Deucher ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 99038433412SAlex Deucher sriov_sc_video_codecs_decode_array_vcn1, 99138433412SAlex Deucher ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1)); 99238433412SAlex Deucher } else { 99338433412SAlex Deucher amdgpu_virt_update_sriov_video_codec(adev, 99438433412SAlex Deucher sriov_sc_video_codecs_encode_array, 99538433412SAlex Deucher ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 99684b31d48SAlex Deucher sriov_sc_video_codecs_decode_array_vcn0, 99784b31d48SAlex Deucher ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0)); 99838433412SAlex Deucher } 999ed9d2053SBokun Zhang } 1000b05b6903SJiange Zhao 10011c312e81SShane Xiao /* Enable selfring doorbell aperture late because doorbell BAR 10021c312e81SShane Xiao * aperture will change if resize BAR successfully in gmc sw_init. 10031c312e81SShane Xiao */ 10041c312e81SShane Xiao adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 10051c312e81SShane Xiao 1006c6b6a421SHawking Zhang return 0; 1007c6b6a421SHawking Zhang } 1008c6b6a421SHawking Zhang 1009c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 1010c6b6a421SHawking Zhang { 1011b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1012b05b6903SJiange Zhao 1013b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 1014b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 1015b05b6903SJiange Zhao 1016c6b6a421SHawking Zhang return 0; 1017c6b6a421SHawking Zhang } 1018c6b6a421SHawking Zhang 1019c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 1020c6b6a421SHawking Zhang { 1021c6b6a421SHawking Zhang return 0; 1022c6b6a421SHawking Zhang } 1023c6b6a421SHawking Zhang 1024c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 1025c6b6a421SHawking Zhang { 1026c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1027c6b6a421SHawking Zhang 10285a5da8aeSEvan Quan if (adev->nbio.funcs->apply_lc_spc_mode_wa) 10295a5da8aeSEvan Quan adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 10305a5da8aeSEvan Quan 1031adcf949eSEvan Quan if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1032adcf949eSEvan Quan adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1033adcf949eSEvan Quan 1034c6b6a421SHawking Zhang /* enable aspm */ 1035c6b6a421SHawking Zhang nv_program_aspm(adev); 1036c6b6a421SHawking Zhang /* setup nbio registers */ 1037bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 1038923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 1039923c087aSYong Zhao * for the purpose of expose those registers 1040923c087aSYong Zhao * to process space 1041923c087aSYong Zhao */ 1042d3a21f7eSFelix Kuehling if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1043923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 1044c6b6a421SHawking Zhang /* enable the doorbell aperture */ 10451c312e81SShane Xiao adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1046c6b6a421SHawking Zhang 1047c6b6a421SHawking Zhang return 0; 1048c6b6a421SHawking Zhang } 1049c6b6a421SHawking Zhang 1050c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 1051c6b6a421SHawking Zhang { 1052c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1053c6b6a421SHawking Zhang 10541c312e81SShane Xiao /* Disable the doorbell aperture and selfring doorbell aperture 10551c312e81SShane Xiao * separately in hw_fini because nv_enable_doorbell_aperture 10561c312e81SShane Xiao * has been removed and there is no need to delay disabling 10571c312e81SShane Xiao * selfring doorbell. 10581c312e81SShane Xiao */ 10591c312e81SShane Xiao adev->nbio.funcs->enable_doorbell_aperture(adev, false); 10601c312e81SShane Xiao adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1061c6b6a421SHawking Zhang 1062c6b6a421SHawking Zhang return 0; 1063c6b6a421SHawking Zhang } 1064c6b6a421SHawking Zhang 1065c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 1066c6b6a421SHawking Zhang { 1067c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1068c6b6a421SHawking Zhang 1069c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 1070c6b6a421SHawking Zhang } 1071c6b6a421SHawking Zhang 1072c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 1073c6b6a421SHawking Zhang { 1074c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1075c6b6a421SHawking Zhang 1076c6b6a421SHawking Zhang return nv_common_hw_init(adev); 1077c6b6a421SHawking Zhang } 1078c6b6a421SHawking Zhang 1079c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 1080c6b6a421SHawking Zhang { 1081c6b6a421SHawking Zhang return true; 1082c6b6a421SHawking Zhang } 1083c6b6a421SHawking Zhang 1084c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 1085c6b6a421SHawking Zhang { 1086c6b6a421SHawking Zhang return 0; 1087c6b6a421SHawking Zhang } 1088c6b6a421SHawking Zhang 1089c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 1090c6b6a421SHawking Zhang { 1091c6b6a421SHawking Zhang return 0; 1092c6b6a421SHawking Zhang } 1093c6b6a421SHawking Zhang 1094c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1095c6b6a421SHawking Zhang enum amd_clockgating_state state) 1096c6b6a421SHawking Zhang { 1097c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1098c6b6a421SHawking Zhang 1099c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1100c6b6a421SHawking Zhang return 0; 1101c6b6a421SHawking Zhang 11021d789535SAlex Deucher switch (adev->ip_versions[NBIO_HWIP][0]) { 11033e67f4f2SAlex Deucher case IP_VERSION(2, 3, 0): 11043e67f4f2SAlex Deucher case IP_VERSION(2, 3, 1): 11053e67f4f2SAlex Deucher case IP_VERSION(2, 3, 2): 11063e67f4f2SAlex Deucher case IP_VERSION(3, 3, 0): 11073e67f4f2SAlex Deucher case IP_VERSION(3, 3, 1): 11083e67f4f2SAlex Deucher case IP_VERSION(3, 3, 2): 11093e67f4f2SAlex Deucher case IP_VERSION(3, 3, 3): 1110bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1111a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1112bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1113a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1114bf087285SLikun Gao adev->hdp.funcs->update_clock_gating(adev, 1115a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 11161001f2a1SLikun Gao adev->smuio.funcs->update_rom_clock_gating(adev, 11171001f2a1SLikun Gao state == AMD_CG_STATE_GATE); 1118c6b6a421SHawking Zhang break; 1119c6b6a421SHawking Zhang default: 1120c6b6a421SHawking Zhang break; 1121c6b6a421SHawking Zhang } 1122c6b6a421SHawking Zhang return 0; 1123c6b6a421SHawking Zhang } 1124c6b6a421SHawking Zhang 1125c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1126c6b6a421SHawking Zhang enum amd_powergating_state state) 1127c6b6a421SHawking Zhang { 1128c6b6a421SHawking Zhang /* TODO */ 1129c6b6a421SHawking Zhang return 0; 1130c6b6a421SHawking Zhang } 1131c6b6a421SHawking Zhang 113225faeddcSEvan Quan static void nv_common_get_clockgating_state(void *handle, u64 *flags) 1133c6b6a421SHawking Zhang { 1134c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1135c6b6a421SHawking Zhang 1136c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1137c6b6a421SHawking Zhang *flags = 0; 1138c6b6a421SHawking Zhang 1139bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1140c6b6a421SHawking Zhang 1141bf087285SLikun Gao adev->hdp.funcs->get_clock_gating_state(adev, flags); 1142c6b6a421SHawking Zhang 11431001f2a1SLikun Gao adev->smuio.funcs->get_clock_gating_state(adev, flags); 11441001f2a1SLikun Gao 1145c6b6a421SHawking Zhang return; 1146c6b6a421SHawking Zhang } 1147c6b6a421SHawking Zhang 1148c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1149c6b6a421SHawking Zhang .name = "nv_common", 1150c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1151c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1152c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1153c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1154c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1155c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1156c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1157c6b6a421SHawking Zhang .resume = nv_common_resume, 1158c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1159c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1160c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1161c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1162c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1163c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1164c6b6a421SHawking Zhang }; 1165