1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 286f786950SAlex Deucher #include <drm/amdgpu_drm.h> 296f786950SAlex Deucher 30c6b6a421SHawking Zhang #include "amdgpu.h" 31c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 32c6b6a421SHawking Zhang #include "amdgpu_ih.h" 33c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 34c6b6a421SHawking Zhang #include "amdgpu_vce.h" 35c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 36c6b6a421SHawking Zhang #include "amdgpu_psp.h" 37c6b6a421SHawking Zhang #include "atom.h" 38c6b6a421SHawking Zhang #include "amd_pcie.h" 39c6b6a421SHawking Zhang 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 41c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 423967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 43c6b6a421SHawking Zhang 44c6b6a421SHawking Zhang #include "soc15.h" 45c6b6a421SHawking Zhang #include "soc15_common.h" 46c6b6a421SHawking Zhang #include "gmc_v10_0.h" 47c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 48c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 49bebc0762SHawking Zhang #include "nbio_v2_3.h" 50a7e91bd7SHuang Rui #include "nbio_v7_2.h" 51bf087285SLikun Gao #include "hdp_v5_0.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59b8f10585SLeo Liu #include "vcn_v3_0.h" 604d72dd12SLeo Liu #include "jpeg_v3_0.h" 61c6b6a421SHawking Zhang #include "dce_virtual.h" 62c6b6a421SHawking Zhang #include "mes_v10_1.h" 63b05b6903SJiange Zhao #include "mxgpu_nv.h" 640bf7f2dcSLikun Gao #include "smuio_v11_0.h" 650bf7f2dcSLikun Gao #include "smuio_v11_0_6.h" 66c6b6a421SHawking Zhang 67c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 68c6b6a421SHawking Zhang 693b246e8bSAlex Deucher /* Navi */ 703b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 713b246e8bSAlex Deucher { 723b246e8bSAlex Deucher { 736f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 743b246e8bSAlex Deucher .max_width = 4096, 753b246e8bSAlex Deucher .max_height = 2304, 763b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 2304, 773b246e8bSAlex Deucher .max_level = 0, 783b246e8bSAlex Deucher }, 793b246e8bSAlex Deucher { 806f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 813b246e8bSAlex Deucher .max_width = 4096, 823b246e8bSAlex Deucher .max_height = 2304, 833b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 2304, 843b246e8bSAlex Deucher .max_level = 0, 853b246e8bSAlex Deucher }, 863b246e8bSAlex Deucher }; 873b246e8bSAlex Deucher 883b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_encode = 893b246e8bSAlex Deucher { 903b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 913b246e8bSAlex Deucher .codec_array = nv_video_codecs_encode_array, 923b246e8bSAlex Deucher }; 933b246e8bSAlex Deucher 943b246e8bSAlex Deucher /* Navi1x */ 953b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 963b246e8bSAlex Deucher { 973b246e8bSAlex Deucher { 986f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 993b246e8bSAlex Deucher .max_width = 4096, 1003b246e8bSAlex Deucher .max_height = 4096, 1013b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1023b246e8bSAlex Deucher .max_level = 3, 1033b246e8bSAlex Deucher }, 1043b246e8bSAlex Deucher { 1056f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1063b246e8bSAlex Deucher .max_width = 4096, 1073b246e8bSAlex Deucher .max_height = 4096, 1083b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1093b246e8bSAlex Deucher .max_level = 5, 1103b246e8bSAlex Deucher }, 1113b246e8bSAlex Deucher { 1126f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 1133b246e8bSAlex Deucher .max_width = 4096, 1143b246e8bSAlex Deucher .max_height = 4096, 1153b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1163b246e8bSAlex Deucher .max_level = 52, 1173b246e8bSAlex Deucher }, 1183b246e8bSAlex Deucher { 1196f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1203b246e8bSAlex Deucher .max_width = 4096, 1213b246e8bSAlex Deucher .max_height = 4096, 1223b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1233b246e8bSAlex Deucher .max_level = 4, 1243b246e8bSAlex Deucher }, 1253b246e8bSAlex Deucher { 1266f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 1273b246e8bSAlex Deucher .max_width = 8192, 1283b246e8bSAlex Deucher .max_height = 4352, 1293b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 1303b246e8bSAlex Deucher .max_level = 186, 1313b246e8bSAlex Deucher }, 1323b246e8bSAlex Deucher { 1336f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 1343b246e8bSAlex Deucher .max_width = 4096, 1353b246e8bSAlex Deucher .max_height = 4096, 1363b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1373b246e8bSAlex Deucher .max_level = 0, 1383b246e8bSAlex Deucher }, 1393b246e8bSAlex Deucher { 1406f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 1413b246e8bSAlex Deucher .max_width = 8192, 1423b246e8bSAlex Deucher .max_height = 4352, 1433b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 1443b246e8bSAlex Deucher .max_level = 0, 1453b246e8bSAlex Deucher }, 1463b246e8bSAlex Deucher }; 1473b246e8bSAlex Deucher 1483b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_decode = 1493b246e8bSAlex Deucher { 1503b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 1513b246e8bSAlex Deucher .codec_array = nv_video_codecs_decode_array, 1523b246e8bSAlex Deucher }; 1533b246e8bSAlex Deucher 1543b246e8bSAlex Deucher /* Sienna Cichlid */ 1553b246e8bSAlex Deucher static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 1563b246e8bSAlex Deucher { 1573b246e8bSAlex Deucher { 1586f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1593b246e8bSAlex Deucher .max_width = 4096, 1603b246e8bSAlex Deucher .max_height = 4096, 1613b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1623b246e8bSAlex Deucher .max_level = 3, 1633b246e8bSAlex Deucher }, 1643b246e8bSAlex Deucher { 1656f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1663b246e8bSAlex Deucher .max_width = 4096, 1673b246e8bSAlex Deucher .max_height = 4096, 1683b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1693b246e8bSAlex Deucher .max_level = 5, 1703b246e8bSAlex Deucher }, 1713b246e8bSAlex Deucher { 1726f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 1733b246e8bSAlex Deucher .max_width = 4096, 1743b246e8bSAlex Deucher .max_height = 4096, 1753b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1763b246e8bSAlex Deucher .max_level = 52, 1773b246e8bSAlex Deucher }, 1783b246e8bSAlex Deucher { 1796f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1803b246e8bSAlex Deucher .max_width = 4096, 1813b246e8bSAlex Deucher .max_height = 4096, 1823b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1833b246e8bSAlex Deucher .max_level = 4, 1843b246e8bSAlex Deucher }, 1853b246e8bSAlex Deucher { 1866f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 1873b246e8bSAlex Deucher .max_width = 8192, 1883b246e8bSAlex Deucher .max_height = 4352, 1893b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 1903b246e8bSAlex Deucher .max_level = 186, 1913b246e8bSAlex Deucher }, 1923b246e8bSAlex Deucher { 1936f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 1943b246e8bSAlex Deucher .max_width = 4096, 1953b246e8bSAlex Deucher .max_height = 4096, 1963b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1973b246e8bSAlex Deucher .max_level = 0, 1983b246e8bSAlex Deucher }, 1993b246e8bSAlex Deucher { 2006f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 2013b246e8bSAlex Deucher .max_width = 8192, 2023b246e8bSAlex Deucher .max_height = 4352, 2033b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 2043b246e8bSAlex Deucher .max_level = 0, 2053b246e8bSAlex Deucher }, 2063b246e8bSAlex Deucher { 2076f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 2083b246e8bSAlex Deucher .max_width = 8192, 2093b246e8bSAlex Deucher .max_height = 4352, 2103b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 2113b246e8bSAlex Deucher .max_level = 0, 2123b246e8bSAlex Deucher }, 2133b246e8bSAlex Deucher }; 2143b246e8bSAlex Deucher 2153b246e8bSAlex Deucher static const struct amdgpu_video_codecs sc_video_codecs_decode = 2163b246e8bSAlex Deucher { 2173b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 2183b246e8bSAlex Deucher .codec_array = sc_video_codecs_decode_array, 2193b246e8bSAlex Deucher }; 2203b246e8bSAlex Deucher 221ed9d2053SBokun Zhang /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 222ed9d2053SBokun Zhang static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 223ed9d2053SBokun Zhang { 224ed9d2053SBokun Zhang { 225ed9d2053SBokun Zhang .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 226ed9d2053SBokun Zhang .max_width = 4096, 227ed9d2053SBokun Zhang .max_height = 2304, 228ed9d2053SBokun Zhang .max_pixels_per_frame = 4096 * 2304, 229ed9d2053SBokun Zhang .max_level = 0, 230ed9d2053SBokun Zhang }, 231ed9d2053SBokun Zhang { 232ed9d2053SBokun Zhang .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 233ed9d2053SBokun Zhang .max_width = 4096, 234ed9d2053SBokun Zhang .max_height = 2304, 235ed9d2053SBokun Zhang .max_pixels_per_frame = 4096 * 2304, 236ed9d2053SBokun Zhang .max_level = 0, 237ed9d2053SBokun Zhang }, 238ed9d2053SBokun Zhang }; 239ed9d2053SBokun Zhang 240ed9d2053SBokun Zhang static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = 241ed9d2053SBokun Zhang { 242ed9d2053SBokun Zhang { 243ed9d2053SBokun Zhang .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 244ed9d2053SBokun Zhang .max_width = 4096, 245ed9d2053SBokun Zhang .max_height = 4096, 246ed9d2053SBokun Zhang .max_pixels_per_frame = 4096 * 4096, 247ed9d2053SBokun Zhang .max_level = 3, 248ed9d2053SBokun Zhang }, 249ed9d2053SBokun Zhang { 250ed9d2053SBokun Zhang .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 251ed9d2053SBokun Zhang .max_width = 4096, 252ed9d2053SBokun Zhang .max_height = 4096, 253ed9d2053SBokun Zhang .max_pixels_per_frame = 4096 * 4096, 254ed9d2053SBokun Zhang .max_level = 5, 255ed9d2053SBokun Zhang }, 256ed9d2053SBokun Zhang { 257ed9d2053SBokun Zhang .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 258ed9d2053SBokun Zhang .max_width = 4096, 259ed9d2053SBokun Zhang .max_height = 4096, 260ed9d2053SBokun Zhang .max_pixels_per_frame = 4096 * 4096, 261ed9d2053SBokun Zhang .max_level = 52, 262ed9d2053SBokun Zhang }, 263ed9d2053SBokun Zhang { 264ed9d2053SBokun Zhang .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 265ed9d2053SBokun Zhang .max_width = 4096, 266ed9d2053SBokun Zhang .max_height = 4096, 267ed9d2053SBokun Zhang .max_pixels_per_frame = 4096 * 4096, 268ed9d2053SBokun Zhang .max_level = 4, 269ed9d2053SBokun Zhang }, 270ed9d2053SBokun Zhang { 271ed9d2053SBokun Zhang .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 272ed9d2053SBokun Zhang .max_width = 8192, 273ed9d2053SBokun Zhang .max_height = 4352, 274ed9d2053SBokun Zhang .max_pixels_per_frame = 8192 * 4352, 275ed9d2053SBokun Zhang .max_level = 186, 276ed9d2053SBokun Zhang }, 277ed9d2053SBokun Zhang { 278ed9d2053SBokun Zhang .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 279ed9d2053SBokun Zhang .max_width = 4096, 280ed9d2053SBokun Zhang .max_height = 4096, 281ed9d2053SBokun Zhang .max_pixels_per_frame = 4096 * 4096, 282ed9d2053SBokun Zhang .max_level = 0, 283ed9d2053SBokun Zhang }, 284ed9d2053SBokun Zhang { 285ed9d2053SBokun Zhang .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 286ed9d2053SBokun Zhang .max_width = 8192, 287ed9d2053SBokun Zhang .max_height = 4352, 288ed9d2053SBokun Zhang .max_pixels_per_frame = 8192 * 4352, 289ed9d2053SBokun Zhang .max_level = 0, 290ed9d2053SBokun Zhang }, 291ed9d2053SBokun Zhang { 292ed9d2053SBokun Zhang .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 293ed9d2053SBokun Zhang .max_width = 8192, 294ed9d2053SBokun Zhang .max_height = 4352, 295ed9d2053SBokun Zhang .max_pixels_per_frame = 8192 * 4352, 296ed9d2053SBokun Zhang .max_level = 0, 297ed9d2053SBokun Zhang }, 298ed9d2053SBokun Zhang }; 299ed9d2053SBokun Zhang 300ed9d2053SBokun Zhang static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 301ed9d2053SBokun Zhang { 302ed9d2053SBokun Zhang .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 303ed9d2053SBokun Zhang .codec_array = sriov_sc_video_codecs_encode_array, 304ed9d2053SBokun Zhang }; 305ed9d2053SBokun Zhang 306ed9d2053SBokun Zhang static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = 307ed9d2053SBokun Zhang { 308ed9d2053SBokun Zhang .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), 309ed9d2053SBokun Zhang .codec_array = sriov_sc_video_codecs_decode_array, 310ed9d2053SBokun Zhang }; 311ed9d2053SBokun Zhang 3123b246e8bSAlex Deucher static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 3133b246e8bSAlex Deucher const struct amdgpu_video_codecs **codecs) 3143b246e8bSAlex Deucher { 3153b246e8bSAlex Deucher switch (adev->asic_type) { 3163b246e8bSAlex Deucher case CHIP_SIENNA_CICHLID: 317ed9d2053SBokun Zhang if (amdgpu_sriov_vf(adev)) { 318ed9d2053SBokun Zhang if (encode) 319ed9d2053SBokun Zhang *codecs = &sriov_sc_video_codecs_encode; 320ed9d2053SBokun Zhang else 321ed9d2053SBokun Zhang *codecs = &sriov_sc_video_codecs_decode; 322ed9d2053SBokun Zhang } else { 323ed9d2053SBokun Zhang if (encode) 324ed9d2053SBokun Zhang *codecs = &nv_video_codecs_encode; 325ed9d2053SBokun Zhang else 326ed9d2053SBokun Zhang *codecs = &sc_video_codecs_decode; 327ed9d2053SBokun Zhang } 328ed9d2053SBokun Zhang return 0; 3293b246e8bSAlex Deucher case CHIP_NAVY_FLOUNDER: 3303b246e8bSAlex Deucher case CHIP_DIMGREY_CAVEFISH: 3313b246e8bSAlex Deucher case CHIP_VANGOGH: 3323b246e8bSAlex Deucher if (encode) 3333b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 3343b246e8bSAlex Deucher else 3353b246e8bSAlex Deucher *codecs = &sc_video_codecs_decode; 3363b246e8bSAlex Deucher return 0; 3373b246e8bSAlex Deucher case CHIP_NAVI10: 3383b246e8bSAlex Deucher case CHIP_NAVI14: 3393b246e8bSAlex Deucher case CHIP_NAVI12: 3403b246e8bSAlex Deucher if (encode) 3413b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 3423b246e8bSAlex Deucher else 3433b246e8bSAlex Deucher *codecs = &nv_video_codecs_decode; 3443b246e8bSAlex Deucher return 0; 3453b246e8bSAlex Deucher default: 3463b246e8bSAlex Deucher return -EINVAL; 3473b246e8bSAlex Deucher } 3483b246e8bSAlex Deucher } 3493b246e8bSAlex Deucher 350c6b6a421SHawking Zhang /* 351c6b6a421SHawking Zhang * Indirect registers accessor 352c6b6a421SHawking Zhang */ 353c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 354c6b6a421SHawking Zhang { 355705a2b5bSHawking Zhang unsigned long address, data; 356bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 357bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 358c6b6a421SHawking Zhang 359705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg(adev, address, data, reg); 360c6b6a421SHawking Zhang } 361c6b6a421SHawking Zhang 362c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 363c6b6a421SHawking Zhang { 364705a2b5bSHawking Zhang unsigned long address, data; 365c6b6a421SHawking Zhang 366bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 367bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 368c6b6a421SHawking Zhang 369705a2b5bSHawking Zhang amdgpu_device_indirect_wreg(adev, address, data, reg, v); 370c6b6a421SHawking Zhang } 371c6b6a421SHawking Zhang 3724922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 3734922f1bcSJohn Clements { 374705a2b5bSHawking Zhang unsigned long address, data; 3754922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 3764922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 3774922f1bcSJohn Clements 378705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg64(adev, address, data, reg); 3794922f1bcSJohn Clements } 3804922f1bcSJohn Clements 3815de54343SHuang Rui static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 3825de54343SHuang Rui { 3835de54343SHuang Rui unsigned long flags, address, data; 3845de54343SHuang Rui u32 r; 3855de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 3865de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 3875de54343SHuang Rui 3885de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 3895de54343SHuang Rui WREG32(address, reg * 4); 3905de54343SHuang Rui (void)RREG32(address); 3915de54343SHuang Rui r = RREG32(data); 3925de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 3935de54343SHuang Rui return r; 3945de54343SHuang Rui } 3955de54343SHuang Rui 3964922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 3974922f1bcSJohn Clements { 398705a2b5bSHawking Zhang unsigned long address, data; 3994922f1bcSJohn Clements 4004922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 4014922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 4024922f1bcSJohn Clements 403705a2b5bSHawking Zhang amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 4044922f1bcSJohn Clements } 4054922f1bcSJohn Clements 4065de54343SHuang Rui static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 4075de54343SHuang Rui { 4085de54343SHuang Rui unsigned long flags, address, data; 4095de54343SHuang Rui 4105de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 4115de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 4125de54343SHuang Rui 4135de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 4145de54343SHuang Rui WREG32(address, reg * 4); 4155de54343SHuang Rui (void)RREG32(address); 4165de54343SHuang Rui WREG32(data, v); 4175de54343SHuang Rui (void)RREG32(data); 4185de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 4195de54343SHuang Rui } 4205de54343SHuang Rui 421c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 422c6b6a421SHawking Zhang { 423c6b6a421SHawking Zhang unsigned long flags, address, data; 424c6b6a421SHawking Zhang u32 r; 425c6b6a421SHawking Zhang 426c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 427c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 428c6b6a421SHawking Zhang 429c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 430c6b6a421SHawking Zhang WREG32(address, (reg)); 431c6b6a421SHawking Zhang r = RREG32(data); 432c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 433c6b6a421SHawking Zhang return r; 434c6b6a421SHawking Zhang } 435c6b6a421SHawking Zhang 436c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 437c6b6a421SHawking Zhang { 438c6b6a421SHawking Zhang unsigned long flags, address, data; 439c6b6a421SHawking Zhang 440c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 441c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 442c6b6a421SHawking Zhang 443c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 444c6b6a421SHawking Zhang WREG32(address, (reg)); 445c6b6a421SHawking Zhang WREG32(data, (v)); 446c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 447c6b6a421SHawking Zhang } 448c6b6a421SHawking Zhang 449c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 450c6b6a421SHawking Zhang { 451bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 452c6b6a421SHawking Zhang } 453c6b6a421SHawking Zhang 454c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 455c6b6a421SHawking Zhang { 456462a70d8STao Zhou return adev->clock.spll.reference_freq; 457c6b6a421SHawking Zhang } 458c6b6a421SHawking Zhang 459c6b6a421SHawking Zhang 460c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 461c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 462c6b6a421SHawking Zhang { 463c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 464c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 465c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 466c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 467c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 468c6b6a421SHawking Zhang 469c6b6a421SHawking Zhang WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 470c6b6a421SHawking Zhang } 471c6b6a421SHawking Zhang 472c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 473c6b6a421SHawking Zhang { 474c6b6a421SHawking Zhang /* todo */ 475c6b6a421SHawking Zhang } 476c6b6a421SHawking Zhang 477c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 478c6b6a421SHawking Zhang { 479c6b6a421SHawking Zhang /* todo */ 480c6b6a421SHawking Zhang return false; 481c6b6a421SHawking Zhang } 482c6b6a421SHawking Zhang 483c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 484c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 485c6b6a421SHawking Zhang { 48629bc37b4SAlex Deucher u32 *dw_ptr; 48729bc37b4SAlex Deucher u32 i, length_dw; 4880bf7f2dcSLikun Gao u32 rom_index_offset, rom_data_offset; 48929bc37b4SAlex Deucher 49029bc37b4SAlex Deucher if (bios == NULL) 491c6b6a421SHawking Zhang return false; 49229bc37b4SAlex Deucher if (length_bytes == 0) 49329bc37b4SAlex Deucher return false; 49429bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 49529bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 49629bc37b4SAlex Deucher return false; 49729bc37b4SAlex Deucher 49829bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 49929bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 50029bc37b4SAlex Deucher 5010bf7f2dcSLikun Gao rom_index_offset = 5020bf7f2dcSLikun Gao adev->smuio.funcs->get_rom_index_offset(adev); 5030bf7f2dcSLikun Gao rom_data_offset = 5040bf7f2dcSLikun Gao adev->smuio.funcs->get_rom_data_offset(adev); 5050bf7f2dcSLikun Gao 50629bc37b4SAlex Deucher /* set rom index to 0 */ 5070bf7f2dcSLikun Gao WREG32(rom_index_offset, 0); 50829bc37b4SAlex Deucher /* read out the rom data */ 50929bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 5100bf7f2dcSLikun Gao dw_ptr[i] = RREG32(rom_data_offset); 51129bc37b4SAlex Deucher 51229bc37b4SAlex Deucher return true; 513c6b6a421SHawking Zhang } 514c6b6a421SHawking Zhang 515c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 516c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 517c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 518c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 519c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 520c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 521c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 522c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 523c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 524c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 525c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 526c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 527c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 528c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 529c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 530c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 531664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 532c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 533c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 534c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 535c6b6a421SHawking Zhang }; 536c6b6a421SHawking Zhang 537c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 538c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 539c6b6a421SHawking Zhang { 540c6b6a421SHawking Zhang uint32_t val; 541c6b6a421SHawking Zhang 542c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 543c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 544c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 545c6b6a421SHawking Zhang 546c6b6a421SHawking Zhang val = RREG32(reg_offset); 547c6b6a421SHawking Zhang 548c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 549c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 550c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 551c6b6a421SHawking Zhang return val; 552c6b6a421SHawking Zhang } 553c6b6a421SHawking Zhang 554c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 555c6b6a421SHawking Zhang bool indexed, u32 se_num, 556c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 557c6b6a421SHawking Zhang { 558c6b6a421SHawking Zhang if (indexed) { 559c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 560c6b6a421SHawking Zhang } else { 561c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 562c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 563c6b6a421SHawking Zhang return RREG32(reg_offset); 564c6b6a421SHawking Zhang } 565c6b6a421SHawking Zhang } 566c6b6a421SHawking Zhang 567c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 568c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 569c6b6a421SHawking Zhang { 570c6b6a421SHawking Zhang uint32_t i; 571c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 572c6b6a421SHawking Zhang 573c6b6a421SHawking Zhang *value = 0; 574c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 575c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 576fced3c3aSHuang Rui if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 577fced3c3aSHuang Rui reg_offset != 578c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 579c6b6a421SHawking Zhang continue; 580c6b6a421SHawking Zhang 581c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 582c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 583c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 584c6b6a421SHawking Zhang return 0; 585c6b6a421SHawking Zhang } 586c6b6a421SHawking Zhang return -EINVAL; 587c6b6a421SHawking Zhang } 588c6b6a421SHawking Zhang 589b913ec62SAlex Deucher static int nv_asic_mode2_reset(struct amdgpu_device *adev) 590b913ec62SAlex Deucher { 591b913ec62SAlex Deucher u32 i; 592b913ec62SAlex Deucher int ret = 0; 593b913ec62SAlex Deucher 594b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, true); 595b913ec62SAlex Deucher 596b913ec62SAlex Deucher /* disable BM */ 597b913ec62SAlex Deucher pci_clear_master(adev->pdev); 598b913ec62SAlex Deucher 599b913ec62SAlex Deucher amdgpu_device_cache_pci_state(adev->pdev); 600b913ec62SAlex Deucher 601b913ec62SAlex Deucher ret = amdgpu_dpm_mode2_reset(adev); 602b913ec62SAlex Deucher if (ret) 603b913ec62SAlex Deucher dev_err(adev->dev, "GPU mode2 reset failed\n"); 604b913ec62SAlex Deucher 605b913ec62SAlex Deucher amdgpu_device_load_pci_state(adev->pdev); 606b913ec62SAlex Deucher 607b913ec62SAlex Deucher /* wait for asic to come out of reset */ 608b913ec62SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 609b913ec62SAlex Deucher u32 memsize = adev->nbio.funcs->get_memsize(adev); 610b913ec62SAlex Deucher 611b913ec62SAlex Deucher if (memsize != 0xffffffff) 612b913ec62SAlex Deucher break; 613b913ec62SAlex Deucher udelay(1); 614b913ec62SAlex Deucher } 615b913ec62SAlex Deucher 616b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, false); 617b913ec62SAlex Deucher 618b913ec62SAlex Deucher return ret; 619b913ec62SAlex Deucher } 620b913ec62SAlex Deucher 6212ddc6c3eSAlex Deucher static enum amd_reset_method 6222ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 6232ddc6c3eSAlex Deucher { 624273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 62516086355SAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 626f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_BACO || 627f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_PCI) 628273da6ffSWenhui Sheng return amdgpu_reset_method; 629273da6ffSWenhui Sheng 630273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 631273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 632273da6ffSWenhui Sheng amdgpu_reset_method); 633273da6ffSWenhui Sheng 634ca6fd7a6SLikun Gao switch (adev->asic_type) { 63516086355SAlex Deucher case CHIP_VANGOGH: 63616086355SAlex Deucher return AMD_RESET_METHOD_MODE2; 637ca6fd7a6SLikun Gao case CHIP_SIENNA_CICHLID: 63822dd44f4SJiansong Chen case CHIP_NAVY_FLOUNDER: 63915ed44c0STao Zhou case CHIP_DIMGREY_CAVEFISH: 6405ed7715dSChengming Gui case CHIP_BEIGE_GOBY: 641ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 642ca6fd7a6SLikun Gao default: 643181e772fSEvan Quan if (amdgpu_dpm_is_baco_supported(adev)) 6442ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 6452ddc6c3eSAlex Deucher else 6462ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 6472ddc6c3eSAlex Deucher } 648ca6fd7a6SLikun Gao } 6492ddc6c3eSAlex Deucher 650c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 651c6b6a421SHawking Zhang { 652767acabdSKevin Wang int ret = 0; 653c6b6a421SHawking Zhang 65416086355SAlex Deucher switch (nv_asic_reset_method(adev)) { 655f172865aSAlex Deucher case AMD_RESET_METHOD_PCI: 656f172865aSAlex Deucher dev_info(adev->dev, "PCI reset\n"); 657f172865aSAlex Deucher ret = amdgpu_device_pci_reset(adev); 658f172865aSAlex Deucher break; 65916086355SAlex Deucher case AMD_RESET_METHOD_BACO: 66011043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 661181e772fSEvan Quan ret = amdgpu_dpm_baco_reset(adev); 66216086355SAlex Deucher break; 66316086355SAlex Deucher case AMD_RESET_METHOD_MODE2: 66416086355SAlex Deucher dev_info(adev->dev, "MODE2 reset\n"); 665b913ec62SAlex Deucher ret = nv_asic_mode2_reset(adev); 66616086355SAlex Deucher break; 66716086355SAlex Deucher default: 66811043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 6695c03e584SFeifei Xu ret = amdgpu_device_mode1_reset(adev); 67016086355SAlex Deucher break; 67111043b7aSAlex Deucher } 672767acabdSKevin Wang 673767acabdSKevin Wang return ret; 674c6b6a421SHawking Zhang } 675c6b6a421SHawking Zhang 676c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 677c6b6a421SHawking Zhang { 678c6b6a421SHawking Zhang /* todo */ 679c6b6a421SHawking Zhang return 0; 680c6b6a421SHawking Zhang } 681c6b6a421SHawking Zhang 682c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 683c6b6a421SHawking Zhang { 684c6b6a421SHawking Zhang /* todo */ 685c6b6a421SHawking Zhang return 0; 686c6b6a421SHawking Zhang } 687c6b6a421SHawking Zhang 688c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 689c6b6a421SHawking Zhang { 690c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 691c6b6a421SHawking Zhang return; 692c6b6a421SHawking Zhang 693c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 694c6b6a421SHawking Zhang return; 695c6b6a421SHawking Zhang 696c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 697c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 698c6b6a421SHawking Zhang return; 699c6b6a421SHawking Zhang 700c6b6a421SHawking Zhang /* todo */ 701c6b6a421SHawking Zhang } 702c6b6a421SHawking Zhang 703c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 704c6b6a421SHawking Zhang { 7050064b0ceSKenneth Feng if (!amdgpu_aspm) 706c6b6a421SHawking Zhang return; 707c6b6a421SHawking Zhang 7083273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 709e1edaeafSLikun Gao (adev->nbio.funcs->program_aspm)) 710e1edaeafSLikun Gao adev->nbio.funcs->program_aspm(adev); 711e1edaeafSLikun Gao 712c6b6a421SHawking Zhang } 713c6b6a421SHawking Zhang 714c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 715c6b6a421SHawking Zhang bool enable) 716c6b6a421SHawking Zhang { 717bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 718bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 719c6b6a421SHawking Zhang } 720c6b6a421SHawking Zhang 721c6b6a421SHawking Zhang static const struct amdgpu_ip_block_version nv_common_ip_block = 722c6b6a421SHawking Zhang { 723c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 724c6b6a421SHawking Zhang .major = 1, 725c6b6a421SHawking Zhang .minor = 0, 726c6b6a421SHawking Zhang .rev = 0, 727c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 728c6b6a421SHawking Zhang }; 729c6b6a421SHawking Zhang 73032358093SLikun Gao static bool nv_is_headless_sku(struct pci_dev *pdev) 73132358093SLikun Gao { 73232358093SLikun Gao if ((pdev->device == 0x731E && 73332358093SLikun Gao (pdev->revision == 0xC6 || pdev->revision == 0xC7)) || 73432358093SLikun Gao (pdev->device == 0x7340 && pdev->revision == 0xC9) || 73532358093SLikun Gao (pdev->device == 0x7360 && pdev->revision == 0xC7)) 73632358093SLikun Gao return true; 73732358093SLikun Gao return false; 73832358093SLikun Gao } 73932358093SLikun Gao 740b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 741c6b6a421SHawking Zhang { 742b5c73856SXiaojie Yuan int r; 743b5c73856SXiaojie Yuan 744b5c73856SXiaojie Yuan if (amdgpu_discovery) { 745b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 746b5c73856SXiaojie Yuan if (r) { 747b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 748b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 749b5c73856SXiaojie Yuan goto legacy_init; 750b5c73856SXiaojie Yuan } 751b5c73856SXiaojie Yuan 7527bd939d0SLikun GAO amdgpu_discovery_harvest_ip(adev); 75332358093SLikun Gao if (nv_is_headless_sku(adev->pdev)) { 75432358093SLikun Gao adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 75532358093SLikun Gao adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 75632358093SLikun Gao } 7577bd939d0SLikun GAO 758b5c73856SXiaojie Yuan return 0; 759b5c73856SXiaojie Yuan } 760b5c73856SXiaojie Yuan 761b5c73856SXiaojie Yuan legacy_init: 762c6b6a421SHawking Zhang switch (adev->asic_type) { 763c6b6a421SHawking Zhang case CHIP_NAVI10: 764c6b6a421SHawking Zhang navi10_reg_base_init(adev); 765c6b6a421SHawking Zhang break; 766a0f6d926SXiaojie Yuan case CHIP_NAVI14: 767a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 768a0f6d926SXiaojie Yuan break; 76903d0a073SXiaojie Yuan case CHIP_NAVI12: 77003d0a073SXiaojie Yuan navi12_reg_base_init(adev); 77103d0a073SXiaojie Yuan break; 772dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 773c8c959f6SJiansong Chen case CHIP_NAVY_FLOUNDER: 774dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 775dccdbf3fSLikun Gao break; 776026570e6SHuang Rui case CHIP_VANGOGH: 777026570e6SHuang Rui vangogh_reg_base_init(adev); 778026570e6SHuang Rui break; 779038d757bSTao Zhou case CHIP_DIMGREY_CAVEFISH: 780038d757bSTao Zhou dimgrey_cavefish_reg_base_init(adev); 781038d757bSTao Zhou break; 782fd5b4b44SChengming Gui case CHIP_BEIGE_GOBY: 783fd5b4b44SChengming Gui beige_goby_reg_base_init(adev); 784fd5b4b44SChengming Gui break; 785c6b6a421SHawking Zhang default: 786c6b6a421SHawking Zhang return -EINVAL; 787c6b6a421SHawking Zhang } 788c6b6a421SHawking Zhang 789b5c73856SXiaojie Yuan return 0; 790b5c73856SXiaojie Yuan } 791b5c73856SXiaojie Yuan 792c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 793c1299461SWenhui Sheng { 794c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 795c1299461SWenhui Sheng } 796c1299461SWenhui Sheng 797b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 798b5c73856SXiaojie Yuan { 799b5c73856SXiaojie Yuan int r; 800b5c73856SXiaojie Yuan 801a7e91bd7SHuang Rui if (adev->flags & AMD_IS_APU) { 802a7e91bd7SHuang Rui adev->nbio.funcs = &nbio_v7_2_funcs; 803a7e91bd7SHuang Rui adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 804a7e91bd7SHuang Rui } else { 805122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 806122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 807a7e91bd7SHuang Rui } 808bf087285SLikun Gao adev->hdp.funcs = &hdp_v5_0_funcs; 809122078deSMonk Liu 8100bf7f2dcSLikun Gao if (adev->asic_type >= CHIP_SIENNA_CICHLID) 8110bf7f2dcSLikun Gao adev->smuio.funcs = &smuio_v11_0_6_funcs; 8120bf7f2dcSLikun Gao else 8130bf7f2dcSLikun Gao adev->smuio.funcs = &smuio_v11_0_funcs; 8140bf7f2dcSLikun Gao 815c652923aSJohn Clements if (adev->asic_type == CHIP_SIENNA_CICHLID) 816c652923aSJohn Clements adev->gmc.xgmi.supported = true; 817c652923aSJohn Clements 818b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 819b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 820b5c73856SXiaojie Yuan if (r) 821b5c73856SXiaojie Yuan return r; 822b5c73856SXiaojie Yuan 823c6b6a421SHawking Zhang switch (adev->asic_type) { 824c6b6a421SHawking Zhang case CHIP_NAVI10: 825d1daf850SAlex Deucher case CHIP_NAVI14: 826c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 827c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 828c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 829c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 830c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 8319530273eSEvan Quan !amdgpu_sriov_vf(adev)) 832c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 833c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 834c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 835f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 8368301f6b9STianci.Yin else if (amdgpu_device_has_dc_support(adev)) 837b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 838f8a7976bSAlex Deucher #endif 839c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 840c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 841c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 8429530273eSEvan Quan !amdgpu_sriov_vf(adev)) 843c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 844c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 8455be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 846c6b6a421SHawking Zhang if (adev->enable_mes) 847c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 848c6b6a421SHawking Zhang break; 84944e9e7c9SXiaojie Yuan case CHIP_NAVI12: 85044e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 85144e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 85244e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 8536b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 85479bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 8557f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 85679902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 85779902029SXiaojie Yuan amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 85820c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 859078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 860078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 86120c14ee1SPetr Cvek #endif 86244e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 86344e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 8647f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 8659530273eSEvan Quan !amdgpu_sriov_vf(adev)) 8667f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 8671fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 868fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 8695be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 87044e9e7c9SXiaojie Yuan break; 8712e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 8722e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 8730b3df16bSLikun Gao amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 874757b3af8SLikun Gao amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 87556304e72SLikun Gao if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 8765aa02350SLikun Gao amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 877b07e5c60SLikun Gao if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 878acf2740fSJane Jian is_support_sw_smu(adev)) 879b07e5c60SLikun Gao amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 8809a986760SLikun Gao if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 8819a986760SLikun Gao amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 882464ab91aSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 883464ab91aSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 884464ab91aSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 885464ab91aSBhawanpreet Lakha #endif 886933c8a93SLikun Gao amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 887157e72e8SLikun Gao amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 888b8f10585SLeo Liu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 889c45fbe1bSJack Zhang if (!amdgpu_sriov_vf(adev)) 8904d72dd12SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 891a346ef86SJack Xiao if (adev->enable_mes) 892a346ef86SJack Xiao amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 8932e1ba10eSLikun Gao break; 8948515e0a4SJiansong Chen case CHIP_NAVY_FLOUNDER: 8958515e0a4SJiansong Chen amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 896fc8f07daSJiansong Chen amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 897026c396bSJiansong Chen amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 8987420eab2SJiansong Chen if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 8997420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 9007420eab2SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 9017420eab2SJiansong Chen is_support_sw_smu(adev)) 9027420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 9035404f073SJiansong Chen if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 9045404f073SJiansong Chen amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 905a6c5308fSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 906a6c5308fSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 907a6c5308fSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 908a6c5308fSBhawanpreet Lakha #endif 909885eb3faSJiansong Chen amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 910df2d15dfSJiansong Chen amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 911290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 912290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 913f4497d10SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 914f4497d10SJiansong Chen is_support_sw_smu(adev)) 915f4497d10SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 9168515e0a4SJiansong Chen break; 91788edbad6SHuang Rui case CHIP_VANGOGH: 91888edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 91988edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 92088edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 921ed3b7353SHuang Rui if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 922ed3b7353SHuang Rui amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 923c821e0fbSHuang Rui amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 92488edbad6SHuang Rui if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 92588edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 92684b934bcSHuang Rui #if defined(CONFIG_DRM_AMD_DC) 92784b934bcSHuang Rui else if (amdgpu_device_has_dc_support(adev)) 92884b934bcSHuang Rui amdgpu_device_ip_block_add(adev, &dm_ip_block); 92984b934bcSHuang Rui #endif 93088edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 93188edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 932b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 933b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 93488edbad6SHuang Rui break; 9352aa92b12STao Zhou case CHIP_DIMGREY_CAVEFISH: 9362aa92b12STao Zhou amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 9373e02ad44STao Zhou amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 938771cc67eSTao Zhou amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 939aff39cdeSTao Zhou if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 940aff39cdeSTao Zhou amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 941aff39cdeSTao Zhou if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 942aff39cdeSTao Zhou is_support_sw_smu(adev)) 943aff39cdeSTao Zhou amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 94476a2d9eaSTao Zhou if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 94576a2d9eaSTao Zhou amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 9467cc656e2STao Zhou #if defined(CONFIG_DRM_AMD_DC) 9477cc656e2STao Zhou else if (amdgpu_device_has_dc_support(adev)) 9487cc656e2STao Zhou amdgpu_device_ip_block_add(adev, &dm_ip_block); 9497cc656e2STao Zhou #endif 950feb6329cSTao Zhou amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 95101069226STao Zhou amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 9520afc770bSJames Zhu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 953be6b1cd3SJames Zhu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 9542aa92b12STao Zhou break; 955aa2caa2aSChengming Gui case CHIP_BEIGE_GOBY: 956aa2caa2aSChengming Gui amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 9572d527ea6SChengming Gui amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 958a1dede36SChengming Gui amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 959c0729819SChengming Gui if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 960c0729819SChengming Gui amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 961c0729819SChengming Gui if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 962c0729819SChengming Gui is_support_sw_smu(adev)) 963c0729819SChengming Gui amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 964898319caSChengming Gui amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 9658760403eSChengming Gui amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 9665663da86SChengming Gui if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 9675663da86SChengming Gui amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 9684d352669SChengming Gui if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 9694d352669SChengming Gui is_support_sw_smu(adev)) 9704d352669SChengming Gui amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 971f703d4b6SVeerabadhran Gopalakrishnan amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 972aa2caa2aSChengming Gui break; 973c6b6a421SHawking Zhang default: 974c6b6a421SHawking Zhang return -EINVAL; 975c6b6a421SHawking Zhang } 976c6b6a421SHawking Zhang 977c6b6a421SHawking Zhang return 0; 978c6b6a421SHawking Zhang } 979c6b6a421SHawking Zhang 980c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 981c6b6a421SHawking Zhang { 982bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 983c6b6a421SHawking Zhang } 984c6b6a421SHawking Zhang 985c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 986c6b6a421SHawking Zhang { 987c6b6a421SHawking Zhang return true; 988c6b6a421SHawking Zhang } 989c6b6a421SHawking Zhang 990c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 991c6b6a421SHawking Zhang { 992c6b6a421SHawking Zhang u32 sol_reg; 993c6b6a421SHawking Zhang 994c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 995c6b6a421SHawking Zhang return false; 996c6b6a421SHawking Zhang 997c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 998c6b6a421SHawking Zhang * are already been loaded. 999c6b6a421SHawking Zhang */ 1000c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 1001c6b6a421SHawking Zhang if (sol_reg) 1002c6b6a421SHawking Zhang return true; 10033967ae6dSAlex Deucher 1004c6b6a421SHawking Zhang return false; 1005c6b6a421SHawking Zhang } 1006c6b6a421SHawking Zhang 10072af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 10082af81531SKevin Wang { 10092af81531SKevin Wang 10102af81531SKevin Wang /* TODO 10112af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 10122af81531SKevin Wang * */ 10132af81531SKevin Wang 10142af81531SKevin Wang return 0; 10152af81531SKevin Wang } 10162af81531SKevin Wang 1017c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 1018c6b6a421SHawking Zhang { 1019c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 1020c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 1021c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 1022c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 1023c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 1024c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 1025c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 1026c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 1027c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 1028c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 1029c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 1030c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 1031c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 103220519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 1033c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 1034c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 1035157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 1036157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 1037c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 1038c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 1039c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 1040c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 1041c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 1042c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 1043c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 1044c6b6a421SHawking Zhang 1045c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 1046c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 1047c6b6a421SHawking Zhang } 1048c6b6a421SHawking Zhang 1049a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 1050a7173731SAlex Deucher { 1051a7173731SAlex Deucher } 1052a7173731SAlex Deucher 105327747293SEvan Quan static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 105427747293SEvan Quan bool enter) 105527747293SEvan Quan { 105627747293SEvan Quan if (enter) 105727747293SEvan Quan amdgpu_gfx_rlc_enter_safe_mode(adev); 105827747293SEvan Quan else 105927747293SEvan Quan amdgpu_gfx_rlc_exit_safe_mode(adev); 106027747293SEvan Quan 106127747293SEvan Quan if (adev->gfx.funcs->update_perfmon_mgcg) 106227747293SEvan Quan adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 106327747293SEvan Quan 10643273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 1065e1edaeafSLikun Gao (adev->nbio.funcs->enable_aspm)) 106627747293SEvan Quan adev->nbio.funcs->enable_aspm(adev, !enter); 106727747293SEvan Quan 106827747293SEvan Quan return 0; 106927747293SEvan Quan } 107027747293SEvan Quan 1071c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 1072c6b6a421SHawking Zhang { 1073c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 1074c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 1075c6b6a421SHawking Zhang .read_register = &nv_read_register, 1076c6b6a421SHawking Zhang .reset = &nv_asic_reset, 10772ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 1078c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 1079c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 1080c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 1081c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 1082c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 1083c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 1084c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 1085c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 10862af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 1087181e772fSEvan Quan .supports_baco = &amdgpu_dpm_is_baco_supported, 1088a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 108927747293SEvan Quan .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 10903b246e8bSAlex Deucher .query_video_codecs = &nv_query_video_codecs, 1091c6b6a421SHawking Zhang }; 1092c6b6a421SHawking Zhang 1093c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 1094c6b6a421SHawking Zhang { 1095923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 1096c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1097c6b6a421SHawking Zhang 1098923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 1099923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 1100c6b6a421SHawking Zhang adev->smc_rreg = NULL; 1101c6b6a421SHawking Zhang adev->smc_wreg = NULL; 1102c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 1103c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 11044922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 11054922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 11065de54343SHuang Rui adev->pciep_rreg = &nv_pcie_port_rreg; 11075de54343SHuang Rui adev->pciep_wreg = &nv_pcie_port_wreg; 1108c6b6a421SHawking Zhang 1109c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 1110c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 1111c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 1112c6b6a421SHawking Zhang 1113c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 1114c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 1115c6b6a421SHawking Zhang 1116c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 1117c6b6a421SHawking Zhang 1118c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 1119c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 1120c6b6a421SHawking Zhang switch (adev->asic_type) { 1121c6b6a421SHawking Zhang case CHIP_NAVI10: 1122c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1123c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 1124c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 1125c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 1126c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 1127c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 1128c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 1129c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 1130c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 1131c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 1132c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 1133c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 1134099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 1135c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 1136c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 1137157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1138c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 1139099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 1140a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 1141c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 1142c6b6a421SHawking Zhang break; 11435e71e011SXiaojie Yuan case CHIP_NAVI14: 1144d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1145d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 1146d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 1147d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 1148d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 1149d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 1150d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 1151d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 1152d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 1153d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 1154d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 1155d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 1156099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 1157d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 1158d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 11590377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 1160099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 11610377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 116235ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 11635e71e011SXiaojie Yuan break; 116474b5e509SXiaojie Yuan case CHIP_NAVI12: 1165dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1166dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 1167dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 1168dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 11695211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 1170fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 11715211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 1172358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 1173358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 11748b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 11758b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 1176ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 1177ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 117865872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 1179099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 1180099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 1181c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 11825ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 1183099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 11841b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 1185df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 1186df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 1187df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 1188df5e984cSTiecheng Zhou */ 1189df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 1190df5e984cSTiecheng Zhou adev->rev_id = 0; 119174b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 119274b5e509SXiaojie Yuan break; 1193117910edSLikun Gao case CHIP_SIENNA_CICHLID: 119400194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 119500194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 11961d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 119700194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 119898f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 119900194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 1200ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 1201ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 12023a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 1203bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 1204bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 1205b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1206d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 1207b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 12081b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 12091b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 1210c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 1211c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 1212c45fbe1bSJack Zhang adev->cg_flags = 0; 1213c45fbe1bSJack Zhang adev->pg_flags = 0; 1214c45fbe1bSJack Zhang } 1215117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 1216117910edSLikun Gao break; 1217543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 121840582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 121940582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 12201d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 122140582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 122240582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 122392c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 122492c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 12254759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 12264759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 122785e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 122885e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 1229c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 123000740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 123147fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 123247fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 123347fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 1234543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 1235543aa259SJiansong Chen break; 1236543aa259SJiansong Chen 1237026570e6SHuang Rui case CHIP_VANGOGH: 1238c345c89bSHuang Rui adev->apu_flags |= AMD_APU_IS_VANGOGH; 123951a7e938SJinzhou.Su adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 124051a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_MGLS | 124151a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CP_LS | 124251a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_RLC_LS | 124351a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CGCG | 1244ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_CGLS | 1245ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_3D_CGCG | 124607f9c22fSBoyuan Zhang AMD_CG_SUPPORT_GFX_3D_CGLS | 12470ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_MGCG | 12480ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_LS | 1249a3964ec4SJinzhou.Su AMD_CG_SUPPORT_GFX_FGCG | 125007f9c22fSBoyuan Zhang AMD_CG_SUPPORT_VCN_MGCG | 1251ef9bcfdeSJinzhou Su AMD_CG_SUPPORT_SDMA_MGCG | 1252ec0f72cbSJinzhou Su AMD_CG_SUPPORT_SDMA_LS | 125307f9c22fSBoyuan Zhang AMD_CG_SUPPORT_JPEG_MGCG; 125407f9c22fSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 125507f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN | 125607f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 125707f9c22fSBoyuan Zhang AMD_PG_SUPPORT_JPEG; 1258c345c89bSHuang Rui if (adev->apu_flags & AMD_APU_IS_VANGOGH) 1259026570e6SHuang Rui adev->external_rev_id = adev->rev_id + 0x01; 1260026570e6SHuang Rui break; 1261550c58e0STao Zhou case CHIP_DIMGREY_CAVEFISH: 1262583e5a5eSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1263583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 12641d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 1265583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 1266583e5a5eSTao Zhou AMD_CG_SUPPORT_VCN_MGCG | 1267135333a0STao Zhou AMD_CG_SUPPORT_JPEG_MGCG | 1268135333a0STao Zhou AMD_CG_SUPPORT_MC_MGCG | 12692c70c332STao Zhou AMD_CG_SUPPORT_MC_LS | 12702c70c332STao Zhou AMD_CG_SUPPORT_HDP_MGCG | 12718e3bfb99STao Zhou AMD_CG_SUPPORT_HDP_LS | 12728e3bfb99STao Zhou AMD_CG_SUPPORT_IH_CG; 1273d5bc1579SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1274cc6161aaSJames Zhu AMD_PG_SUPPORT_VCN_DPG | 127573da8e86STao Zhou AMD_PG_SUPPORT_JPEG | 127673da8e86STao Zhou AMD_PG_SUPPORT_ATHUB | 127773da8e86STao Zhou AMD_PG_SUPPORT_MMHUB; 1278550c58e0STao Zhou adev->external_rev_id = adev->rev_id + 0x3c; 1279550c58e0STao Zhou break; 12808573035aSChengming Gui case CHIP_BEIGE_GOBY: 1281bc6bd46bSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1282bc6bd46bSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 1283*d69d278fSTao Zhou AMD_CG_SUPPORT_GFX_CGLS | 12845d36b865STao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 12855d36b865STao Zhou AMD_CG_SUPPORT_MC_MGCG | 1286170c193fSTao Zhou AMD_CG_SUPPORT_MC_LS | 1287170c193fSTao Zhou AMD_CG_SUPPORT_HDP_MGCG | 1288a764bef3STao Zhou AMD_CG_SUPPORT_HDP_LS | 1289e47e4c0eSVeerabadhran Gopalakrishnan AMD_CG_SUPPORT_IH_CG | 1290e47e4c0eSVeerabadhran Gopalakrishnan AMD_CG_SUPPORT_VCN_MGCG; 1291f703d4b6SVeerabadhran Gopalakrishnan adev->pg_flags = AMD_PG_SUPPORT_VCN | 1292147de218STao Zhou AMD_PG_SUPPORT_VCN_DPG | 1293147de218STao Zhou AMD_PG_SUPPORT_ATHUB | 1294147de218STao Zhou AMD_PG_SUPPORT_MMHUB; 12958573035aSChengming Gui adev->external_rev_id = adev->rev_id + 0x46; 12968573035aSChengming Gui break; 1297c6b6a421SHawking Zhang default: 1298c6b6a421SHawking Zhang /* FIXME: not supported yet */ 1299c6b6a421SHawking Zhang return -EINVAL; 1300c6b6a421SHawking Zhang } 1301c6b6a421SHawking Zhang 13027bd939d0SLikun GAO if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 13037bd939d0SLikun GAO adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 13047bd939d0SLikun GAO AMD_PG_SUPPORT_VCN_DPG | 13057bd939d0SLikun GAO AMD_PG_SUPPORT_JPEG); 13067bd939d0SLikun GAO 1307b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 1308b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 1309b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 1310b05b6903SJiange Zhao } 1311b05b6903SJiange Zhao 1312c6b6a421SHawking Zhang return 0; 1313c6b6a421SHawking Zhang } 1314c6b6a421SHawking Zhang 1315c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 1316c6b6a421SHawking Zhang { 1317b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1318b05b6903SJiange Zhao 1319ed9d2053SBokun Zhang if (amdgpu_sriov_vf(adev)) { 1320b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 1321ed9d2053SBokun Zhang amdgpu_virt_update_sriov_video_codec(adev, 1322ed9d2053SBokun Zhang sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 1323ed9d2053SBokun Zhang sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); 1324ed9d2053SBokun Zhang } 1325b05b6903SJiange Zhao 1326c6b6a421SHawking Zhang return 0; 1327c6b6a421SHawking Zhang } 1328c6b6a421SHawking Zhang 1329c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 1330c6b6a421SHawking Zhang { 1331b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1332b05b6903SJiange Zhao 1333b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 1334b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 1335b05b6903SJiange Zhao 1336c6b6a421SHawking Zhang return 0; 1337c6b6a421SHawking Zhang } 1338c6b6a421SHawking Zhang 1339c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 1340c6b6a421SHawking Zhang { 1341c6b6a421SHawking Zhang return 0; 1342c6b6a421SHawking Zhang } 1343c6b6a421SHawking Zhang 1344c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 1345c6b6a421SHawking Zhang { 1346c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1347c6b6a421SHawking Zhang 1348c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 1349c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 1350c6b6a421SHawking Zhang /* enable aspm */ 1351c6b6a421SHawking Zhang nv_program_aspm(adev); 1352c6b6a421SHawking Zhang /* setup nbio registers */ 1353bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 1354923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 1355923c087aSYong Zhao * for the purpose of expose those registers 1356923c087aSYong Zhao * to process space 1357923c087aSYong Zhao */ 1358923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 1359923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 1360c6b6a421SHawking Zhang /* enable the doorbell aperture */ 1361c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 1362c6b6a421SHawking Zhang 1363c6b6a421SHawking Zhang return 0; 1364c6b6a421SHawking Zhang } 1365c6b6a421SHawking Zhang 1366c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 1367c6b6a421SHawking Zhang { 1368c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1369c6b6a421SHawking Zhang 1370c6b6a421SHawking Zhang /* disable the doorbell aperture */ 1371c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 1372c6b6a421SHawking Zhang 1373c6b6a421SHawking Zhang return 0; 1374c6b6a421SHawking Zhang } 1375c6b6a421SHawking Zhang 1376c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 1377c6b6a421SHawking Zhang { 1378c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1379c6b6a421SHawking Zhang 1380c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 1381c6b6a421SHawking Zhang } 1382c6b6a421SHawking Zhang 1383c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 1384c6b6a421SHawking Zhang { 1385c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1386c6b6a421SHawking Zhang 1387c6b6a421SHawking Zhang return nv_common_hw_init(adev); 1388c6b6a421SHawking Zhang } 1389c6b6a421SHawking Zhang 1390c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 1391c6b6a421SHawking Zhang { 1392c6b6a421SHawking Zhang return true; 1393c6b6a421SHawking Zhang } 1394c6b6a421SHawking Zhang 1395c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 1396c6b6a421SHawking Zhang { 1397c6b6a421SHawking Zhang return 0; 1398c6b6a421SHawking Zhang } 1399c6b6a421SHawking Zhang 1400c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 1401c6b6a421SHawking Zhang { 1402c6b6a421SHawking Zhang return 0; 1403c6b6a421SHawking Zhang } 1404c6b6a421SHawking Zhang 1405c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1406c6b6a421SHawking Zhang enum amd_clockgating_state state) 1407c6b6a421SHawking Zhang { 1408c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1409c6b6a421SHawking Zhang 1410c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1411c6b6a421SHawking Zhang return 0; 1412c6b6a421SHawking Zhang 1413c6b6a421SHawking Zhang switch (adev->asic_type) { 1414c6b6a421SHawking Zhang case CHIP_NAVI10: 14155e71e011SXiaojie Yuan case CHIP_NAVI14: 14167e17e58bSXiaojie Yuan case CHIP_NAVI12: 1417117910edSLikun Gao case CHIP_SIENNA_CICHLID: 1418543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 1419550c58e0STao Zhou case CHIP_DIMGREY_CAVEFISH: 14208573035aSChengming Gui case CHIP_BEIGE_GOBY: 1421bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1422a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1423bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1424a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1425bf087285SLikun Gao adev->hdp.funcs->update_clock_gating(adev, 1426a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 14271001f2a1SLikun Gao adev->smuio.funcs->update_rom_clock_gating(adev, 14281001f2a1SLikun Gao state == AMD_CG_STATE_GATE); 1429c6b6a421SHawking Zhang break; 1430c6b6a421SHawking Zhang default: 1431c6b6a421SHawking Zhang break; 1432c6b6a421SHawking Zhang } 1433c6b6a421SHawking Zhang return 0; 1434c6b6a421SHawking Zhang } 1435c6b6a421SHawking Zhang 1436c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1437c6b6a421SHawking Zhang enum amd_powergating_state state) 1438c6b6a421SHawking Zhang { 1439c6b6a421SHawking Zhang /* TODO */ 1440c6b6a421SHawking Zhang return 0; 1441c6b6a421SHawking Zhang } 1442c6b6a421SHawking Zhang 1443c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1444c6b6a421SHawking Zhang { 1445c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1446c6b6a421SHawking Zhang 1447c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1448c6b6a421SHawking Zhang *flags = 0; 1449c6b6a421SHawking Zhang 1450bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1451c6b6a421SHawking Zhang 1452bf087285SLikun Gao adev->hdp.funcs->get_clock_gating_state(adev, flags); 1453c6b6a421SHawking Zhang 14541001f2a1SLikun Gao adev->smuio.funcs->get_clock_gating_state(adev, flags); 14551001f2a1SLikun Gao 1456c6b6a421SHawking Zhang return; 1457c6b6a421SHawking Zhang } 1458c6b6a421SHawking Zhang 1459c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1460c6b6a421SHawking Zhang .name = "nv_common", 1461c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1462c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1463c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1464c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1465c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1466c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1467c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1468c6b6a421SHawking Zhang .resume = nv_common_resume, 1469c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1470c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1471c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1472c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1473c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1474c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1475c6b6a421SHawking Zhang }; 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