1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 28c6b6a421SHawking Zhang #include "amdgpu.h" 29c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 30c6b6a421SHawking Zhang #include "amdgpu_ih.h" 31c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 32c6b6a421SHawking Zhang #include "amdgpu_vce.h" 33c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 34c6b6a421SHawking Zhang #include "amdgpu_psp.h" 35767acabdSKevin Wang #include "amdgpu_smu.h" 36c6b6a421SHawking Zhang #include "atom.h" 37c6b6a421SHawking Zhang #include "amd_pcie.h" 38c6b6a421SHawking Zhang 39c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 41c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_offset.h" 42c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_sh_mask.h" 4329bc37b4SAlex Deucher #include "smuio/smuio_11_0_0_offset.h" 443967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 45c6b6a421SHawking Zhang 46c6b6a421SHawking Zhang #include "soc15.h" 47c6b6a421SHawking Zhang #include "soc15_common.h" 48c6b6a421SHawking Zhang #include "gmc_v10_0.h" 49c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 50c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 51bebc0762SHawking Zhang #include "nbio_v2_3.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59b8f10585SLeo Liu #include "vcn_v3_0.h" 604d72dd12SLeo Liu #include "jpeg_v3_0.h" 61c6b6a421SHawking Zhang #include "dce_virtual.h" 62c6b6a421SHawking Zhang #include "mes_v10_1.h" 63b05b6903SJiange Zhao #include "mxgpu_nv.h" 64c6b6a421SHawking Zhang 65c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 66c6b6a421SHawking Zhang 67c6b6a421SHawking Zhang /* 68c6b6a421SHawking Zhang * Indirect registers accessor 69c6b6a421SHawking Zhang */ 70c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 71c6b6a421SHawking Zhang { 72c6b6a421SHawking Zhang unsigned long flags, address, data; 73c6b6a421SHawking Zhang u32 r; 74bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 75bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 76c6b6a421SHawking Zhang 77c6b6a421SHawking Zhang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 78c6b6a421SHawking Zhang WREG32(address, reg); 79c6b6a421SHawking Zhang (void)RREG32(address); 80c6b6a421SHawking Zhang r = RREG32(data); 81c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 82c6b6a421SHawking Zhang return r; 83c6b6a421SHawking Zhang } 84c6b6a421SHawking Zhang 85c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 86c6b6a421SHawking Zhang { 87c6b6a421SHawking Zhang unsigned long flags, address, data; 88c6b6a421SHawking Zhang 89bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 90bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 91c6b6a421SHawking Zhang 92c6b6a421SHawking Zhang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 93c6b6a421SHawking Zhang WREG32(address, reg); 94c6b6a421SHawking Zhang (void)RREG32(address); 95c6b6a421SHawking Zhang WREG32(data, v); 96c6b6a421SHawking Zhang (void)RREG32(data); 97c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 98c6b6a421SHawking Zhang } 99c6b6a421SHawking Zhang 100c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 101c6b6a421SHawking Zhang { 102c6b6a421SHawking Zhang unsigned long flags, address, data; 103c6b6a421SHawking Zhang u32 r; 104c6b6a421SHawking Zhang 105c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 106c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 107c6b6a421SHawking Zhang 108c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 109c6b6a421SHawking Zhang WREG32(address, (reg)); 110c6b6a421SHawking Zhang r = RREG32(data); 111c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 112c6b6a421SHawking Zhang return r; 113c6b6a421SHawking Zhang } 114c6b6a421SHawking Zhang 115c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 116c6b6a421SHawking Zhang { 117c6b6a421SHawking Zhang unsigned long flags, address, data; 118c6b6a421SHawking Zhang 119c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 120c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 121c6b6a421SHawking Zhang 122c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 123c6b6a421SHawking Zhang WREG32(address, (reg)); 124c6b6a421SHawking Zhang WREG32(data, (v)); 125c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 126c6b6a421SHawking Zhang } 127c6b6a421SHawking Zhang 128c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 129c6b6a421SHawking Zhang { 130bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 131c6b6a421SHawking Zhang } 132c6b6a421SHawking Zhang 133c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 134c6b6a421SHawking Zhang { 135462a70d8STao Zhou return adev->clock.spll.reference_freq; 136c6b6a421SHawking Zhang } 137c6b6a421SHawking Zhang 138c6b6a421SHawking Zhang 139c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 140c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 141c6b6a421SHawking Zhang { 142c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 143c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 144c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 145c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 146c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 147c6b6a421SHawking Zhang 148c6b6a421SHawking Zhang WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 149c6b6a421SHawking Zhang } 150c6b6a421SHawking Zhang 151c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 152c6b6a421SHawking Zhang { 153c6b6a421SHawking Zhang /* todo */ 154c6b6a421SHawking Zhang } 155c6b6a421SHawking Zhang 156c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 157c6b6a421SHawking Zhang { 158c6b6a421SHawking Zhang /* todo */ 159c6b6a421SHawking Zhang return false; 160c6b6a421SHawking Zhang } 161c6b6a421SHawking Zhang 162c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 163c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 164c6b6a421SHawking Zhang { 16529bc37b4SAlex Deucher u32 *dw_ptr; 16629bc37b4SAlex Deucher u32 i, length_dw; 16729bc37b4SAlex Deucher 16829bc37b4SAlex Deucher if (bios == NULL) 169c6b6a421SHawking Zhang return false; 17029bc37b4SAlex Deucher if (length_bytes == 0) 17129bc37b4SAlex Deucher return false; 17229bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 17329bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 17429bc37b4SAlex Deucher return false; 17529bc37b4SAlex Deucher 17629bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 17729bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 17829bc37b4SAlex Deucher 17929bc37b4SAlex Deucher /* set rom index to 0 */ 18029bc37b4SAlex Deucher WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 18129bc37b4SAlex Deucher /* read out the rom data */ 18229bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 18329bc37b4SAlex Deucher dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 18429bc37b4SAlex Deucher 18529bc37b4SAlex Deucher return true; 186c6b6a421SHawking Zhang } 187c6b6a421SHawking Zhang 188c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 189c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 190c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 191c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 192c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 193c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 194c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 195c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 196c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 197c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 198c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 199c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 200c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 201c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 202c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 203c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 204664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 205c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 206c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 207c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 208c6b6a421SHawking Zhang }; 209c6b6a421SHawking Zhang 210c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 211c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 212c6b6a421SHawking Zhang { 213c6b6a421SHawking Zhang uint32_t val; 214c6b6a421SHawking Zhang 215c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 216c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 217c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 218c6b6a421SHawking Zhang 219c6b6a421SHawking Zhang val = RREG32(reg_offset); 220c6b6a421SHawking Zhang 221c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 222c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 223c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 224c6b6a421SHawking Zhang return val; 225c6b6a421SHawking Zhang } 226c6b6a421SHawking Zhang 227c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 228c6b6a421SHawking Zhang bool indexed, u32 se_num, 229c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 230c6b6a421SHawking Zhang { 231c6b6a421SHawking Zhang if (indexed) { 232c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 233c6b6a421SHawking Zhang } else { 234c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 235c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 236c6b6a421SHawking Zhang return RREG32(reg_offset); 237c6b6a421SHawking Zhang } 238c6b6a421SHawking Zhang } 239c6b6a421SHawking Zhang 240c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 241c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 242c6b6a421SHawking Zhang { 243c6b6a421SHawking Zhang uint32_t i; 244c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 245c6b6a421SHawking Zhang 246c6b6a421SHawking Zhang *value = 0; 247c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 248c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 249c6b6a421SHawking Zhang if (reg_offset != 250c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 251c6b6a421SHawking Zhang continue; 252c6b6a421SHawking Zhang 253c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 254c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 255c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 256c6b6a421SHawking Zhang return 0; 257c6b6a421SHawking Zhang } 258c6b6a421SHawking Zhang return -EINVAL; 259c6b6a421SHawking Zhang } 260c6b6a421SHawking Zhang 2613e2bb60aSKevin Wang static int nv_asic_mode1_reset(struct amdgpu_device *adev) 2623e2bb60aSKevin Wang { 2633e2bb60aSKevin Wang u32 i; 2643e2bb60aSKevin Wang int ret = 0; 2653e2bb60aSKevin Wang 2663e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, true); 2673e2bb60aSKevin Wang 2683e2bb60aSKevin Wang /* disable BM */ 2693e2bb60aSKevin Wang pci_clear_master(adev->pdev); 2703e2bb60aSKevin Wang 2713e2bb60aSKevin Wang pci_save_state(adev->pdev); 2723e2bb60aSKevin Wang 273311531f0SWenhui Sheng if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 274311531f0SWenhui Sheng dev_info(adev->dev, "GPU smu mode1 reset\n"); 275311531f0SWenhui Sheng ret = amdgpu_dpm_mode1_reset(adev); 276311531f0SWenhui Sheng } else { 277311531f0SWenhui Sheng dev_info(adev->dev, "GPU psp mode1 reset\n"); 2783e2bb60aSKevin Wang ret = psp_gpu_reset(adev); 279311531f0SWenhui Sheng } 280311531f0SWenhui Sheng 2813e2bb60aSKevin Wang if (ret) 2823e2bb60aSKevin Wang dev_err(adev->dev, "GPU mode1 reset failed\n"); 2833e2bb60aSKevin Wang pci_restore_state(adev->pdev); 2843e2bb60aSKevin Wang 2853e2bb60aSKevin Wang /* wait for asic to come out of reset */ 2863e2bb60aSKevin Wang for (i = 0; i < adev->usec_timeout; i++) { 287bebc0762SHawking Zhang u32 memsize = adev->nbio.funcs->get_memsize(adev); 2883e2bb60aSKevin Wang 2893e2bb60aSKevin Wang if (memsize != 0xffffffff) 2903e2bb60aSKevin Wang break; 2913e2bb60aSKevin Wang udelay(1); 2923e2bb60aSKevin Wang } 2933e2bb60aSKevin Wang 2943e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, false); 2953e2bb60aSKevin Wang 2963e2bb60aSKevin Wang return ret; 2973e2bb60aSKevin Wang } 2982ddc6c3eSAlex Deucher 299ac742616SAlex Deucher static bool nv_asic_supports_baco(struct amdgpu_device *adev) 300ac742616SAlex Deucher { 301ac742616SAlex Deucher struct smu_context *smu = &adev->smu; 302ac742616SAlex Deucher 303ac742616SAlex Deucher if (smu_baco_is_support(smu)) 304ac742616SAlex Deucher return true; 305ac742616SAlex Deucher else 306ac742616SAlex Deucher return false; 307ac742616SAlex Deucher } 308ac742616SAlex Deucher 3092ddc6c3eSAlex Deucher static enum amd_reset_method 3102ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 3112ddc6c3eSAlex Deucher { 3122ddc6c3eSAlex Deucher struct smu_context *smu = &adev->smu; 3132ddc6c3eSAlex Deucher 314273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 315273da6ffSWenhui Sheng amdgpu_reset_method == AMD_RESET_METHOD_BACO) 316273da6ffSWenhui Sheng return amdgpu_reset_method; 317273da6ffSWenhui Sheng 318273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 319273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 320273da6ffSWenhui Sheng amdgpu_reset_method); 321273da6ffSWenhui Sheng 322311531f0SWenhui Sheng if (smu_baco_is_support(smu)) 3232ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 3242ddc6c3eSAlex Deucher else 3252ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 3262ddc6c3eSAlex Deucher } 3272ddc6c3eSAlex Deucher 328c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 329c6b6a421SHawking Zhang { 330767acabdSKevin Wang int ret = 0; 331767acabdSKevin Wang struct smu_context *smu = &adev->smu; 332c6b6a421SHawking Zhang 333e3526257SMonk Liu if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 334311531f0SWenhui Sheng dev_info(adev->dev, "GPU BACO reset\n"); 335311531f0SWenhui Sheng 33611520f27SAlex Deucher ret = smu_baco_enter(smu); 33711520f27SAlex Deucher if (ret) 33811520f27SAlex Deucher return ret; 33911520f27SAlex Deucher ret = smu_baco_exit(smu); 34011520f27SAlex Deucher if (ret) 34111520f27SAlex Deucher return ret; 342311531f0SWenhui Sheng } else 3433e2bb60aSKevin Wang ret = nv_asic_mode1_reset(adev); 344767acabdSKevin Wang 345767acabdSKevin Wang return ret; 346c6b6a421SHawking Zhang } 347c6b6a421SHawking Zhang 348c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 349c6b6a421SHawking Zhang { 350c6b6a421SHawking Zhang /* todo */ 351c6b6a421SHawking Zhang return 0; 352c6b6a421SHawking Zhang } 353c6b6a421SHawking Zhang 354c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 355c6b6a421SHawking Zhang { 356c6b6a421SHawking Zhang /* todo */ 357c6b6a421SHawking Zhang return 0; 358c6b6a421SHawking Zhang } 359c6b6a421SHawking Zhang 360c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 361c6b6a421SHawking Zhang { 362c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 363c6b6a421SHawking Zhang return; 364c6b6a421SHawking Zhang 365c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 366c6b6a421SHawking Zhang return; 367c6b6a421SHawking Zhang 368c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 369c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 370c6b6a421SHawking Zhang return; 371c6b6a421SHawking Zhang 372c6b6a421SHawking Zhang /* todo */ 373c6b6a421SHawking Zhang } 374c6b6a421SHawking Zhang 375c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 376c6b6a421SHawking Zhang { 377c6b6a421SHawking Zhang 378c6b6a421SHawking Zhang if (amdgpu_aspm == 0) 379c6b6a421SHawking Zhang return; 380c6b6a421SHawking Zhang 381c6b6a421SHawking Zhang /* todo */ 382c6b6a421SHawking Zhang } 383c6b6a421SHawking Zhang 384c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 385c6b6a421SHawking Zhang bool enable) 386c6b6a421SHawking Zhang { 387bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 388bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 389c6b6a421SHawking Zhang } 390c6b6a421SHawking Zhang 391c6b6a421SHawking Zhang static const struct amdgpu_ip_block_version nv_common_ip_block = 392c6b6a421SHawking Zhang { 393c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 394c6b6a421SHawking Zhang .major = 1, 395c6b6a421SHawking Zhang .minor = 0, 396c6b6a421SHawking Zhang .rev = 0, 397c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 398c6b6a421SHawking Zhang }; 399c6b6a421SHawking Zhang 400b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 401c6b6a421SHawking Zhang { 402b5c73856SXiaojie Yuan int r; 403b5c73856SXiaojie Yuan 404b5c73856SXiaojie Yuan if (amdgpu_discovery) { 405b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 406b5c73856SXiaojie Yuan if (r) { 407b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 408b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 409b5c73856SXiaojie Yuan goto legacy_init; 410b5c73856SXiaojie Yuan } 411b5c73856SXiaojie Yuan 412b5c73856SXiaojie Yuan return 0; 413b5c73856SXiaojie Yuan } 414b5c73856SXiaojie Yuan 415b5c73856SXiaojie Yuan legacy_init: 416c6b6a421SHawking Zhang switch (adev->asic_type) { 417c6b6a421SHawking Zhang case CHIP_NAVI10: 418c6b6a421SHawking Zhang navi10_reg_base_init(adev); 419c6b6a421SHawking Zhang break; 420a0f6d926SXiaojie Yuan case CHIP_NAVI14: 421a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 422a0f6d926SXiaojie Yuan break; 42303d0a073SXiaojie Yuan case CHIP_NAVI12: 42403d0a073SXiaojie Yuan navi12_reg_base_init(adev); 42503d0a073SXiaojie Yuan break; 426dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 427c8c959f6SJiansong Chen case CHIP_NAVY_FLOUNDER: 428dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 429dccdbf3fSLikun Gao break; 430c6b6a421SHawking Zhang default: 431c6b6a421SHawking Zhang return -EINVAL; 432c6b6a421SHawking Zhang } 433c6b6a421SHawking Zhang 434b5c73856SXiaojie Yuan return 0; 435b5c73856SXiaojie Yuan } 436b5c73856SXiaojie Yuan 437c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 438c1299461SWenhui Sheng { 439c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 440c1299461SWenhui Sheng } 441c1299461SWenhui Sheng 442b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 443b5c73856SXiaojie Yuan { 444b5c73856SXiaojie Yuan int r; 445b5c73856SXiaojie Yuan 446122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 447122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 448122078deSMonk Liu 449c652923aSJohn Clements if (adev->asic_type == CHIP_SIENNA_CICHLID) 450c652923aSJohn Clements adev->gmc.xgmi.supported = true; 451c652923aSJohn Clements 452b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 453b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 454b5c73856SXiaojie Yuan if (r) 455b5c73856SXiaojie Yuan return r; 456b5c73856SXiaojie Yuan 457c6b6a421SHawking Zhang switch (adev->asic_type) { 458c6b6a421SHawking Zhang case CHIP_NAVI10: 459d1daf850SAlex Deucher case CHIP_NAVI14: 460c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 461c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 462c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 463c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 464c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4659530273eSEvan Quan !amdgpu_sriov_vf(adev)) 466c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 467c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 468c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 469f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 470b4f199c7SHarry Wentland else if (amdgpu_device_has_dc_support(adev)) 471b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 472f8a7976bSAlex Deucher #endif 473c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 474c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 475c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 4769530273eSEvan Quan !amdgpu_sriov_vf(adev)) 477c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 478c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 4795be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 480c6b6a421SHawking Zhang if (adev->enable_mes) 481c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 482c6b6a421SHawking Zhang break; 48344e9e7c9SXiaojie Yuan case CHIP_NAVI12: 48444e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 48544e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 48644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 4876b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 48879bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 4897f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 49079902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 49179902029SXiaojie Yuan amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 49220c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 493078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 494078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 49520c14ee1SPetr Cvek #endif 49644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 49744e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 4987f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 4999530273eSEvan Quan !amdgpu_sriov_vf(adev)) 5007f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5011fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 502fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 5035be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 50444e9e7c9SXiaojie Yuan break; 5052e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 5062e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 5070b3df16bSLikun Gao amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 508757b3af8SLikun Gao amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 50956304e72SLikun Gao if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 5105aa02350SLikun Gao amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 511b07e5c60SLikun Gao if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 51238d5bbefSshaoyunl is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 513b07e5c60SLikun Gao amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5149a986760SLikun Gao if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 5159a986760SLikun Gao amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 516464ab91aSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 517464ab91aSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 518464ab91aSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 519464ab91aSBhawanpreet Lakha #endif 520933c8a93SLikun Gao amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 521157e72e8SLikun Gao amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 522b8f10585SLeo Liu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 523c45fbe1bSJack Zhang if (!amdgpu_sriov_vf(adev)) 5244d72dd12SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 525c45fbe1bSJack Zhang 526a346ef86SJack Xiao if (adev->enable_mes) 527a346ef86SJack Xiao amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 5282e1ba10eSLikun Gao break; 5298515e0a4SJiansong Chen case CHIP_NAVY_FLOUNDER: 5308515e0a4SJiansong Chen amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 531fc8f07daSJiansong Chen amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 532026c396bSJiansong Chen amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 5337420eab2SJiansong Chen if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 5347420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 5357420eab2SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5367420eab2SJiansong Chen is_support_sw_smu(adev)) 5377420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5385404f073SJiansong Chen if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 5395404f073SJiansong Chen amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 540a6c5308fSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 541a6c5308fSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 542a6c5308fSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 543a6c5308fSBhawanpreet Lakha #endif 544885eb3faSJiansong Chen amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 545df2d15dfSJiansong Chen amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 546290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 547290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 548f4497d10SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 549f4497d10SJiansong Chen is_support_sw_smu(adev)) 550f4497d10SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5518515e0a4SJiansong Chen break; 552c6b6a421SHawking Zhang default: 553c6b6a421SHawking Zhang return -EINVAL; 554c6b6a421SHawking Zhang } 555c6b6a421SHawking Zhang 556c6b6a421SHawking Zhang return 0; 557c6b6a421SHawking Zhang } 558c6b6a421SHawking Zhang 559c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 560c6b6a421SHawking Zhang { 561bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 562c6b6a421SHawking Zhang } 563c6b6a421SHawking Zhang 564c6b6a421SHawking Zhang static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 565c6b6a421SHawking Zhang { 566bebc0762SHawking Zhang adev->nbio.funcs->hdp_flush(adev, ring); 567c6b6a421SHawking Zhang } 568c6b6a421SHawking Zhang 569c6b6a421SHawking Zhang static void nv_invalidate_hdp(struct amdgpu_device *adev, 570c6b6a421SHawking Zhang struct amdgpu_ring *ring) 571c6b6a421SHawking Zhang { 572c6b6a421SHawking Zhang if (!ring || !ring->funcs->emit_wreg) { 573c6b6a421SHawking Zhang WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 574c6b6a421SHawking Zhang } else { 575c6b6a421SHawking Zhang amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 576c6b6a421SHawking Zhang HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 577c6b6a421SHawking Zhang } 578c6b6a421SHawking Zhang } 579c6b6a421SHawking Zhang 580c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 581c6b6a421SHawking Zhang { 582c6b6a421SHawking Zhang return true; 583c6b6a421SHawking Zhang } 584c6b6a421SHawking Zhang 585c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 586c6b6a421SHawking Zhang { 587c6b6a421SHawking Zhang u32 sol_reg; 588c6b6a421SHawking Zhang 589c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 590c6b6a421SHawking Zhang return false; 591c6b6a421SHawking Zhang 592c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 593c6b6a421SHawking Zhang * are already been loaded. 594c6b6a421SHawking Zhang */ 595c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 596c6b6a421SHawking Zhang if (sol_reg) 597c6b6a421SHawking Zhang return true; 5983967ae6dSAlex Deucher 599c6b6a421SHawking Zhang return false; 600c6b6a421SHawking Zhang } 601c6b6a421SHawking Zhang 6022af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 6032af81531SKevin Wang { 6042af81531SKevin Wang 6052af81531SKevin Wang /* TODO 6062af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 6072af81531SKevin Wang * */ 6082af81531SKevin Wang 6092af81531SKevin Wang return 0; 6102af81531SKevin Wang } 6112af81531SKevin Wang 612c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 613c6b6a421SHawking Zhang { 614c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 615c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 616c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 617c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 618c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 619c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 620c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 621c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 622c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 623c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 624c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 625c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 626c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 62720519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 628c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 629c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 630157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 631157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 632c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 633c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 634c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 635c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 636c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 637c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 638c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 639c6b6a421SHawking Zhang 640c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 641c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 642c6b6a421SHawking Zhang } 643c6b6a421SHawking Zhang 644c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 645c6b6a421SHawking Zhang { 646c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 647c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 648c6b6a421SHawking Zhang .read_register = &nv_read_register, 649c6b6a421SHawking Zhang .reset = &nv_asic_reset, 6502ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 651c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 652c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 653c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 654c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 655c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 656c6b6a421SHawking Zhang .flush_hdp = &nv_flush_hdp, 657c6b6a421SHawking Zhang .invalidate_hdp = &nv_invalidate_hdp, 658c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 659c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 660c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 6612af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 662ac742616SAlex Deucher .supports_baco = &nv_asic_supports_baco, 663c6b6a421SHawking Zhang }; 664c6b6a421SHawking Zhang 665c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 666c6b6a421SHawking Zhang { 667923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 668c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 669c6b6a421SHawking Zhang 670923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 671923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 672c6b6a421SHawking Zhang adev->smc_rreg = NULL; 673c6b6a421SHawking Zhang adev->smc_wreg = NULL; 674c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 675c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 676c6b6a421SHawking Zhang 677c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 678c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 679c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 680c6b6a421SHawking Zhang 681c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 682c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 683c6b6a421SHawking Zhang 684c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 685c6b6a421SHawking Zhang 686c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 687c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 688c6b6a421SHawking Zhang switch (adev->asic_type) { 689c6b6a421SHawking Zhang case CHIP_NAVI10: 690c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 691c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 692c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 693c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 694c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 695c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 696c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 697c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 698c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 699c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 700c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 701c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 702099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 703c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 704c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 705157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 706c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 707099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 708a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 709c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 710c6b6a421SHawking Zhang break; 7115e71e011SXiaojie Yuan case CHIP_NAVI14: 712d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 713d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 714d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 715d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 716d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 717d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 718d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 719d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 720d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 721d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 722d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 723d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 724099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 725d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 726d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 7270377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 728099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7290377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 73035ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 7315e71e011SXiaojie Yuan break; 73274b5e509SXiaojie Yuan case CHIP_NAVI12: 733dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 734dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 735dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 736dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 7375211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 738fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 7395211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 740358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 741358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 7428b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 7438b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 744ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 745ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 74665872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 747099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 748099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 749c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 7505ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 751099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7521b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 753df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 754df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 755df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 756df5e984cSTiecheng Zhou */ 757df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 758df5e984cSTiecheng Zhou adev->rev_id = 0; 75974b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 76074b5e509SXiaojie Yuan break; 761117910edSLikun Gao case CHIP_SIENNA_CICHLID: 76200194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 76300194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 76400194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 76598f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 76600194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 767ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 768ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 7693a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 770bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 771bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 772b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 773d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 774b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 7751b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 7761b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 777c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 778c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 779c45fbe1bSJack Zhang adev->cg_flags = 0; 780c45fbe1bSJack Zhang adev->pg_flags = 0; 781c45fbe1bSJack Zhang } 782117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 783117910edSLikun Gao break; 784543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 78540582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 78640582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 78740582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 78840582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 78992c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 79092c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 7914759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 7924759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 79385e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 79485e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 795c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 79600740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 79747fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 79847fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 79947fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 800543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 801543aa259SJiansong Chen break; 802543aa259SJiansong Chen 803c6b6a421SHawking Zhang default: 804c6b6a421SHawking Zhang /* FIXME: not supported yet */ 805c6b6a421SHawking Zhang return -EINVAL; 806c6b6a421SHawking Zhang } 807c6b6a421SHawking Zhang 808b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 809b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 810b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 811b05b6903SJiange Zhao } 812b05b6903SJiange Zhao 813c6b6a421SHawking Zhang return 0; 814c6b6a421SHawking Zhang } 815c6b6a421SHawking Zhang 816c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 817c6b6a421SHawking Zhang { 818b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 819b05b6903SJiange Zhao 820b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 821b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 822b05b6903SJiange Zhao 823c6b6a421SHawking Zhang return 0; 824c6b6a421SHawking Zhang } 825c6b6a421SHawking Zhang 826c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 827c6b6a421SHawking Zhang { 828b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 829b05b6903SJiange Zhao 830b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 831b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 832b05b6903SJiange Zhao 833c6b6a421SHawking Zhang return 0; 834c6b6a421SHawking Zhang } 835c6b6a421SHawking Zhang 836c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 837c6b6a421SHawking Zhang { 838c6b6a421SHawking Zhang return 0; 839c6b6a421SHawking Zhang } 840c6b6a421SHawking Zhang 841c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 842c6b6a421SHawking Zhang { 843c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 844c6b6a421SHawking Zhang 845c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 846c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 847c6b6a421SHawking Zhang /* enable aspm */ 848c6b6a421SHawking Zhang nv_program_aspm(adev); 849c6b6a421SHawking Zhang /* setup nbio registers */ 850bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 851923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 852923c087aSYong Zhao * for the purpose of expose those registers 853923c087aSYong Zhao * to process space 854923c087aSYong Zhao */ 855923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 856923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 857c6b6a421SHawking Zhang /* enable the doorbell aperture */ 858c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 859c6b6a421SHawking Zhang 860c6b6a421SHawking Zhang return 0; 861c6b6a421SHawking Zhang } 862c6b6a421SHawking Zhang 863c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 864c6b6a421SHawking Zhang { 865c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 866c6b6a421SHawking Zhang 867c6b6a421SHawking Zhang /* disable the doorbell aperture */ 868c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 869c6b6a421SHawking Zhang 870c6b6a421SHawking Zhang return 0; 871c6b6a421SHawking Zhang } 872c6b6a421SHawking Zhang 873c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 874c6b6a421SHawking Zhang { 875c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 876c6b6a421SHawking Zhang 877c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 878c6b6a421SHawking Zhang } 879c6b6a421SHawking Zhang 880c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 881c6b6a421SHawking Zhang { 882c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 883c6b6a421SHawking Zhang 884c6b6a421SHawking Zhang return nv_common_hw_init(adev); 885c6b6a421SHawking Zhang } 886c6b6a421SHawking Zhang 887c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 888c6b6a421SHawking Zhang { 889c6b6a421SHawking Zhang return true; 890c6b6a421SHawking Zhang } 891c6b6a421SHawking Zhang 892c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 893c6b6a421SHawking Zhang { 894c6b6a421SHawking Zhang return 0; 895c6b6a421SHawking Zhang } 896c6b6a421SHawking Zhang 897c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 898c6b6a421SHawking Zhang { 899c6b6a421SHawking Zhang return 0; 900c6b6a421SHawking Zhang } 901c6b6a421SHawking Zhang 902c6b6a421SHawking Zhang static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 903c6b6a421SHawking Zhang bool enable) 904c6b6a421SHawking Zhang { 905c6b6a421SHawking Zhang uint32_t hdp_clk_cntl, hdp_clk_cntl1; 906c6b6a421SHawking Zhang uint32_t hdp_mem_pwr_cntl; 907c6b6a421SHawking Zhang 908c6b6a421SHawking Zhang if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 909c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_DS | 910c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_SD))) 911c6b6a421SHawking Zhang return; 912c6b6a421SHawking Zhang 913c6b6a421SHawking Zhang hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 914c6b6a421SHawking Zhang hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 915c6b6a421SHawking Zhang 916c6b6a421SHawking Zhang /* Before doing clock/power mode switch, 917c6b6a421SHawking Zhang * forced on IPH & RC clock */ 918c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 919c6b6a421SHawking Zhang IPH_MEM_CLK_SOFT_OVERRIDE, 1); 920c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 921c6b6a421SHawking Zhang RC_MEM_CLK_SOFT_OVERRIDE, 1); 922c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 923c6b6a421SHawking Zhang 924c6b6a421SHawking Zhang /* HDP 5.0 doesn't support dynamic power mode switch, 925c6b6a421SHawking Zhang * disable clock and power gating before any changing */ 926c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 927c6b6a421SHawking Zhang IPH_MEM_POWER_CTRL_EN, 0); 928c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 929c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, 0); 930c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 931c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, 0); 932c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 933c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, 0); 934c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 935c6b6a421SHawking Zhang RC_MEM_POWER_CTRL_EN, 0); 936c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 937c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, 0); 938c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 939c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, 0); 940c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 941c6b6a421SHawking Zhang RC_MEM_POWER_SD_EN, 0); 942c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 943c6b6a421SHawking Zhang 944c6b6a421SHawking Zhang /* only one clock gating mode (LS/DS/SD) can be enabled */ 945c6b6a421SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 946c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 947c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 948c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, enable); 949c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 950c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 951c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, enable); 952c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 953c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 954c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 955c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, enable); 956c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 957c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 958c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 959c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 960c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 961c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 962c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, enable); 963c6b6a421SHawking Zhang /* RC should not use shut down mode, fallback to ds */ 964c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 965c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 966c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 967c6b6a421SHawking Zhang } 968c6b6a421SHawking Zhang 96991c6adf8SKenneth Feng /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 97091c6adf8SKenneth Feng * be set for SRAM LS/DS/SD */ 97191c6adf8SKenneth Feng if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 97291c6adf8SKenneth Feng AMD_CG_SUPPORT_HDP_SD)) { 97391c6adf8SKenneth Feng hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 97491c6adf8SKenneth Feng IPH_MEM_POWER_CTRL_EN, 1); 97591c6adf8SKenneth Feng hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 97691c6adf8SKenneth Feng RC_MEM_POWER_CTRL_EN, 1); 97791c6adf8SKenneth Feng } 97891c6adf8SKenneth Feng 979c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 980c6b6a421SHawking Zhang 981c6b6a421SHawking Zhang /* restore IPH & RC clock override after clock/power mode changing */ 982c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 983c6b6a421SHawking Zhang } 984c6b6a421SHawking Zhang 985c6b6a421SHawking Zhang static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 986c6b6a421SHawking Zhang bool enable) 987c6b6a421SHawking Zhang { 988c6b6a421SHawking Zhang uint32_t hdp_clk_cntl; 989c6b6a421SHawking Zhang 990c6b6a421SHawking Zhang if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 991c6b6a421SHawking Zhang return; 992c6b6a421SHawking Zhang 993c6b6a421SHawking Zhang hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 994c6b6a421SHawking Zhang 995c6b6a421SHawking Zhang if (enable) { 996c6b6a421SHawking Zhang hdp_clk_cntl &= 997c6b6a421SHawking Zhang ~(uint32_t) 998c6b6a421SHawking Zhang (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 999c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1000c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1001c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1002c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1003c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 1004c6b6a421SHawking Zhang } else { 1005c6b6a421SHawking Zhang hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1006c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1007c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1008c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1009c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1010c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 1011c6b6a421SHawking Zhang } 1012c6b6a421SHawking Zhang 1013c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1014c6b6a421SHawking Zhang } 1015c6b6a421SHawking Zhang 1016c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1017c6b6a421SHawking Zhang enum amd_clockgating_state state) 1018c6b6a421SHawking Zhang { 1019c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1020c6b6a421SHawking Zhang 1021c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1022c6b6a421SHawking Zhang return 0; 1023c6b6a421SHawking Zhang 1024c6b6a421SHawking Zhang switch (adev->asic_type) { 1025c6b6a421SHawking Zhang case CHIP_NAVI10: 10265e71e011SXiaojie Yuan case CHIP_NAVI14: 10277e17e58bSXiaojie Yuan case CHIP_NAVI12: 1028117910edSLikun Gao case CHIP_SIENNA_CICHLID: 1029543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 1030bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1031a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1032bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1033a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1034c6b6a421SHawking Zhang nv_update_hdp_mem_power_gating(adev, 1035a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1036c6b6a421SHawking Zhang nv_update_hdp_clock_gating(adev, 1037a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1038c6b6a421SHawking Zhang break; 1039c6b6a421SHawking Zhang default: 1040c6b6a421SHawking Zhang break; 1041c6b6a421SHawking Zhang } 1042c6b6a421SHawking Zhang return 0; 1043c6b6a421SHawking Zhang } 1044c6b6a421SHawking Zhang 1045c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1046c6b6a421SHawking Zhang enum amd_powergating_state state) 1047c6b6a421SHawking Zhang { 1048c6b6a421SHawking Zhang /* TODO */ 1049c6b6a421SHawking Zhang return 0; 1050c6b6a421SHawking Zhang } 1051c6b6a421SHawking Zhang 1052c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1053c6b6a421SHawking Zhang { 1054c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1055c6b6a421SHawking Zhang uint32_t tmp; 1056c6b6a421SHawking Zhang 1057c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1058c6b6a421SHawking Zhang *flags = 0; 1059c6b6a421SHawking Zhang 1060bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1061c6b6a421SHawking Zhang 1062c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_MGCG */ 1063c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1064c6b6a421SHawking Zhang if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1065c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1066c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1067c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1068c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1069c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 1070c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1071c6b6a421SHawking Zhang 1072c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 1073c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1074c6b6a421SHawking Zhang if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 1075c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_LS; 1076c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1077c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_DS; 1078c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1079c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_SD; 1080c6b6a421SHawking Zhang 1081c6b6a421SHawking Zhang return; 1082c6b6a421SHawking Zhang } 1083c6b6a421SHawking Zhang 1084c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1085c6b6a421SHawking Zhang .name = "nv_common", 1086c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1087c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1088c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1089c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1090c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1091c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1092c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1093c6b6a421SHawking Zhang .resume = nv_common_resume, 1094c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1095c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1096c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1097c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1098c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1099c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1100c6b6a421SHawking Zhang }; 1101