1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 286f786950SAlex Deucher #include <drm/amdgpu_drm.h> 296f786950SAlex Deucher 30c6b6a421SHawking Zhang #include "amdgpu.h" 31c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 32c6b6a421SHawking Zhang #include "amdgpu_ih.h" 33c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 34c6b6a421SHawking Zhang #include "amdgpu_vce.h" 35c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 36c6b6a421SHawking Zhang #include "amdgpu_psp.h" 37c6b6a421SHawking Zhang #include "atom.h" 38c6b6a421SHawking Zhang #include "amd_pcie.h" 39c6b6a421SHawking Zhang 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 41c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 423967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 43c6b6a421SHawking Zhang 44c6b6a421SHawking Zhang #include "soc15.h" 45c6b6a421SHawking Zhang #include "soc15_common.h" 46c6b6a421SHawking Zhang #include "gmc_v10_0.h" 47c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 48c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 49bebc0762SHawking Zhang #include "nbio_v2_3.h" 50a7e91bd7SHuang Rui #include "nbio_v7_2.h" 51bf087285SLikun Gao #include "hdp_v5_0.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59b8f10585SLeo Liu #include "vcn_v3_0.h" 604d72dd12SLeo Liu #include "jpeg_v3_0.h" 61733ee71aSRyan Taylor #include "amdgpu_vkms.h" 62c6b6a421SHawking Zhang #include "mes_v10_1.h" 63b05b6903SJiange Zhao #include "mxgpu_nv.h" 640bf7f2dcSLikun Gao #include "smuio_v11_0.h" 650bf7f2dcSLikun Gao #include "smuio_v11_0_6.h" 66c6b6a421SHawking Zhang 67c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 68c6b6a421SHawking Zhang 693b246e8bSAlex Deucher /* Navi */ 703b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 713b246e8bSAlex Deucher { 729075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 739075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 743b246e8bSAlex Deucher }; 753b246e8bSAlex Deucher 763b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_encode = 773b246e8bSAlex Deucher { 783b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 793b246e8bSAlex Deucher .codec_array = nv_video_codecs_encode_array, 803b246e8bSAlex Deucher }; 813b246e8bSAlex Deucher 823b246e8bSAlex Deucher /* Navi1x */ 833b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 843b246e8bSAlex Deucher { 859075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 869075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 879075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 889075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 899075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 909075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 919075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 923b246e8bSAlex Deucher }; 933b246e8bSAlex Deucher 943b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_decode = 953b246e8bSAlex Deucher { 963b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 973b246e8bSAlex Deucher .codec_array = nv_video_codecs_decode_array, 983b246e8bSAlex Deucher }; 993b246e8bSAlex Deucher 1003b246e8bSAlex Deucher /* Sienna Cichlid */ 1013b246e8bSAlex Deucher static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 1023b246e8bSAlex Deucher { 1039075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 1049075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 1059075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 1069075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 1079075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 1089075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 1099075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 1109075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 1113b246e8bSAlex Deucher }; 1123b246e8bSAlex Deucher 1133b246e8bSAlex Deucher static const struct amdgpu_video_codecs sc_video_codecs_decode = 1143b246e8bSAlex Deucher { 1153b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 1163b246e8bSAlex Deucher .codec_array = sc_video_codecs_decode_array, 1173b246e8bSAlex Deucher }; 1183b246e8bSAlex Deucher 119ed9d2053SBokun Zhang /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 120ed9d2053SBokun Zhang static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 121ed9d2053SBokun Zhang { 1229075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 1239075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 124ed9d2053SBokun Zhang }; 125ed9d2053SBokun Zhang 126ed9d2053SBokun Zhang static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = 127ed9d2053SBokun Zhang { 1289075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 1299075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 1309075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 1319075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 1329075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 1339075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 1349075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 1359075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136ed9d2053SBokun Zhang }; 137ed9d2053SBokun Zhang 138ed9d2053SBokun Zhang static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 139ed9d2053SBokun Zhang { 140ed9d2053SBokun Zhang .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 141ed9d2053SBokun Zhang .codec_array = sriov_sc_video_codecs_encode_array, 142ed9d2053SBokun Zhang }; 143ed9d2053SBokun Zhang 144ed9d2053SBokun Zhang static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = 145ed9d2053SBokun Zhang { 146ed9d2053SBokun Zhang .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), 147ed9d2053SBokun Zhang .codec_array = sriov_sc_video_codecs_decode_array, 148ed9d2053SBokun Zhang }; 149ed9d2053SBokun Zhang 150b3a24461SVeerabadhran Gopalakrishnan /* Beige Goby*/ 151b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 152b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 153b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 154b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 155b3a24461SVeerabadhran Gopalakrishnan }; 156b3a24461SVeerabadhran Gopalakrishnan 157b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs bg_video_codecs_decode = { 158b3a24461SVeerabadhran Gopalakrishnan .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 159b3a24461SVeerabadhran Gopalakrishnan .codec_array = bg_video_codecs_decode_array, 160b3a24461SVeerabadhran Gopalakrishnan }; 161b3a24461SVeerabadhran Gopalakrishnan 162b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs bg_video_codecs_encode = { 163b3a24461SVeerabadhran Gopalakrishnan .codec_count = 0, 164b3a24461SVeerabadhran Gopalakrishnan .codec_array = NULL, 165b3a24461SVeerabadhran Gopalakrishnan }; 166b3a24461SVeerabadhran Gopalakrishnan 16755439817SVeerabadhran Gopalakrishnan /* Yellow Carp*/ 16855439817SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 16955439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 17055439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 17155439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 17255439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 17355439817SVeerabadhran Gopalakrishnan }; 17455439817SVeerabadhran Gopalakrishnan 17555439817SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs yc_video_codecs_decode = { 176f72ac409SVeerabadhran Gopalakrishnan .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 177f72ac409SVeerabadhran Gopalakrishnan .codec_array = yc_video_codecs_decode_array, 17855439817SVeerabadhran Gopalakrishnan }; 17955439817SVeerabadhran Gopalakrishnan 1803b246e8bSAlex Deucher static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 1813b246e8bSAlex Deucher const struct amdgpu_video_codecs **codecs) 1823b246e8bSAlex Deucher { 1833b246e8bSAlex Deucher switch (adev->asic_type) { 1843b246e8bSAlex Deucher case CHIP_SIENNA_CICHLID: 185ed9d2053SBokun Zhang if (amdgpu_sriov_vf(adev)) { 186ed9d2053SBokun Zhang if (encode) 187ed9d2053SBokun Zhang *codecs = &sriov_sc_video_codecs_encode; 188ed9d2053SBokun Zhang else 189ed9d2053SBokun Zhang *codecs = &sriov_sc_video_codecs_decode; 190ed9d2053SBokun Zhang } else { 191ed9d2053SBokun Zhang if (encode) 192ed9d2053SBokun Zhang *codecs = &nv_video_codecs_encode; 193ed9d2053SBokun Zhang else 194ed9d2053SBokun Zhang *codecs = &sc_video_codecs_decode; 195ed9d2053SBokun Zhang } 196ed9d2053SBokun Zhang return 0; 1973b246e8bSAlex Deucher case CHIP_NAVY_FLOUNDER: 1983b246e8bSAlex Deucher case CHIP_DIMGREY_CAVEFISH: 1993b246e8bSAlex Deucher case CHIP_VANGOGH: 2003b246e8bSAlex Deucher if (encode) 2013b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2023b246e8bSAlex Deucher else 2033b246e8bSAlex Deucher *codecs = &sc_video_codecs_decode; 2043b246e8bSAlex Deucher return 0; 20555439817SVeerabadhran Gopalakrishnan case CHIP_YELLOW_CARP: 20655439817SVeerabadhran Gopalakrishnan if (encode) 20755439817SVeerabadhran Gopalakrishnan *codecs = &nv_video_codecs_encode; 20855439817SVeerabadhran Gopalakrishnan else 20955439817SVeerabadhran Gopalakrishnan *codecs = &yc_video_codecs_decode; 21055439817SVeerabadhran Gopalakrishnan return 0; 211b3a24461SVeerabadhran Gopalakrishnan case CHIP_BEIGE_GOBY: 212b3a24461SVeerabadhran Gopalakrishnan if (encode) 213b3a24461SVeerabadhran Gopalakrishnan *codecs = &bg_video_codecs_encode; 214b3a24461SVeerabadhran Gopalakrishnan else 215b3a24461SVeerabadhran Gopalakrishnan *codecs = &bg_video_codecs_decode; 216b3a24461SVeerabadhran Gopalakrishnan return 0; 2173b246e8bSAlex Deucher case CHIP_NAVI10: 2183b246e8bSAlex Deucher case CHIP_NAVI14: 2193b246e8bSAlex Deucher case CHIP_NAVI12: 2203b246e8bSAlex Deucher if (encode) 2213b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2223b246e8bSAlex Deucher else 2233b246e8bSAlex Deucher *codecs = &nv_video_codecs_decode; 2243b246e8bSAlex Deucher return 0; 2253b246e8bSAlex Deucher default: 2263b246e8bSAlex Deucher return -EINVAL; 2273b246e8bSAlex Deucher } 2283b246e8bSAlex Deucher } 2293b246e8bSAlex Deucher 230c6b6a421SHawking Zhang /* 231c6b6a421SHawking Zhang * Indirect registers accessor 232c6b6a421SHawking Zhang */ 233c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 234c6b6a421SHawking Zhang { 235705a2b5bSHawking Zhang unsigned long address, data; 236bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 237bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 238c6b6a421SHawking Zhang 239705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg(adev, address, data, reg); 240c6b6a421SHawking Zhang } 241c6b6a421SHawking Zhang 242c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 243c6b6a421SHawking Zhang { 244705a2b5bSHawking Zhang unsigned long address, data; 245c6b6a421SHawking Zhang 246bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 247bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 248c6b6a421SHawking Zhang 249705a2b5bSHawking Zhang amdgpu_device_indirect_wreg(adev, address, data, reg, v); 250c6b6a421SHawking Zhang } 251c6b6a421SHawking Zhang 2524922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 2534922f1bcSJohn Clements { 254705a2b5bSHawking Zhang unsigned long address, data; 2554922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 2564922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 2574922f1bcSJohn Clements 258705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg64(adev, address, data, reg); 2594922f1bcSJohn Clements } 2604922f1bcSJohn Clements 2615de54343SHuang Rui static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 2625de54343SHuang Rui { 2635de54343SHuang Rui unsigned long flags, address, data; 2645de54343SHuang Rui u32 r; 2655de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 2665de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 2675de54343SHuang Rui 2685de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2695de54343SHuang Rui WREG32(address, reg * 4); 2705de54343SHuang Rui (void)RREG32(address); 2715de54343SHuang Rui r = RREG32(data); 2725de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2735de54343SHuang Rui return r; 2745de54343SHuang Rui } 2755de54343SHuang Rui 2764922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 2774922f1bcSJohn Clements { 278705a2b5bSHawking Zhang unsigned long address, data; 2794922f1bcSJohn Clements 2804922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 2814922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 2824922f1bcSJohn Clements 283705a2b5bSHawking Zhang amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 2844922f1bcSJohn Clements } 2854922f1bcSJohn Clements 2865de54343SHuang Rui static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 2875de54343SHuang Rui { 2885de54343SHuang Rui unsigned long flags, address, data; 2895de54343SHuang Rui 2905de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 2915de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 2925de54343SHuang Rui 2935de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2945de54343SHuang Rui WREG32(address, reg * 4); 2955de54343SHuang Rui (void)RREG32(address); 2965de54343SHuang Rui WREG32(data, v); 2975de54343SHuang Rui (void)RREG32(data); 2985de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2995de54343SHuang Rui } 3005de54343SHuang Rui 301c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 302c6b6a421SHawking Zhang { 303c6b6a421SHawking Zhang unsigned long flags, address, data; 304c6b6a421SHawking Zhang u32 r; 305c6b6a421SHawking Zhang 306c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 307c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 308c6b6a421SHawking Zhang 309c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 310c6b6a421SHawking Zhang WREG32(address, (reg)); 311c6b6a421SHawking Zhang r = RREG32(data); 312c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 313c6b6a421SHawking Zhang return r; 314c6b6a421SHawking Zhang } 315c6b6a421SHawking Zhang 316c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 317c6b6a421SHawking Zhang { 318c6b6a421SHawking Zhang unsigned long flags, address, data; 319c6b6a421SHawking Zhang 320c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 321c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 322c6b6a421SHawking Zhang 323c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 324c6b6a421SHawking Zhang WREG32(address, (reg)); 325c6b6a421SHawking Zhang WREG32(data, (v)); 326c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 327c6b6a421SHawking Zhang } 328c6b6a421SHawking Zhang 329c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 330c6b6a421SHawking Zhang { 331bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 332c6b6a421SHawking Zhang } 333c6b6a421SHawking Zhang 334c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 335c6b6a421SHawking Zhang { 336462a70d8STao Zhou return adev->clock.spll.reference_freq; 337c6b6a421SHawking Zhang } 338c6b6a421SHawking Zhang 339c6b6a421SHawking Zhang 340c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 341c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 342c6b6a421SHawking Zhang { 343c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 344c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 345c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 346c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 347c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 348c6b6a421SHawking Zhang 349f2958a8bSPeng Ju Zhou WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 350c6b6a421SHawking Zhang } 351c6b6a421SHawking Zhang 352c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 353c6b6a421SHawking Zhang { 354c6b6a421SHawking Zhang /* todo */ 355c6b6a421SHawking Zhang } 356c6b6a421SHawking Zhang 357c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 358c6b6a421SHawking Zhang { 359c6b6a421SHawking Zhang /* todo */ 360c6b6a421SHawking Zhang return false; 361c6b6a421SHawking Zhang } 362c6b6a421SHawking Zhang 363c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 364c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 365c6b6a421SHawking Zhang { 36629bc37b4SAlex Deucher u32 *dw_ptr; 36729bc37b4SAlex Deucher u32 i, length_dw; 3680bf7f2dcSLikun Gao u32 rom_index_offset, rom_data_offset; 36929bc37b4SAlex Deucher 37029bc37b4SAlex Deucher if (bios == NULL) 371c6b6a421SHawking Zhang return false; 37229bc37b4SAlex Deucher if (length_bytes == 0) 37329bc37b4SAlex Deucher return false; 37429bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 37529bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 37629bc37b4SAlex Deucher return false; 37729bc37b4SAlex Deucher 37829bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 37929bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 38029bc37b4SAlex Deucher 3810bf7f2dcSLikun Gao rom_index_offset = 3820bf7f2dcSLikun Gao adev->smuio.funcs->get_rom_index_offset(adev); 3830bf7f2dcSLikun Gao rom_data_offset = 3840bf7f2dcSLikun Gao adev->smuio.funcs->get_rom_data_offset(adev); 3850bf7f2dcSLikun Gao 38629bc37b4SAlex Deucher /* set rom index to 0 */ 3870bf7f2dcSLikun Gao WREG32(rom_index_offset, 0); 38829bc37b4SAlex Deucher /* read out the rom data */ 38929bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 3900bf7f2dcSLikun Gao dw_ptr[i] = RREG32(rom_data_offset); 39129bc37b4SAlex Deucher 39229bc37b4SAlex Deucher return true; 393c6b6a421SHawking Zhang } 394c6b6a421SHawking Zhang 395c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 396c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 397c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 398c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 399c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 400c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 401c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 402c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 403c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 404c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 405c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 406c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 407c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 408c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 409c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 410c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 411664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 412c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 413c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 414c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 415c6b6a421SHawking Zhang }; 416c6b6a421SHawking Zhang 417c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 418c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 419c6b6a421SHawking Zhang { 420c6b6a421SHawking Zhang uint32_t val; 421c6b6a421SHawking Zhang 422c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 423c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 424c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 425c6b6a421SHawking Zhang 426c6b6a421SHawking Zhang val = RREG32(reg_offset); 427c6b6a421SHawking Zhang 428c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 429c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 430c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 431c6b6a421SHawking Zhang return val; 432c6b6a421SHawking Zhang } 433c6b6a421SHawking Zhang 434c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 435c6b6a421SHawking Zhang bool indexed, u32 se_num, 436c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 437c6b6a421SHawking Zhang { 438c6b6a421SHawking Zhang if (indexed) { 439c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 440c6b6a421SHawking Zhang } else { 441c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 442c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 443c6b6a421SHawking Zhang return RREG32(reg_offset); 444c6b6a421SHawking Zhang } 445c6b6a421SHawking Zhang } 446c6b6a421SHawking Zhang 447c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 448c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 449c6b6a421SHawking Zhang { 450c6b6a421SHawking Zhang uint32_t i; 451c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 452c6b6a421SHawking Zhang 453c6b6a421SHawking Zhang *value = 0; 454c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 455c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 456fced3c3aSHuang Rui if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 457fced3c3aSHuang Rui reg_offset != 458c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 459c6b6a421SHawking Zhang continue; 460c6b6a421SHawking Zhang 461c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 462c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 463c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 464c6b6a421SHawking Zhang return 0; 465c6b6a421SHawking Zhang } 466c6b6a421SHawking Zhang return -EINVAL; 467c6b6a421SHawking Zhang } 468c6b6a421SHawking Zhang 469b913ec62SAlex Deucher static int nv_asic_mode2_reset(struct amdgpu_device *adev) 470b913ec62SAlex Deucher { 471b913ec62SAlex Deucher u32 i; 472b913ec62SAlex Deucher int ret = 0; 473b913ec62SAlex Deucher 474b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, true); 475b913ec62SAlex Deucher 476b913ec62SAlex Deucher /* disable BM */ 477b913ec62SAlex Deucher pci_clear_master(adev->pdev); 478b913ec62SAlex Deucher 479b913ec62SAlex Deucher amdgpu_device_cache_pci_state(adev->pdev); 480b913ec62SAlex Deucher 481b913ec62SAlex Deucher ret = amdgpu_dpm_mode2_reset(adev); 482b913ec62SAlex Deucher if (ret) 483b913ec62SAlex Deucher dev_err(adev->dev, "GPU mode2 reset failed\n"); 484b913ec62SAlex Deucher 485b913ec62SAlex Deucher amdgpu_device_load_pci_state(adev->pdev); 486b913ec62SAlex Deucher 487b913ec62SAlex Deucher /* wait for asic to come out of reset */ 488b913ec62SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 489b913ec62SAlex Deucher u32 memsize = adev->nbio.funcs->get_memsize(adev); 490b913ec62SAlex Deucher 491b913ec62SAlex Deucher if (memsize != 0xffffffff) 492b913ec62SAlex Deucher break; 493b913ec62SAlex Deucher udelay(1); 494b913ec62SAlex Deucher } 495b913ec62SAlex Deucher 496b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, false); 497b913ec62SAlex Deucher 498b913ec62SAlex Deucher return ret; 499b913ec62SAlex Deucher } 500b913ec62SAlex Deucher 5012ddc6c3eSAlex Deucher static enum amd_reset_method 5022ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 5032ddc6c3eSAlex Deucher { 504273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 50516086355SAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 506f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_BACO || 507f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_PCI) 508273da6ffSWenhui Sheng return amdgpu_reset_method; 509273da6ffSWenhui Sheng 510273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 511273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 512273da6ffSWenhui Sheng amdgpu_reset_method); 513273da6ffSWenhui Sheng 514ca6fd7a6SLikun Gao switch (adev->asic_type) { 51516086355SAlex Deucher case CHIP_VANGOGH: 5167d38d9dcSAaron Liu case CHIP_YELLOW_CARP: 51716086355SAlex Deucher return AMD_RESET_METHOD_MODE2; 518ca6fd7a6SLikun Gao case CHIP_SIENNA_CICHLID: 51922dd44f4SJiansong Chen case CHIP_NAVY_FLOUNDER: 52015ed44c0STao Zhou case CHIP_DIMGREY_CAVEFISH: 5215ed7715dSChengming Gui case CHIP_BEIGE_GOBY: 522ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 523ca6fd7a6SLikun Gao default: 524181e772fSEvan Quan if (amdgpu_dpm_is_baco_supported(adev)) 5252ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 5262ddc6c3eSAlex Deucher else 5272ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 5282ddc6c3eSAlex Deucher } 529ca6fd7a6SLikun Gao } 5302ddc6c3eSAlex Deucher 531c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 532c6b6a421SHawking Zhang { 533767acabdSKevin Wang int ret = 0; 534c6b6a421SHawking Zhang 53516086355SAlex Deucher switch (nv_asic_reset_method(adev)) { 536f172865aSAlex Deucher case AMD_RESET_METHOD_PCI: 537f172865aSAlex Deucher dev_info(adev->dev, "PCI reset\n"); 538f172865aSAlex Deucher ret = amdgpu_device_pci_reset(adev); 539f172865aSAlex Deucher break; 54016086355SAlex Deucher case AMD_RESET_METHOD_BACO: 54111043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 542181e772fSEvan Quan ret = amdgpu_dpm_baco_reset(adev); 54316086355SAlex Deucher break; 54416086355SAlex Deucher case AMD_RESET_METHOD_MODE2: 54516086355SAlex Deucher dev_info(adev->dev, "MODE2 reset\n"); 546b913ec62SAlex Deucher ret = nv_asic_mode2_reset(adev); 54716086355SAlex Deucher break; 54816086355SAlex Deucher default: 54911043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 5505c03e584SFeifei Xu ret = amdgpu_device_mode1_reset(adev); 55116086355SAlex Deucher break; 55211043b7aSAlex Deucher } 553767acabdSKevin Wang 554767acabdSKevin Wang return ret; 555c6b6a421SHawking Zhang } 556c6b6a421SHawking Zhang 557c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 558c6b6a421SHawking Zhang { 559c6b6a421SHawking Zhang /* todo */ 560c6b6a421SHawking Zhang return 0; 561c6b6a421SHawking Zhang } 562c6b6a421SHawking Zhang 563c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 564c6b6a421SHawking Zhang { 565c6b6a421SHawking Zhang /* todo */ 566c6b6a421SHawking Zhang return 0; 567c6b6a421SHawking Zhang } 568c6b6a421SHawking Zhang 569c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 570c6b6a421SHawking Zhang { 571c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 572c6b6a421SHawking Zhang return; 573c6b6a421SHawking Zhang 574c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 575c6b6a421SHawking Zhang return; 576c6b6a421SHawking Zhang 577c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 578c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 579c6b6a421SHawking Zhang return; 580c6b6a421SHawking Zhang 581c6b6a421SHawking Zhang /* todo */ 582c6b6a421SHawking Zhang } 583c6b6a421SHawking Zhang 584c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 585c6b6a421SHawking Zhang { 5860064b0ceSKenneth Feng if (!amdgpu_aspm) 587c6b6a421SHawking Zhang return; 588c6b6a421SHawking Zhang 5893273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 590e1edaeafSLikun Gao (adev->nbio.funcs->program_aspm)) 591e1edaeafSLikun Gao adev->nbio.funcs->program_aspm(adev); 592e1edaeafSLikun Gao 593c6b6a421SHawking Zhang } 594c6b6a421SHawking Zhang 595c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 596c6b6a421SHawking Zhang bool enable) 597c6b6a421SHawking Zhang { 598bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 599bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 600c6b6a421SHawking Zhang } 601c6b6a421SHawking Zhang 602*a1f62df7SAlex Deucher const struct amdgpu_ip_block_version nv_common_ip_block = 603c6b6a421SHawking Zhang { 604c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 605c6b6a421SHawking Zhang .major = 1, 606c6b6a421SHawking Zhang .minor = 0, 607c6b6a421SHawking Zhang .rev = 0, 608c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 609c6b6a421SHawking Zhang }; 610c6b6a421SHawking Zhang 611b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 612c6b6a421SHawking Zhang { 613b5c73856SXiaojie Yuan int r; 614b5c73856SXiaojie Yuan 615b5c73856SXiaojie Yuan if (amdgpu_discovery) { 616b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 617b5c73856SXiaojie Yuan if (r) { 618b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 619b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 620b5c73856SXiaojie Yuan goto legacy_init; 621b5c73856SXiaojie Yuan } 622b5c73856SXiaojie Yuan 6237bd939d0SLikun GAO amdgpu_discovery_harvest_ip(adev); 6247bd939d0SLikun GAO 625b5c73856SXiaojie Yuan return 0; 626b5c73856SXiaojie Yuan } 627b5c73856SXiaojie Yuan 628b5c73856SXiaojie Yuan legacy_init: 629c6b6a421SHawking Zhang switch (adev->asic_type) { 630c6b6a421SHawking Zhang case CHIP_NAVI10: 631c6b6a421SHawking Zhang navi10_reg_base_init(adev); 632c6b6a421SHawking Zhang break; 633a0f6d926SXiaojie Yuan case CHIP_NAVI14: 634a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 635a0f6d926SXiaojie Yuan break; 63603d0a073SXiaojie Yuan case CHIP_NAVI12: 63703d0a073SXiaojie Yuan navi12_reg_base_init(adev); 63803d0a073SXiaojie Yuan break; 639dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 640c8c959f6SJiansong Chen case CHIP_NAVY_FLOUNDER: 641dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 642dccdbf3fSLikun Gao break; 643026570e6SHuang Rui case CHIP_VANGOGH: 644026570e6SHuang Rui vangogh_reg_base_init(adev); 645026570e6SHuang Rui break; 646038d757bSTao Zhou case CHIP_DIMGREY_CAVEFISH: 647038d757bSTao Zhou dimgrey_cavefish_reg_base_init(adev); 648038d757bSTao Zhou break; 649fd5b4b44SChengming Gui case CHIP_BEIGE_GOBY: 650fd5b4b44SChengming Gui beige_goby_reg_base_init(adev); 651fd5b4b44SChengming Gui break; 652e7990721SAaron Liu case CHIP_YELLOW_CARP: 653e7990721SAaron Liu yellow_carp_reg_base_init(adev); 654e7990721SAaron Liu break; 65570839197STao Zhou case CHIP_CYAN_SKILLFISH: 65670839197STao Zhou cyan_skillfish_reg_base_init(adev); 65770839197STao Zhou break; 658c6b6a421SHawking Zhang default: 659c6b6a421SHawking Zhang return -EINVAL; 660c6b6a421SHawking Zhang } 661c6b6a421SHawking Zhang 662b5c73856SXiaojie Yuan return 0; 663b5c73856SXiaojie Yuan } 664b5c73856SXiaojie Yuan 665c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 666c1299461SWenhui Sheng { 667c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 668c1299461SWenhui Sheng } 669c1299461SWenhui Sheng 670b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 671b5c73856SXiaojie Yuan { 672b5c73856SXiaojie Yuan int r; 673b5c73856SXiaojie Yuan 674338b3cf0STao Zhou if (adev->asic_type == CHIP_CYAN_SKILLFISH) { 675338b3cf0STao Zhou adev->nbio.funcs = &nbio_v2_3_funcs; 676338b3cf0STao Zhou adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 677338b3cf0STao Zhou } else if (adev->flags & AMD_IS_APU) { 678a7e91bd7SHuang Rui adev->nbio.funcs = &nbio_v7_2_funcs; 679a7e91bd7SHuang Rui adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 680a7e91bd7SHuang Rui } else { 681122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 682122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 683a7e91bd7SHuang Rui } 684bf087285SLikun Gao adev->hdp.funcs = &hdp_v5_0_funcs; 685122078deSMonk Liu 6860bf7f2dcSLikun Gao if (adev->asic_type >= CHIP_SIENNA_CICHLID) 6870bf7f2dcSLikun Gao adev->smuio.funcs = &smuio_v11_0_6_funcs; 6880bf7f2dcSLikun Gao else 6890bf7f2dcSLikun Gao adev->smuio.funcs = &smuio_v11_0_funcs; 6900bf7f2dcSLikun Gao 691c652923aSJohn Clements if (adev->asic_type == CHIP_SIENNA_CICHLID) 692c652923aSJohn Clements adev->gmc.xgmi.supported = true; 693c652923aSJohn Clements 694b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 695b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 696b5c73856SXiaojie Yuan if (r) 697b5c73856SXiaojie Yuan return r; 698b5c73856SXiaojie Yuan 699c6b6a421SHawking Zhang switch (adev->asic_type) { 700c6b6a421SHawking Zhang case CHIP_NAVI10: 701d1daf850SAlex Deucher case CHIP_NAVI14: 702c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 703c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 704c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 705c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 706c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 7079530273eSEvan Quan !amdgpu_sriov_vf(adev)) 708c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 709c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 710733ee71aSRyan Taylor amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 711f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 7128301f6b9STianci.Yin else if (amdgpu_device_has_dc_support(adev)) 713b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 714f8a7976bSAlex Deucher #endif 715c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 716c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 717c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 7189530273eSEvan Quan !amdgpu_sriov_vf(adev)) 719c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 720c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 7215be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 722c6b6a421SHawking Zhang if (adev->enable_mes) 723c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 724c6b6a421SHawking Zhang break; 72544e9e7c9SXiaojie Yuan case CHIP_NAVI12: 72644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 72744e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 7282a4021ccSPeng Ju Zhou if (!amdgpu_sriov_vf(adev)) { 72944e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 7306b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 7312a4021ccSPeng Ju Zhou } else { 7322a4021ccSPeng Ju Zhou amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 7332a4021ccSPeng Ju Zhou amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 7342a4021ccSPeng Ju Zhou } 73579bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 7367f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 73779902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 738733ee71aSRyan Taylor amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 73920c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 740078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 741078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 74220c14ee1SPetr Cvek #endif 74344e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 74444e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 7457f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 7469530273eSEvan Quan !amdgpu_sriov_vf(adev)) 7477f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 7481fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 749fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 7505be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 75144e9e7c9SXiaojie Yuan break; 7522e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 7532e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 7540b3df16bSLikun Gao amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 7554aa7e6e0SYuBiao Wang if (!amdgpu_sriov_vf(adev)) { 756757b3af8SLikun Gao amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 75756304e72SLikun Gao if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 7585aa02350SLikun Gao amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 7594aa7e6e0SYuBiao Wang } else { 7604aa7e6e0SYuBiao Wang if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 7614aa7e6e0SYuBiao Wang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 7624aa7e6e0SYuBiao Wang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 7634aa7e6e0SYuBiao Wang } 764b07e5c60SLikun Gao if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 765acf2740fSJane Jian is_support_sw_smu(adev)) 766b07e5c60SLikun Gao amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 7679a986760SLikun Gao if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 768733ee71aSRyan Taylor amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 769464ab91aSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 770464ab91aSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 771464ab91aSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 772464ab91aSBhawanpreet Lakha #endif 773933c8a93SLikun Gao amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 774157e72e8SLikun Gao amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 775b8f10585SLeo Liu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 776c45fbe1bSJack Zhang if (!amdgpu_sriov_vf(adev)) 7774d72dd12SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 778a346ef86SJack Xiao if (adev->enable_mes) 779a346ef86SJack Xiao amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 7802e1ba10eSLikun Gao break; 7818515e0a4SJiansong Chen case CHIP_NAVY_FLOUNDER: 7828515e0a4SJiansong Chen amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 783fc8f07daSJiansong Chen amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 784026c396bSJiansong Chen amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 7857420eab2SJiansong Chen if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 7867420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 7877420eab2SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 7887420eab2SJiansong Chen is_support_sw_smu(adev)) 7897420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 7905404f073SJiansong Chen if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 791733ee71aSRyan Taylor amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 792a6c5308fSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 793a6c5308fSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 794a6c5308fSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 795a6c5308fSBhawanpreet Lakha #endif 796885eb3faSJiansong Chen amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 797df2d15dfSJiansong Chen amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 798290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 799290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 800f4497d10SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 801f4497d10SJiansong Chen is_support_sw_smu(adev)) 802f4497d10SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 8038515e0a4SJiansong Chen break; 80488edbad6SHuang Rui case CHIP_VANGOGH: 80588edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 80688edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 80788edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 808ed3b7353SHuang Rui if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 809ed3b7353SHuang Rui amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 810c821e0fbSHuang Rui amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 81188edbad6SHuang Rui if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 812733ee71aSRyan Taylor amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 81384b934bcSHuang Rui #if defined(CONFIG_DRM_AMD_DC) 81484b934bcSHuang Rui else if (amdgpu_device_has_dc_support(adev)) 81584b934bcSHuang Rui amdgpu_device_ip_block_add(adev, &dm_ip_block); 81684b934bcSHuang Rui #endif 81788edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 81888edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 819b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 820b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 82188edbad6SHuang Rui break; 8222aa92b12STao Zhou case CHIP_DIMGREY_CAVEFISH: 8232aa92b12STao Zhou amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 8243e02ad44STao Zhou amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 825771cc67eSTao Zhou amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 826aff39cdeSTao Zhou if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 827aff39cdeSTao Zhou amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 828aff39cdeSTao Zhou if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 829aff39cdeSTao Zhou is_support_sw_smu(adev)) 830aff39cdeSTao Zhou amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 83176a2d9eaSTao Zhou if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 832733ee71aSRyan Taylor amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 8337cc656e2STao Zhou #if defined(CONFIG_DRM_AMD_DC) 8347cc656e2STao Zhou else if (amdgpu_device_has_dc_support(adev)) 8357cc656e2STao Zhou amdgpu_device_ip_block_add(adev, &dm_ip_block); 8367cc656e2STao Zhou #endif 837feb6329cSTao Zhou amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 83801069226STao Zhou amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 8390afc770bSJames Zhu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 840be6b1cd3SJames Zhu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 8412aa92b12STao Zhou break; 842aa2caa2aSChengming Gui case CHIP_BEIGE_GOBY: 843aa2caa2aSChengming Gui amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 8442d527ea6SChengming Gui amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 845a1dede36SChengming Gui amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 846c0729819SChengming Gui if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 847c0729819SChengming Gui amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 848c0729819SChengming Gui if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 849c0729819SChengming Gui is_support_sw_smu(adev)) 850c0729819SChengming Gui amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 851898319caSChengming Gui amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 8528760403eSChengming Gui amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 8535663da86SChengming Gui if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 854733ee71aSRyan Taylor amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 855ddaed58bSAurabindo Pillai #if defined(CONFIG_DRM_AMD_DC) 856ddaed58bSAurabindo Pillai else if (amdgpu_device_has_dc_support(adev)) 857ddaed58bSAurabindo Pillai amdgpu_device_ip_block_add(adev, &dm_ip_block); 858ddaed58bSAurabindo Pillai #endif 8594d352669SChengming Gui if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 8604d352669SChengming Gui is_support_sw_smu(adev)) 8614d352669SChengming Gui amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 862f703d4b6SVeerabadhran Gopalakrishnan amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 863aa2caa2aSChengming Gui break; 8645c462ca9SAaron Liu case CHIP_YELLOW_CARP: 8655c462ca9SAaron Liu amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 8665c462ca9SAaron Liu amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 8675c462ca9SAaron Liu amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 868903bb18bSAaron Liu if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 869903bb18bSAaron Liu amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 870120a6db4SAaron Liu amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 8715c462ca9SAaron Liu if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 872733ee71aSRyan Taylor amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 8735c462ca9SAaron Liu amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 8745c462ca9SAaron Liu amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 875c8b73f7fSNicholas Kazlauskas if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 876733ee71aSRyan Taylor amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 877c8b73f7fSNicholas Kazlauskas #if defined(CONFIG_DRM_AMD_DC) 878c8b73f7fSNicholas Kazlauskas else if (amdgpu_device_has_dc_support(adev)) 879c8b73f7fSNicholas Kazlauskas amdgpu_device_ip_block_add(adev, &dm_ip_block); 880c8b73f7fSNicholas Kazlauskas #endif 881ee8d893fSJames Zhu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 882ee8d893fSJames Zhu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 8835c462ca9SAaron Liu break; 884f36fb5a0STao Zhou case CHIP_CYAN_SKILLFISH: 885f36fb5a0STao Zhou amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 886f36fb5a0STao Zhou amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 887f36fb5a0STao Zhou amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 888641df099SLang Yu if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 889641df099SLang Yu if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 8901c7916afSLang Yu amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 891641df099SLang Yu amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 8921c7916afSLang Yu } 893f36fb5a0STao Zhou if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 894733ee71aSRyan Taylor amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 8953f68c01bSZhan Liu #if defined(CONFIG_DRM_AMD_DC) 8963f68c01bSZhan Liu else if (amdgpu_device_has_dc_support(adev)) 8973f68c01bSZhan Liu amdgpu_device_ip_block_add(adev, &dm_ip_block); 8983f68c01bSZhan Liu #endif 899f36fb5a0STao Zhou amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 900f36fb5a0STao Zhou amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 901f36fb5a0STao Zhou break; 902c6b6a421SHawking Zhang default: 903c6b6a421SHawking Zhang return -EINVAL; 904c6b6a421SHawking Zhang } 905c6b6a421SHawking Zhang 906c6b6a421SHawking Zhang return 0; 907c6b6a421SHawking Zhang } 908c6b6a421SHawking Zhang 909c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 910c6b6a421SHawking Zhang { 911bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 912c6b6a421SHawking Zhang } 913c6b6a421SHawking Zhang 914c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 915c6b6a421SHawking Zhang { 916c6b6a421SHawking Zhang return true; 917c6b6a421SHawking Zhang } 918c6b6a421SHawking Zhang 919c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 920c6b6a421SHawking Zhang { 921c6b6a421SHawking Zhang u32 sol_reg; 922c6b6a421SHawking Zhang 923c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 924c6b6a421SHawking Zhang return false; 925c6b6a421SHawking Zhang 926c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 927c6b6a421SHawking Zhang * are already been loaded. 928c6b6a421SHawking Zhang */ 929c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 930c6b6a421SHawking Zhang if (sol_reg) 931c6b6a421SHawking Zhang return true; 9323967ae6dSAlex Deucher 933c6b6a421SHawking Zhang return false; 934c6b6a421SHawking Zhang } 935c6b6a421SHawking Zhang 9362af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 9372af81531SKevin Wang { 9382af81531SKevin Wang 9392af81531SKevin Wang /* TODO 9402af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 9412af81531SKevin Wang * */ 9422af81531SKevin Wang 9432af81531SKevin Wang return 0; 9442af81531SKevin Wang } 9452af81531SKevin Wang 946c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 947c6b6a421SHawking Zhang { 948c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 949c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 950c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 951c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 952c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 953c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 954c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 955c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 956c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 957c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 958c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 959c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 960c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 96120519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 962c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 963c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 964157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 965157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 966c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 967c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 968c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 969c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 970c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 971c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 972c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 973c6b6a421SHawking Zhang 974c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 975c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 976c6b6a421SHawking Zhang } 977c6b6a421SHawking Zhang 978a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 979a7173731SAlex Deucher { 980a7173731SAlex Deucher } 981a7173731SAlex Deucher 98227747293SEvan Quan static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 98327747293SEvan Quan bool enter) 98427747293SEvan Quan { 98527747293SEvan Quan if (enter) 98627747293SEvan Quan amdgpu_gfx_rlc_enter_safe_mode(adev); 98727747293SEvan Quan else 98827747293SEvan Quan amdgpu_gfx_rlc_exit_safe_mode(adev); 98927747293SEvan Quan 99027747293SEvan Quan if (adev->gfx.funcs->update_perfmon_mgcg) 99127747293SEvan Quan adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 99227747293SEvan Quan 9933273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 994e1edaeafSLikun Gao (adev->nbio.funcs->enable_aspm)) 99527747293SEvan Quan adev->nbio.funcs->enable_aspm(adev, !enter); 99627747293SEvan Quan 99727747293SEvan Quan return 0; 99827747293SEvan Quan } 99927747293SEvan Quan 1000c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 1001c6b6a421SHawking Zhang { 1002c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 1003c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 1004c6b6a421SHawking Zhang .read_register = &nv_read_register, 1005c6b6a421SHawking Zhang .reset = &nv_asic_reset, 10062ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 1007c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 1008c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 1009c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 1010c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 1011c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 1012c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 1013c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 1014c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 10152af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 1016181e772fSEvan Quan .supports_baco = &amdgpu_dpm_is_baco_supported, 1017a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 101827747293SEvan Quan .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 10193b246e8bSAlex Deucher .query_video_codecs = &nv_query_video_codecs, 1020c6b6a421SHawking Zhang }; 1021c6b6a421SHawking Zhang 1022c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 1023c6b6a421SHawking Zhang { 1024923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 1025c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1026c6b6a421SHawking Zhang 1027923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 1028923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 1029c6b6a421SHawking Zhang adev->smc_rreg = NULL; 1030c6b6a421SHawking Zhang adev->smc_wreg = NULL; 1031c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 1032c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 10334922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 10344922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 10355de54343SHuang Rui adev->pciep_rreg = &nv_pcie_port_rreg; 10365de54343SHuang Rui adev->pciep_wreg = &nv_pcie_port_wreg; 1037c6b6a421SHawking Zhang 1038c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 1039c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 1040c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 1041c6b6a421SHawking Zhang 1042c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 1043c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 1044c6b6a421SHawking Zhang 1045c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 1046c6b6a421SHawking Zhang 1047c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 1048c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 1049c6b6a421SHawking Zhang switch (adev->asic_type) { 1050c6b6a421SHawking Zhang case CHIP_NAVI10: 1051c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1052c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 1053c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 1054c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 1055c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 1056c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 1057c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 1058c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 1059c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 1060c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 1061c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 1062c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 1063099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 1064c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 1065c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 1066157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1067c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 1068099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 1069a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 1070c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 1071c6b6a421SHawking Zhang break; 10725e71e011SXiaojie Yuan case CHIP_NAVI14: 1073d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1074d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 1075d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 1076d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 1077d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 1078d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 1079d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 1080d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 1081d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 1082d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 1083d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 1084d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 1085099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 1086d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 1087d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 10880377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 1089099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 10900377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 109135ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 10925e71e011SXiaojie Yuan break; 109374b5e509SXiaojie Yuan case CHIP_NAVI12: 1094dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1095dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 1096dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 1097dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 10985211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 1099fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 11005211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 1101358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 1102358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 11038b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 11048b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 1105ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 1106ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 110765872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 1108099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 1109099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 1110c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 11115ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 1112099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 11131b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 1114df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 1115df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 1116df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 1117df5e984cSTiecheng Zhou */ 1118df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 1119df5e984cSTiecheng Zhou adev->rev_id = 0; 112074b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 112174b5e509SXiaojie Yuan break; 1122117910edSLikun Gao case CHIP_SIENNA_CICHLID: 112300194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 112400194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 11251d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 112600194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 112798f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 112800194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 1129ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 1130ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 11313a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 1132bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 1133bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 1134b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1135d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 1136b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 11371b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 11381b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 1139c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 1140c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 1141c45fbe1bSJack Zhang adev->cg_flags = 0; 1142c45fbe1bSJack Zhang adev->pg_flags = 0; 1143c45fbe1bSJack Zhang } 1144117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 1145117910edSLikun Gao break; 1146543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 114740582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 114840582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 11491d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 115040582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 115140582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 115292c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 115392c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 11544759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 11554759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 115685e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 115785e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 1158c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 115900740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 116047fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 116147fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 116247fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 1163543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 1164543aa259SJiansong Chen break; 1165543aa259SJiansong Chen 1166026570e6SHuang Rui case CHIP_VANGOGH: 116751a7e938SJinzhou.Su adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 116851a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_MGLS | 116951a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CP_LS | 117051a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_RLC_LS | 117151a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CGCG | 1172ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_CGLS | 1173ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_3D_CGCG | 117407f9c22fSBoyuan Zhang AMD_CG_SUPPORT_GFX_3D_CGLS | 11750ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_MGCG | 11760ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_LS | 1177a3964ec4SJinzhou.Su AMD_CG_SUPPORT_GFX_FGCG | 117807f9c22fSBoyuan Zhang AMD_CG_SUPPORT_VCN_MGCG | 1179ef9bcfdeSJinzhou Su AMD_CG_SUPPORT_SDMA_MGCG | 1180ec0f72cbSJinzhou Su AMD_CG_SUPPORT_SDMA_LS | 118107f9c22fSBoyuan Zhang AMD_CG_SUPPORT_JPEG_MGCG; 118207f9c22fSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 118307f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN | 118407f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 118507f9c22fSBoyuan Zhang AMD_PG_SUPPORT_JPEG; 1186c345c89bSHuang Rui if (adev->apu_flags & AMD_APU_IS_VANGOGH) 1187026570e6SHuang Rui adev->external_rev_id = adev->rev_id + 0x01; 1188026570e6SHuang Rui break; 1189550c58e0STao Zhou case CHIP_DIMGREY_CAVEFISH: 1190583e5a5eSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1191583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 11921d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 1193583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 1194583e5a5eSTao Zhou AMD_CG_SUPPORT_VCN_MGCG | 1195135333a0STao Zhou AMD_CG_SUPPORT_JPEG_MGCG | 1196135333a0STao Zhou AMD_CG_SUPPORT_MC_MGCG | 11972c70c332STao Zhou AMD_CG_SUPPORT_MC_LS | 11982c70c332STao Zhou AMD_CG_SUPPORT_HDP_MGCG | 11998e3bfb99STao Zhou AMD_CG_SUPPORT_HDP_LS | 12008e3bfb99STao Zhou AMD_CG_SUPPORT_IH_CG; 1201d5bc1579SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1202cc6161aaSJames Zhu AMD_PG_SUPPORT_VCN_DPG | 120373da8e86STao Zhou AMD_PG_SUPPORT_JPEG | 120473da8e86STao Zhou AMD_PG_SUPPORT_ATHUB | 120573da8e86STao Zhou AMD_PG_SUPPORT_MMHUB; 1206550c58e0STao Zhou adev->external_rev_id = adev->rev_id + 0x3c; 1207550c58e0STao Zhou break; 12088573035aSChengming Gui case CHIP_BEIGE_GOBY: 1209bc6bd46bSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1210bc6bd46bSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 1211d69d278fSTao Zhou AMD_CG_SUPPORT_GFX_CGLS | 12125d36b865STao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 12135d36b865STao Zhou AMD_CG_SUPPORT_MC_MGCG | 1214170c193fSTao Zhou AMD_CG_SUPPORT_MC_LS | 1215170c193fSTao Zhou AMD_CG_SUPPORT_HDP_MGCG | 1216a764bef3STao Zhou AMD_CG_SUPPORT_HDP_LS | 1217e47e4c0eSVeerabadhran Gopalakrishnan AMD_CG_SUPPORT_IH_CG | 1218e47e4c0eSVeerabadhran Gopalakrishnan AMD_CG_SUPPORT_VCN_MGCG; 1219f703d4b6SVeerabadhran Gopalakrishnan adev->pg_flags = AMD_PG_SUPPORT_VCN | 1220147de218STao Zhou AMD_PG_SUPPORT_VCN_DPG | 1221147de218STao Zhou AMD_PG_SUPPORT_ATHUB | 1222147de218STao Zhou AMD_PG_SUPPORT_MMHUB; 12238573035aSChengming Gui adev->external_rev_id = adev->rev_id + 0x46; 12248573035aSChengming Gui break; 1225e7990721SAaron Liu case CHIP_YELLOW_CARP: 12269c6c48e6SAaron Liu adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 12279c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_MGLS | 12289c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CGCG | 12299c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CGLS | 12309c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_3D_CGCG | 12319c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_3D_CGLS | 12329c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_RLC_LS | 12339c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CP_LS | 123483ae09b5SAaron Liu AMD_CG_SUPPORT_GFX_FGCG | 123583ae09b5SAaron Liu AMD_CG_SUPPORT_MC_MGCG | 1236f1e9aa65SAaron Liu AMD_CG_SUPPORT_MC_LS | 12376bd95572SAaron Liu AMD_CG_SUPPORT_SDMA_LS | 12386bd95572SAaron Liu AMD_CG_SUPPORT_HDP_MGCG | 1239b7dd14c7SAaron Liu AMD_CG_SUPPORT_HDP_LS | 1240b7dd14c7SAaron Liu AMD_CG_SUPPORT_ATHUB_MGCG | 1241db72c3faSAaron Liu AMD_CG_SUPPORT_ATHUB_LS | 1242948b1216SAaron Liu AMD_CG_SUPPORT_IH_CG | 1243948b1216SAaron Liu AMD_CG_SUPPORT_VCN_MGCG | 1244948b1216SAaron Liu AMD_CG_SUPPORT_JPEG_MGCG; 124554f4f6f3SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1246948b1216SAaron Liu AMD_PG_SUPPORT_VCN | 1247948b1216SAaron Liu AMD_PG_SUPPORT_VCN_DPG | 1248948b1216SAaron Liu AMD_PG_SUPPORT_JPEG; 1249e97c8d86SAaron Liu if (adev->pdev->device == 0x1681) 1250e97c8d86SAaron Liu adev->external_rev_id = adev->rev_id + 0x19; 1251e97c8d86SAaron Liu else 1252e7990721SAaron Liu adev->external_rev_id = adev->rev_id + 0x01; 1253e7990721SAaron Liu break; 1254b515937bSTao Zhou case CHIP_CYAN_SKILLFISH: 1255b515937bSTao Zhou adev->cg_flags = 0; 1256b515937bSTao Zhou adev->pg_flags = 0; 1257b515937bSTao Zhou adev->external_rev_id = adev->rev_id + 0x82; 1258b515937bSTao Zhou break; 1259c6b6a421SHawking Zhang default: 1260c6b6a421SHawking Zhang /* FIXME: not supported yet */ 1261c6b6a421SHawking Zhang return -EINVAL; 1262c6b6a421SHawking Zhang } 1263c6b6a421SHawking Zhang 12647bd939d0SLikun GAO if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 12657bd939d0SLikun GAO adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 12667bd939d0SLikun GAO AMD_PG_SUPPORT_VCN_DPG | 12677bd939d0SLikun GAO AMD_PG_SUPPORT_JPEG); 12687bd939d0SLikun GAO 1269b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 1270b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 1271b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 1272b05b6903SJiange Zhao } 1273b05b6903SJiange Zhao 1274c6b6a421SHawking Zhang return 0; 1275c6b6a421SHawking Zhang } 1276c6b6a421SHawking Zhang 1277c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 1278c6b6a421SHawking Zhang { 1279b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1280b05b6903SJiange Zhao 1281ed9d2053SBokun Zhang if (amdgpu_sriov_vf(adev)) { 1282b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 1283ed9d2053SBokun Zhang amdgpu_virt_update_sriov_video_codec(adev, 1284ed9d2053SBokun Zhang sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 1285ed9d2053SBokun Zhang sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); 1286ed9d2053SBokun Zhang } 1287b05b6903SJiange Zhao 1288c6b6a421SHawking Zhang return 0; 1289c6b6a421SHawking Zhang } 1290c6b6a421SHawking Zhang 1291c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 1292c6b6a421SHawking Zhang { 1293b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1294b05b6903SJiange Zhao 1295b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 1296b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 1297b05b6903SJiange Zhao 1298c6b6a421SHawking Zhang return 0; 1299c6b6a421SHawking Zhang } 1300c6b6a421SHawking Zhang 1301c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 1302c6b6a421SHawking Zhang { 1303c6b6a421SHawking Zhang return 0; 1304c6b6a421SHawking Zhang } 1305c6b6a421SHawking Zhang 1306c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 1307c6b6a421SHawking Zhang { 1308c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1309c6b6a421SHawking Zhang 13105a5da8aeSEvan Quan if (adev->nbio.funcs->apply_lc_spc_mode_wa) 13115a5da8aeSEvan Quan adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 13125a5da8aeSEvan Quan 1313adcf949eSEvan Quan if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1314adcf949eSEvan Quan adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1315adcf949eSEvan Quan 1316c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 1317c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 1318c6b6a421SHawking Zhang /* enable aspm */ 1319c6b6a421SHawking Zhang nv_program_aspm(adev); 1320c6b6a421SHawking Zhang /* setup nbio registers */ 1321bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 1322923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 1323923c087aSYong Zhao * for the purpose of expose those registers 1324923c087aSYong Zhao * to process space 1325923c087aSYong Zhao */ 1326923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 1327923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 1328c6b6a421SHawking Zhang /* enable the doorbell aperture */ 1329c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 1330c6b6a421SHawking Zhang 1331c6b6a421SHawking Zhang return 0; 1332c6b6a421SHawking Zhang } 1333c6b6a421SHawking Zhang 1334c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 1335c6b6a421SHawking Zhang { 1336c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1337c6b6a421SHawking Zhang 1338c6b6a421SHawking Zhang /* disable the doorbell aperture */ 1339c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 1340c6b6a421SHawking Zhang 1341c6b6a421SHawking Zhang return 0; 1342c6b6a421SHawking Zhang } 1343c6b6a421SHawking Zhang 1344c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 1345c6b6a421SHawking Zhang { 1346c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1347c6b6a421SHawking Zhang 1348c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 1349c6b6a421SHawking Zhang } 1350c6b6a421SHawking Zhang 1351c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 1352c6b6a421SHawking Zhang { 1353c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1354c6b6a421SHawking Zhang 1355c6b6a421SHawking Zhang return nv_common_hw_init(adev); 1356c6b6a421SHawking Zhang } 1357c6b6a421SHawking Zhang 1358c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 1359c6b6a421SHawking Zhang { 1360c6b6a421SHawking Zhang return true; 1361c6b6a421SHawking Zhang } 1362c6b6a421SHawking Zhang 1363c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 1364c6b6a421SHawking Zhang { 1365c6b6a421SHawking Zhang return 0; 1366c6b6a421SHawking Zhang } 1367c6b6a421SHawking Zhang 1368c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 1369c6b6a421SHawking Zhang { 1370c6b6a421SHawking Zhang return 0; 1371c6b6a421SHawking Zhang } 1372c6b6a421SHawking Zhang 1373c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1374c6b6a421SHawking Zhang enum amd_clockgating_state state) 1375c6b6a421SHawking Zhang { 1376c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1377c6b6a421SHawking Zhang 1378c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1379c6b6a421SHawking Zhang return 0; 1380c6b6a421SHawking Zhang 1381c6b6a421SHawking Zhang switch (adev->asic_type) { 1382c6b6a421SHawking Zhang case CHIP_NAVI10: 13835e71e011SXiaojie Yuan case CHIP_NAVI14: 13847e17e58bSXiaojie Yuan case CHIP_NAVI12: 1385117910edSLikun Gao case CHIP_SIENNA_CICHLID: 1386543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 1387550c58e0STao Zhou case CHIP_DIMGREY_CAVEFISH: 13888573035aSChengming Gui case CHIP_BEIGE_GOBY: 1389bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1390a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1391bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1392a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1393bf087285SLikun Gao adev->hdp.funcs->update_clock_gating(adev, 1394a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 13951001f2a1SLikun Gao adev->smuio.funcs->update_rom_clock_gating(adev, 13961001f2a1SLikun Gao state == AMD_CG_STATE_GATE); 1397c6b6a421SHawking Zhang break; 1398c6b6a421SHawking Zhang default: 1399c6b6a421SHawking Zhang break; 1400c6b6a421SHawking Zhang } 1401c6b6a421SHawking Zhang return 0; 1402c6b6a421SHawking Zhang } 1403c6b6a421SHawking Zhang 1404c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1405c6b6a421SHawking Zhang enum amd_powergating_state state) 1406c6b6a421SHawking Zhang { 1407c6b6a421SHawking Zhang /* TODO */ 1408c6b6a421SHawking Zhang return 0; 1409c6b6a421SHawking Zhang } 1410c6b6a421SHawking Zhang 1411c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1412c6b6a421SHawking Zhang { 1413c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1414c6b6a421SHawking Zhang 1415c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1416c6b6a421SHawking Zhang *flags = 0; 1417c6b6a421SHawking Zhang 1418bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1419c6b6a421SHawking Zhang 1420bf087285SLikun Gao adev->hdp.funcs->get_clock_gating_state(adev, flags); 1421c6b6a421SHawking Zhang 14221001f2a1SLikun Gao adev->smuio.funcs->get_clock_gating_state(adev, flags); 14231001f2a1SLikun Gao 1424c6b6a421SHawking Zhang return; 1425c6b6a421SHawking Zhang } 1426c6b6a421SHawking Zhang 1427c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1428c6b6a421SHawking Zhang .name = "nv_common", 1429c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1430c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1431c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1432c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1433c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1434c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1435c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1436c6b6a421SHawking Zhang .resume = nv_common_resume, 1437c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1438c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1439c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1440c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1441c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1442c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1443c6b6a421SHawking Zhang }; 1444