1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 286f786950SAlex Deucher #include <drm/amdgpu_drm.h> 296f786950SAlex Deucher 30c6b6a421SHawking Zhang #include "amdgpu.h" 31c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 32c6b6a421SHawking Zhang #include "amdgpu_ih.h" 33c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 34c6b6a421SHawking Zhang #include "amdgpu_vce.h" 35c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 36c6b6a421SHawking Zhang #include "amdgpu_psp.h" 37c6b6a421SHawking Zhang #include "atom.h" 38c6b6a421SHawking Zhang #include "amd_pcie.h" 39c6b6a421SHawking Zhang 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 41c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 423967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 43c6b6a421SHawking Zhang 44c6b6a421SHawking Zhang #include "soc15.h" 45c6b6a421SHawking Zhang #include "soc15_common.h" 46c6b6a421SHawking Zhang #include "gmc_v10_0.h" 47c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 48c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 49bebc0762SHawking Zhang #include "nbio_v2_3.h" 50a7e91bd7SHuang Rui #include "nbio_v7_2.h" 51bf087285SLikun Gao #include "hdp_v5_0.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59b8f10585SLeo Liu #include "vcn_v3_0.h" 604d72dd12SLeo Liu #include "jpeg_v3_0.h" 61733ee71aSRyan Taylor #include "amdgpu_vkms.h" 62c6b6a421SHawking Zhang #include "mes_v10_1.h" 63b05b6903SJiange Zhao #include "mxgpu_nv.h" 640bf7f2dcSLikun Gao #include "smuio_v11_0.h" 650bf7f2dcSLikun Gao #include "smuio_v11_0_6.h" 66c6b6a421SHawking Zhang 67c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 68c6b6a421SHawking Zhang 693b246e8bSAlex Deucher /* Navi */ 703b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 713b246e8bSAlex Deucher { 729075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 739075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 743b246e8bSAlex Deucher }; 753b246e8bSAlex Deucher 763b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_encode = 773b246e8bSAlex Deucher { 783b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 793b246e8bSAlex Deucher .codec_array = nv_video_codecs_encode_array, 803b246e8bSAlex Deucher }; 813b246e8bSAlex Deucher 823b246e8bSAlex Deucher /* Navi1x */ 833b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 843b246e8bSAlex Deucher { 859075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 869075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 879075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 889075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 899075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 909075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 919075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 923b246e8bSAlex Deucher }; 933b246e8bSAlex Deucher 943b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_decode = 953b246e8bSAlex Deucher { 963b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 973b246e8bSAlex Deucher .codec_array = nv_video_codecs_decode_array, 983b246e8bSAlex Deucher }; 993b246e8bSAlex Deucher 1003b246e8bSAlex Deucher /* Sienna Cichlid */ 1013b246e8bSAlex Deucher static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 1023b246e8bSAlex Deucher { 1039075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 1049075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 1059075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 1069075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 1079075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 1089075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 1099075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 1109075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 1113b246e8bSAlex Deucher }; 1123b246e8bSAlex Deucher 1133b246e8bSAlex Deucher static const struct amdgpu_video_codecs sc_video_codecs_decode = 1143b246e8bSAlex Deucher { 1153b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 1163b246e8bSAlex Deucher .codec_array = sc_video_codecs_decode_array, 1173b246e8bSAlex Deucher }; 1183b246e8bSAlex Deucher 119ed9d2053SBokun Zhang /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 120ed9d2053SBokun Zhang static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 121ed9d2053SBokun Zhang { 1229075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 1239075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 124ed9d2053SBokun Zhang }; 125ed9d2053SBokun Zhang 126ed9d2053SBokun Zhang static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = 127ed9d2053SBokun Zhang { 1289075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 1299075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 1309075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 1319075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 1329075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 1339075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 1349075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 1359075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136ed9d2053SBokun Zhang }; 137ed9d2053SBokun Zhang 138ed9d2053SBokun Zhang static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 139ed9d2053SBokun Zhang { 140ed9d2053SBokun Zhang .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 141ed9d2053SBokun Zhang .codec_array = sriov_sc_video_codecs_encode_array, 142ed9d2053SBokun Zhang }; 143ed9d2053SBokun Zhang 144ed9d2053SBokun Zhang static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = 145ed9d2053SBokun Zhang { 146ed9d2053SBokun Zhang .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), 147ed9d2053SBokun Zhang .codec_array = sriov_sc_video_codecs_decode_array, 148ed9d2053SBokun Zhang }; 149ed9d2053SBokun Zhang 150b3a24461SVeerabadhran Gopalakrishnan /* Beige Goby*/ 151b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 152b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 153b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 154b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 155b3a24461SVeerabadhran Gopalakrishnan }; 156b3a24461SVeerabadhran Gopalakrishnan 157b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs bg_video_codecs_decode = { 158b3a24461SVeerabadhran Gopalakrishnan .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 159b3a24461SVeerabadhran Gopalakrishnan .codec_array = bg_video_codecs_decode_array, 160b3a24461SVeerabadhran Gopalakrishnan }; 161b3a24461SVeerabadhran Gopalakrishnan 162b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs bg_video_codecs_encode = { 163b3a24461SVeerabadhran Gopalakrishnan .codec_count = 0, 164b3a24461SVeerabadhran Gopalakrishnan .codec_array = NULL, 165b3a24461SVeerabadhran Gopalakrishnan }; 166b3a24461SVeerabadhran Gopalakrishnan 16755439817SVeerabadhran Gopalakrishnan /* Yellow Carp*/ 16855439817SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 16955439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 17055439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 17155439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 17255439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 17355439817SVeerabadhran Gopalakrishnan }; 17455439817SVeerabadhran Gopalakrishnan 17555439817SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs yc_video_codecs_decode = { 176f72ac409SVeerabadhran Gopalakrishnan .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 177f72ac409SVeerabadhran Gopalakrishnan .codec_array = yc_video_codecs_decode_array, 17855439817SVeerabadhran Gopalakrishnan }; 17955439817SVeerabadhran Gopalakrishnan 1803b246e8bSAlex Deucher static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 1813b246e8bSAlex Deucher const struct amdgpu_video_codecs **codecs) 1823b246e8bSAlex Deucher { 1831d789535SAlex Deucher switch (adev->ip_versions[UVD_HWIP][0]) { 1843e67f4f2SAlex Deucher case IP_VERSION(3, 0, 0): 1854d395f93SGuchun Chen case IP_VERSION(3, 0, 64): 186da3b36a2SJane Jian case IP_VERSION(3, 0, 192): 187ed9d2053SBokun Zhang if (amdgpu_sriov_vf(adev)) { 188ed9d2053SBokun Zhang if (encode) 189ed9d2053SBokun Zhang *codecs = &sriov_sc_video_codecs_encode; 190ed9d2053SBokun Zhang else 191ed9d2053SBokun Zhang *codecs = &sriov_sc_video_codecs_decode; 192ed9d2053SBokun Zhang } else { 193ed9d2053SBokun Zhang if (encode) 194ed9d2053SBokun Zhang *codecs = &nv_video_codecs_encode; 195ed9d2053SBokun Zhang else 196ed9d2053SBokun Zhang *codecs = &sc_video_codecs_decode; 197ed9d2053SBokun Zhang } 198ed9d2053SBokun Zhang return 0; 1993e67f4f2SAlex Deucher case IP_VERSION(3, 0, 16): 2003e67f4f2SAlex Deucher case IP_VERSION(3, 0, 2): 2013b246e8bSAlex Deucher if (encode) 2023b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2033b246e8bSAlex Deucher else 2043b246e8bSAlex Deucher *codecs = &sc_video_codecs_decode; 2053b246e8bSAlex Deucher return 0; 2063e67f4f2SAlex Deucher case IP_VERSION(3, 1, 1): 207afc2f276SBoyuan Zhang case IP_VERSION(3, 1, 2): 20855439817SVeerabadhran Gopalakrishnan if (encode) 20955439817SVeerabadhran Gopalakrishnan *codecs = &nv_video_codecs_encode; 21055439817SVeerabadhran Gopalakrishnan else 21155439817SVeerabadhran Gopalakrishnan *codecs = &yc_video_codecs_decode; 21255439817SVeerabadhran Gopalakrishnan return 0; 2133e67f4f2SAlex Deucher case IP_VERSION(3, 0, 33): 214b3a24461SVeerabadhran Gopalakrishnan if (encode) 215b3a24461SVeerabadhran Gopalakrishnan *codecs = &bg_video_codecs_encode; 216b3a24461SVeerabadhran Gopalakrishnan else 217b3a24461SVeerabadhran Gopalakrishnan *codecs = &bg_video_codecs_decode; 218b3a24461SVeerabadhran Gopalakrishnan return 0; 2193e67f4f2SAlex Deucher case IP_VERSION(2, 0, 0): 2203e67f4f2SAlex Deucher case IP_VERSION(2, 0, 2): 2213b246e8bSAlex Deucher if (encode) 2223b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2233b246e8bSAlex Deucher else 2243b246e8bSAlex Deucher *codecs = &nv_video_codecs_decode; 2253b246e8bSAlex Deucher return 0; 2263b246e8bSAlex Deucher default: 2273b246e8bSAlex Deucher return -EINVAL; 2283b246e8bSAlex Deucher } 2293b246e8bSAlex Deucher } 2303b246e8bSAlex Deucher 231c6b6a421SHawking Zhang /* 232c6b6a421SHawking Zhang * Indirect registers accessor 233c6b6a421SHawking Zhang */ 234c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 235c6b6a421SHawking Zhang { 236705a2b5bSHawking Zhang unsigned long address, data; 237bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 238bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 239c6b6a421SHawking Zhang 240705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg(adev, address, data, reg); 241c6b6a421SHawking Zhang } 242c6b6a421SHawking Zhang 243c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 244c6b6a421SHawking Zhang { 245705a2b5bSHawking Zhang unsigned long address, data; 246c6b6a421SHawking Zhang 247bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 248bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 249c6b6a421SHawking Zhang 250705a2b5bSHawking Zhang amdgpu_device_indirect_wreg(adev, address, data, reg, v); 251c6b6a421SHawking Zhang } 252c6b6a421SHawking Zhang 2534922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 2544922f1bcSJohn Clements { 255705a2b5bSHawking Zhang unsigned long address, data; 2564922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 2574922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 2584922f1bcSJohn Clements 259705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg64(adev, address, data, reg); 2604922f1bcSJohn Clements } 2614922f1bcSJohn Clements 2624922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 2634922f1bcSJohn Clements { 264705a2b5bSHawking Zhang unsigned long address, data; 2654922f1bcSJohn Clements 2664922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 2674922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 2684922f1bcSJohn Clements 269705a2b5bSHawking Zhang amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 2704922f1bcSJohn Clements } 2714922f1bcSJohn Clements 272c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 273c6b6a421SHawking Zhang { 274c6b6a421SHawking Zhang unsigned long flags, address, data; 275c6b6a421SHawking Zhang u32 r; 276c6b6a421SHawking Zhang 277c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 278c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 279c6b6a421SHawking Zhang 280c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 281c6b6a421SHawking Zhang WREG32(address, (reg)); 282c6b6a421SHawking Zhang r = RREG32(data); 283c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 284c6b6a421SHawking Zhang return r; 285c6b6a421SHawking Zhang } 286c6b6a421SHawking Zhang 287c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 288c6b6a421SHawking Zhang { 289c6b6a421SHawking Zhang unsigned long flags, address, data; 290c6b6a421SHawking Zhang 291c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 292c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 293c6b6a421SHawking Zhang 294c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 295c6b6a421SHawking Zhang WREG32(address, (reg)); 296c6b6a421SHawking Zhang WREG32(data, (v)); 297c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 298c6b6a421SHawking Zhang } 299c6b6a421SHawking Zhang 300c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 301c6b6a421SHawking Zhang { 302bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 303c6b6a421SHawking Zhang } 304c6b6a421SHawking Zhang 305c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 306c6b6a421SHawking Zhang { 307462a70d8STao Zhou return adev->clock.spll.reference_freq; 308c6b6a421SHawking Zhang } 309c6b6a421SHawking Zhang 310c6b6a421SHawking Zhang 311c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 312c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 313c6b6a421SHawking Zhang { 314c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 315c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 316c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 317c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 318c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 319c6b6a421SHawking Zhang 320f2958a8bSPeng Ju Zhou WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 321c6b6a421SHawking Zhang } 322c6b6a421SHawking Zhang 323c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 324c6b6a421SHawking Zhang { 325c6b6a421SHawking Zhang /* todo */ 326c6b6a421SHawking Zhang } 327c6b6a421SHawking Zhang 328c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 329c6b6a421SHawking Zhang { 330c6b6a421SHawking Zhang /* todo */ 331c6b6a421SHawking Zhang return false; 332c6b6a421SHawking Zhang } 333c6b6a421SHawking Zhang 334c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 335c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 336c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 337c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 338c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 339c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 340c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 341c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 342c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 343c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 344c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 345c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 346c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 347c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 348c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 349c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 350664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 351c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 352c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 353c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 354c6b6a421SHawking Zhang }; 355c6b6a421SHawking Zhang 356c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 357c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 358c6b6a421SHawking Zhang { 359c6b6a421SHawking Zhang uint32_t val; 360c6b6a421SHawking Zhang 361c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 362c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 363c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 364c6b6a421SHawking Zhang 365c6b6a421SHawking Zhang val = RREG32(reg_offset); 366c6b6a421SHawking Zhang 367c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 368c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 369c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 370c6b6a421SHawking Zhang return val; 371c6b6a421SHawking Zhang } 372c6b6a421SHawking Zhang 373c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 374c6b6a421SHawking Zhang bool indexed, u32 se_num, 375c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 376c6b6a421SHawking Zhang { 377c6b6a421SHawking Zhang if (indexed) { 378c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 379c6b6a421SHawking Zhang } else { 380c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 381c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 382c6b6a421SHawking Zhang return RREG32(reg_offset); 383c6b6a421SHawking Zhang } 384c6b6a421SHawking Zhang } 385c6b6a421SHawking Zhang 386c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 387c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 388c6b6a421SHawking Zhang { 389c6b6a421SHawking Zhang uint32_t i; 390c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 391c6b6a421SHawking Zhang 392c6b6a421SHawking Zhang *value = 0; 393c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 394c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 395fced3c3aSHuang Rui if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 396fced3c3aSHuang Rui reg_offset != 397c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 398c6b6a421SHawking Zhang continue; 399c6b6a421SHawking Zhang 400c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 401c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 402c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 403c6b6a421SHawking Zhang return 0; 404c6b6a421SHawking Zhang } 405c6b6a421SHawking Zhang return -EINVAL; 406c6b6a421SHawking Zhang } 407c6b6a421SHawking Zhang 408b913ec62SAlex Deucher static int nv_asic_mode2_reset(struct amdgpu_device *adev) 409b913ec62SAlex Deucher { 410b913ec62SAlex Deucher u32 i; 411b913ec62SAlex Deucher int ret = 0; 412b913ec62SAlex Deucher 413b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, true); 414b913ec62SAlex Deucher 415b913ec62SAlex Deucher /* disable BM */ 416b913ec62SAlex Deucher pci_clear_master(adev->pdev); 417b913ec62SAlex Deucher 418b913ec62SAlex Deucher amdgpu_device_cache_pci_state(adev->pdev); 419b913ec62SAlex Deucher 420b913ec62SAlex Deucher ret = amdgpu_dpm_mode2_reset(adev); 421b913ec62SAlex Deucher if (ret) 422b913ec62SAlex Deucher dev_err(adev->dev, "GPU mode2 reset failed\n"); 423b913ec62SAlex Deucher 424b913ec62SAlex Deucher amdgpu_device_load_pci_state(adev->pdev); 425b913ec62SAlex Deucher 426b913ec62SAlex Deucher /* wait for asic to come out of reset */ 427b913ec62SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 428b913ec62SAlex Deucher u32 memsize = adev->nbio.funcs->get_memsize(adev); 429b913ec62SAlex Deucher 430b913ec62SAlex Deucher if (memsize != 0xffffffff) 431b913ec62SAlex Deucher break; 432b913ec62SAlex Deucher udelay(1); 433b913ec62SAlex Deucher } 434b913ec62SAlex Deucher 435b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, false); 436b913ec62SAlex Deucher 437b913ec62SAlex Deucher return ret; 438b913ec62SAlex Deucher } 439b913ec62SAlex Deucher 4402ddc6c3eSAlex Deucher static enum amd_reset_method 4412ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 4422ddc6c3eSAlex Deucher { 443273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 44416086355SAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 445f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_BACO || 446f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_PCI) 447273da6ffSWenhui Sheng return amdgpu_reset_method; 448273da6ffSWenhui Sheng 449273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 450273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 451273da6ffSWenhui Sheng amdgpu_reset_method); 452273da6ffSWenhui Sheng 4531d789535SAlex Deucher switch (adev->ip_versions[MP1_HWIP][0]) { 4543e67f4f2SAlex Deucher case IP_VERSION(11, 5, 0): 4553e67f4f2SAlex Deucher case IP_VERSION(13, 0, 1): 4563e67f4f2SAlex Deucher case IP_VERSION(13, 0, 3): 45750439060SYifan Zhang case IP_VERSION(13, 0, 5): 45816086355SAlex Deucher return AMD_RESET_METHOD_MODE2; 4593e67f4f2SAlex Deucher case IP_VERSION(11, 0, 7): 4603e67f4f2SAlex Deucher case IP_VERSION(11, 0, 11): 4613e67f4f2SAlex Deucher case IP_VERSION(11, 0, 12): 4623e67f4f2SAlex Deucher case IP_VERSION(11, 0, 13): 463ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 464ca6fd7a6SLikun Gao default: 465181e772fSEvan Quan if (amdgpu_dpm_is_baco_supported(adev)) 4662ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 4672ddc6c3eSAlex Deucher else 4682ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 4692ddc6c3eSAlex Deucher } 470ca6fd7a6SLikun Gao } 4712ddc6c3eSAlex Deucher 472c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 473c6b6a421SHawking Zhang { 474767acabdSKevin Wang int ret = 0; 475c6b6a421SHawking Zhang 47616086355SAlex Deucher switch (nv_asic_reset_method(adev)) { 477f172865aSAlex Deucher case AMD_RESET_METHOD_PCI: 478f172865aSAlex Deucher dev_info(adev->dev, "PCI reset\n"); 479f172865aSAlex Deucher ret = amdgpu_device_pci_reset(adev); 480f172865aSAlex Deucher break; 48116086355SAlex Deucher case AMD_RESET_METHOD_BACO: 48211043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 483181e772fSEvan Quan ret = amdgpu_dpm_baco_reset(adev); 48416086355SAlex Deucher break; 48516086355SAlex Deucher case AMD_RESET_METHOD_MODE2: 48616086355SAlex Deucher dev_info(adev->dev, "MODE2 reset\n"); 487b913ec62SAlex Deucher ret = nv_asic_mode2_reset(adev); 48816086355SAlex Deucher break; 48916086355SAlex Deucher default: 49011043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 4915c03e584SFeifei Xu ret = amdgpu_device_mode1_reset(adev); 49216086355SAlex Deucher break; 49311043b7aSAlex Deucher } 494767acabdSKevin Wang 495767acabdSKevin Wang return ret; 496c6b6a421SHawking Zhang } 497c6b6a421SHawking Zhang 498c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 499c6b6a421SHawking Zhang { 500c6b6a421SHawking Zhang /* todo */ 501c6b6a421SHawking Zhang return 0; 502c6b6a421SHawking Zhang } 503c6b6a421SHawking Zhang 504c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 505c6b6a421SHawking Zhang { 506c6b6a421SHawking Zhang /* todo */ 507c6b6a421SHawking Zhang return 0; 508c6b6a421SHawking Zhang } 509c6b6a421SHawking Zhang 510c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 511c6b6a421SHawking Zhang { 512c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 513c6b6a421SHawking Zhang return; 514c6b6a421SHawking Zhang 515c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 516c6b6a421SHawking Zhang return; 517c6b6a421SHawking Zhang 518c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 519c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 520c6b6a421SHawking Zhang return; 521c6b6a421SHawking Zhang 522c6b6a421SHawking Zhang /* todo */ 523c6b6a421SHawking Zhang } 524c6b6a421SHawking Zhang 525c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 526c6b6a421SHawking Zhang { 5270ab5d711SMario Limonciello if (!amdgpu_device_should_use_aspm(adev)) 528c6b6a421SHawking Zhang return; 529c6b6a421SHawking Zhang 5303273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 531e1edaeafSLikun Gao (adev->nbio.funcs->program_aspm)) 532e1edaeafSLikun Gao adev->nbio.funcs->program_aspm(adev); 533e1edaeafSLikun Gao 534c6b6a421SHawking Zhang } 535c6b6a421SHawking Zhang 536c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 537c6b6a421SHawking Zhang bool enable) 538c6b6a421SHawking Zhang { 539bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 540bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 541c6b6a421SHawking Zhang } 542c6b6a421SHawking Zhang 543a1f62df7SAlex Deucher const struct amdgpu_ip_block_version nv_common_ip_block = 544c6b6a421SHawking Zhang { 545c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 546c6b6a421SHawking Zhang .major = 1, 547c6b6a421SHawking Zhang .minor = 0, 548c6b6a421SHawking Zhang .rev = 0, 549c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 550c6b6a421SHawking Zhang }; 551c6b6a421SHawking Zhang 552c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 553c1299461SWenhui Sheng { 554c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 555c1299461SWenhui Sheng } 556c1299461SWenhui Sheng 557c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 558c6b6a421SHawking Zhang { 559bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 560c6b6a421SHawking Zhang } 561c6b6a421SHawking Zhang 562c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 563c6b6a421SHawking Zhang { 564c6b6a421SHawking Zhang return true; 565c6b6a421SHawking Zhang } 566c6b6a421SHawking Zhang 567c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 568c6b6a421SHawking Zhang { 569c6b6a421SHawking Zhang u32 sol_reg; 570c6b6a421SHawking Zhang 571c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 572c6b6a421SHawking Zhang return false; 573c6b6a421SHawking Zhang 574c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 575c6b6a421SHawking Zhang * are already been loaded. 576c6b6a421SHawking Zhang */ 577c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 578c6b6a421SHawking Zhang if (sol_reg) 579c6b6a421SHawking Zhang return true; 5803967ae6dSAlex Deucher 581c6b6a421SHawking Zhang return false; 582c6b6a421SHawking Zhang } 583c6b6a421SHawking Zhang 5842af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 5852af81531SKevin Wang { 5862af81531SKevin Wang 5872af81531SKevin Wang /* TODO 5882af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 5892af81531SKevin Wang * */ 5902af81531SKevin Wang 5912af81531SKevin Wang return 0; 5922af81531SKevin Wang } 5932af81531SKevin Wang 594c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 595c6b6a421SHawking Zhang { 596c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 597c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 598c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 599c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 600c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 601c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 602c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 603c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 604c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 605c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 606c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 607c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 608c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 60920519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 610c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 611c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 612157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 613157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 614c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 615c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 616c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 617c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 618c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 619c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 620c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 621c6b6a421SHawking Zhang 622c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 623c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 624c6b6a421SHawking Zhang } 625c6b6a421SHawking Zhang 626a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 627a7173731SAlex Deucher { 628a7173731SAlex Deucher } 629a7173731SAlex Deucher 63027747293SEvan Quan static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 63127747293SEvan Quan bool enter) 63227747293SEvan Quan { 63327747293SEvan Quan if (enter) 63427747293SEvan Quan amdgpu_gfx_rlc_enter_safe_mode(adev); 63527747293SEvan Quan else 63627747293SEvan Quan amdgpu_gfx_rlc_exit_safe_mode(adev); 63727747293SEvan Quan 63827747293SEvan Quan if (adev->gfx.funcs->update_perfmon_mgcg) 63927747293SEvan Quan adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 64027747293SEvan Quan 6413273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 642d01899d3SMario Limonciello (adev->nbio.funcs->enable_aspm) && 643d01899d3SMario Limonciello amdgpu_device_should_use_aspm(adev)) 64427747293SEvan Quan adev->nbio.funcs->enable_aspm(adev, !enter); 64527747293SEvan Quan 64627747293SEvan Quan return 0; 64727747293SEvan Quan } 64827747293SEvan Quan 649c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 650c6b6a421SHawking Zhang { 651c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 65204022982SHawking Zhang .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 653c6b6a421SHawking Zhang .read_register = &nv_read_register, 654c6b6a421SHawking Zhang .reset = &nv_asic_reset, 6552ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 656c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 657c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 658c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 659c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 660c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 661c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 662c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 663c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 6642af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 665181e772fSEvan Quan .supports_baco = &amdgpu_dpm_is_baco_supported, 666a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 66727747293SEvan Quan .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 6683b246e8bSAlex Deucher .query_video_codecs = &nv_query_video_codecs, 669c6b6a421SHawking Zhang }; 670c6b6a421SHawking Zhang 671c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 672c6b6a421SHawking Zhang { 673923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 674c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 675c6b6a421SHawking Zhang 676d3a21f7eSFelix Kuehling if (!amdgpu_sriov_vf(adev)) { 677923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 678923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 679d3a21f7eSFelix Kuehling } 680c6b6a421SHawking Zhang adev->smc_rreg = NULL; 681c6b6a421SHawking Zhang adev->smc_wreg = NULL; 682c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 683c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 6844922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 6854922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 68686700a40SXiaojian Du adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 68786700a40SXiaojian Du adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 688c6b6a421SHawking Zhang 689c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 690c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 691c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 692c6b6a421SHawking Zhang 693c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 694c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 695c6b6a421SHawking Zhang 696c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 697c6b6a421SHawking Zhang 698c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 699c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 7003e67f4f2SAlex Deucher /* TODO: split the GC and PG flags based on the relevant IP version for which 7013e67f4f2SAlex Deucher * they are relevant. 7023e67f4f2SAlex Deucher */ 7031d789535SAlex Deucher switch (adev->ip_versions[GC_HWIP][0]) { 7043e67f4f2SAlex Deucher case IP_VERSION(10, 1, 10): 705c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 706c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 707c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 708c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 709c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 710c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 711c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 712c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 713c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 714c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 715c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 716c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 717099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 718c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 719c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 720157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 721c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 722099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 723a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 724c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 725c6b6a421SHawking Zhang break; 7263e67f4f2SAlex Deucher case IP_VERSION(10, 1, 1): 727d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 728d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 729d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 730d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 731d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 732d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 733d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 734d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 735d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 736d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 737d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 738d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 739099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 740d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 741d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 7420377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 743099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7440377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 74535ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 7465e71e011SXiaojie Yuan break; 7473e67f4f2SAlex Deucher case IP_VERSION(10, 1, 2): 748dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 749dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 750dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 751dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 7525211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 753fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 7545211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 755358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 756358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 7578b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 7588b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 759ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 760ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 76165872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 762099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 763099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 764c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 7655ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 766099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7671b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 768df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 769df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 770df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 771df5e984cSTiecheng Zhou */ 772df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 773df5e984cSTiecheng Zhou adev->rev_id = 0; 77474b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 77574b5e509SXiaojie Yuan break; 7763e67f4f2SAlex Deucher case IP_VERSION(10, 3, 0): 77700194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 77800194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 7791d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 78000194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 78198f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 78200194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 783ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 784ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 7853a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 786bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 787bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 788b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 789d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 790b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 7911b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 7921b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 793c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 794c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 795c45fbe1bSJack Zhang adev->cg_flags = 0; 796c45fbe1bSJack Zhang adev->pg_flags = 0; 797c45fbe1bSJack Zhang } 798117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 799117910edSLikun Gao break; 8003e67f4f2SAlex Deucher case IP_VERSION(10, 3, 2): 80140582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 80240582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 8031d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 80440582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 80540582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 80692c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 80792c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 8084759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 8094759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 81085e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 81185e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 812c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 81300740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 81447fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 81547fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 81647fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 817543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 818543aa259SJiansong Chen break; 8193e67f4f2SAlex Deucher case IP_VERSION(10, 3, 1): 82051a7e938SJinzhou.Su adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 82151a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_MGLS | 82251a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CP_LS | 82351a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_RLC_LS | 82451a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CGCG | 825ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_CGLS | 826ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_3D_CGCG | 82707f9c22fSBoyuan Zhang AMD_CG_SUPPORT_GFX_3D_CGLS | 8280ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_MGCG | 8290ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_LS | 830a3964ec4SJinzhou.Su AMD_CG_SUPPORT_GFX_FGCG | 83107f9c22fSBoyuan Zhang AMD_CG_SUPPORT_VCN_MGCG | 832ef9bcfdeSJinzhou Su AMD_CG_SUPPORT_SDMA_MGCG | 833ec0f72cbSJinzhou Su AMD_CG_SUPPORT_SDMA_LS | 83407f9c22fSBoyuan Zhang AMD_CG_SUPPORT_JPEG_MGCG; 83507f9c22fSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 83607f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN | 83707f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 83807f9c22fSBoyuan Zhang AMD_PG_SUPPORT_JPEG; 839c345c89bSHuang Rui if (adev->apu_flags & AMD_APU_IS_VANGOGH) 840026570e6SHuang Rui adev->external_rev_id = adev->rev_id + 0x01; 841026570e6SHuang Rui break; 8423e67f4f2SAlex Deucher case IP_VERSION(10, 3, 4): 843583e5a5eSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 844583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 8451d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 846583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 847583e5a5eSTao Zhou AMD_CG_SUPPORT_VCN_MGCG | 848135333a0STao Zhou AMD_CG_SUPPORT_JPEG_MGCG | 849135333a0STao Zhou AMD_CG_SUPPORT_MC_MGCG | 8502c70c332STao Zhou AMD_CG_SUPPORT_MC_LS | 8512c70c332STao Zhou AMD_CG_SUPPORT_HDP_MGCG | 8528e3bfb99STao Zhou AMD_CG_SUPPORT_HDP_LS | 8538e3bfb99STao Zhou AMD_CG_SUPPORT_IH_CG; 854d5bc1579SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_VCN | 855cc6161aaSJames Zhu AMD_PG_SUPPORT_VCN_DPG | 85673da8e86STao Zhou AMD_PG_SUPPORT_JPEG | 85773da8e86STao Zhou AMD_PG_SUPPORT_ATHUB | 85873da8e86STao Zhou AMD_PG_SUPPORT_MMHUB; 859550c58e0STao Zhou adev->external_rev_id = adev->rev_id + 0x3c; 860550c58e0STao Zhou break; 8613e67f4f2SAlex Deucher case IP_VERSION(10, 3, 5): 862bc6bd46bSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 863bc6bd46bSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 864d69d278fSTao Zhou AMD_CG_SUPPORT_GFX_CGLS | 8655d36b865STao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 8665d36b865STao Zhou AMD_CG_SUPPORT_MC_MGCG | 867170c193fSTao Zhou AMD_CG_SUPPORT_MC_LS | 868170c193fSTao Zhou AMD_CG_SUPPORT_HDP_MGCG | 869a764bef3STao Zhou AMD_CG_SUPPORT_HDP_LS | 870e47e4c0eSVeerabadhran Gopalakrishnan AMD_CG_SUPPORT_IH_CG | 871e47e4c0eSVeerabadhran Gopalakrishnan AMD_CG_SUPPORT_VCN_MGCG; 872f703d4b6SVeerabadhran Gopalakrishnan adev->pg_flags = AMD_PG_SUPPORT_VCN | 873147de218STao Zhou AMD_PG_SUPPORT_VCN_DPG | 874147de218STao Zhou AMD_PG_SUPPORT_ATHUB | 875147de218STao Zhou AMD_PG_SUPPORT_MMHUB; 8768573035aSChengming Gui adev->external_rev_id = adev->rev_id + 0x46; 8778573035aSChengming Gui break; 8783e67f4f2SAlex Deucher case IP_VERSION(10, 3, 3): 8799c6c48e6SAaron Liu adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 8809c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_MGLS | 8819c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CGCG | 8829c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CGLS | 8839c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_3D_CGCG | 8849c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_3D_CGLS | 8859c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_RLC_LS | 8869c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CP_LS | 88783ae09b5SAaron Liu AMD_CG_SUPPORT_GFX_FGCG | 88883ae09b5SAaron Liu AMD_CG_SUPPORT_MC_MGCG | 889f1e9aa65SAaron Liu AMD_CG_SUPPORT_MC_LS | 8906bd95572SAaron Liu AMD_CG_SUPPORT_SDMA_LS | 8916bd95572SAaron Liu AMD_CG_SUPPORT_HDP_MGCG | 892b7dd14c7SAaron Liu AMD_CG_SUPPORT_HDP_LS | 893b7dd14c7SAaron Liu AMD_CG_SUPPORT_ATHUB_MGCG | 894db72c3faSAaron Liu AMD_CG_SUPPORT_ATHUB_LS | 895948b1216SAaron Liu AMD_CG_SUPPORT_IH_CG | 896948b1216SAaron Liu AMD_CG_SUPPORT_VCN_MGCG | 897948b1216SAaron Liu AMD_CG_SUPPORT_JPEG_MGCG; 89854f4f6f3SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 899948b1216SAaron Liu AMD_PG_SUPPORT_VCN | 900948b1216SAaron Liu AMD_PG_SUPPORT_VCN_DPG | 901948b1216SAaron Liu AMD_PG_SUPPORT_JPEG; 902e97c8d86SAaron Liu if (adev->pdev->device == 0x1681) 9035efacdf0SAaron Liu adev->external_rev_id = 0x20; 904e97c8d86SAaron Liu else 905e7990721SAaron Liu adev->external_rev_id = adev->rev_id + 0x01; 906e7990721SAaron Liu break; 9073e67f4f2SAlex Deucher case IP_VERSION(10, 1, 3): 908f9ed188dSLang Yu case IP_VERSION(10, 1, 4): 909b515937bSTao Zhou adev->cg_flags = 0; 910b515937bSTao Zhou adev->pg_flags = 0; 911b515937bSTao Zhou adev->external_rev_id = adev->rev_id + 0x82; 912b515937bSTao Zhou break; 9131957f27dSYifan Zhang case IP_VERSION(10, 3, 6): 91450e14a62SYifan Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 91550e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_MGLS | 91650e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_CGCG | 91750e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_CGLS | 91850e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_3D_CGCG | 91950e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_3D_CGLS | 92050e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_RLC_LS | 92150e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_CP_LS | 92250e14a62SYifan Zhang AMD_CG_SUPPORT_GFX_FGCG | 92350e14a62SYifan Zhang AMD_CG_SUPPORT_MC_MGCG | 92450e14a62SYifan Zhang AMD_CG_SUPPORT_MC_LS | 92550e14a62SYifan Zhang AMD_CG_SUPPORT_SDMA_LS | 92650e14a62SYifan Zhang AMD_CG_SUPPORT_HDP_MGCG | 92750e14a62SYifan Zhang AMD_CG_SUPPORT_HDP_LS | 92850e14a62SYifan Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 92950e14a62SYifan Zhang AMD_CG_SUPPORT_ATHUB_LS | 93087b5e77fSBoyuan Zhang AMD_CG_SUPPORT_IH_CG | 93187b5e77fSBoyuan Zhang AMD_CG_SUPPORT_VCN_MGCG | 93287b5e77fSBoyuan Zhang AMD_CG_SUPPORT_JPEG_MGCG; 93387b5e77fSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 93487b5e77fSBoyuan Zhang AMD_PG_SUPPORT_VCN | 93587b5e77fSBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 93687b5e77fSBoyuan Zhang AMD_PG_SUPPORT_JPEG; 9371957f27dSYifan Zhang adev->external_rev_id = adev->rev_id + 0x01; 9381957f27dSYifan Zhang break; 939b67f00e0SPrike Liang case IP_VERSION(10, 3, 7): 940*9e148e8cSPrike Liang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 941*9e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_MGLS | 942*9e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_CGCG | 943*9e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_CGLS | 944*9e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_3D_CGCG | 945*9e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_3D_CGLS | 946*9e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_RLC_LS | 947*9e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_CP_LS | 948*9e148e8cSPrike Liang AMD_CG_SUPPORT_GFX_FGCG; 94935c27d95SSathishkumar S adev->pg_flags = AMD_PG_SUPPORT_VCN | 95035c27d95SSathishkumar S AMD_PG_SUPPORT_VCN_DPG | 95135c27d95SSathishkumar S AMD_PG_SUPPORT_JPEG; 952b67f00e0SPrike Liang adev->external_rev_id = adev->rev_id + 0x01; 953b67f00e0SPrike Liang break; 954c6b6a421SHawking Zhang default: 955c6b6a421SHawking Zhang /* FIXME: not supported yet */ 956c6b6a421SHawking Zhang return -EINVAL; 957c6b6a421SHawking Zhang } 958c6b6a421SHawking Zhang 9597bd939d0SLikun GAO if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 9607bd939d0SLikun GAO adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 9617bd939d0SLikun GAO AMD_PG_SUPPORT_VCN_DPG | 9627bd939d0SLikun GAO AMD_PG_SUPPORT_JPEG); 9637bd939d0SLikun GAO 964b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 965b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 966b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 967b05b6903SJiange Zhao } 968b05b6903SJiange Zhao 969c6b6a421SHawking Zhang return 0; 970c6b6a421SHawking Zhang } 971c6b6a421SHawking Zhang 972c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 973c6b6a421SHawking Zhang { 974b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 975b05b6903SJiange Zhao 976ed9d2053SBokun Zhang if (amdgpu_sriov_vf(adev)) { 977b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 978ed9d2053SBokun Zhang amdgpu_virt_update_sriov_video_codec(adev, 979ed9d2053SBokun Zhang sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 980ed9d2053SBokun Zhang sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); 981ed9d2053SBokun Zhang } 982b05b6903SJiange Zhao 983c6b6a421SHawking Zhang return 0; 984c6b6a421SHawking Zhang } 985c6b6a421SHawking Zhang 986c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 987c6b6a421SHawking Zhang { 988b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 989b05b6903SJiange Zhao 990b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 991b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 992b05b6903SJiange Zhao 993c6b6a421SHawking Zhang return 0; 994c6b6a421SHawking Zhang } 995c6b6a421SHawking Zhang 996c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 997c6b6a421SHawking Zhang { 998c6b6a421SHawking Zhang return 0; 999c6b6a421SHawking Zhang } 1000c6b6a421SHawking Zhang 1001c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 1002c6b6a421SHawking Zhang { 1003c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1004c6b6a421SHawking Zhang 10055a5da8aeSEvan Quan if (adev->nbio.funcs->apply_lc_spc_mode_wa) 10065a5da8aeSEvan Quan adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 10075a5da8aeSEvan Quan 1008adcf949eSEvan Quan if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1009adcf949eSEvan Quan adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1010adcf949eSEvan Quan 1011c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 1012c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 1013c6b6a421SHawking Zhang /* enable aspm */ 1014c6b6a421SHawking Zhang nv_program_aspm(adev); 1015c6b6a421SHawking Zhang /* setup nbio registers */ 1016bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 1017923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 1018923c087aSYong Zhao * for the purpose of expose those registers 1019923c087aSYong Zhao * to process space 1020923c087aSYong Zhao */ 1021d3a21f7eSFelix Kuehling if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1022923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 1023c6b6a421SHawking Zhang /* enable the doorbell aperture */ 1024c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 1025c6b6a421SHawking Zhang 1026c6b6a421SHawking Zhang return 0; 1027c6b6a421SHawking Zhang } 1028c6b6a421SHawking Zhang 1029c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 1030c6b6a421SHawking Zhang { 1031c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1032c6b6a421SHawking Zhang 1033c6b6a421SHawking Zhang /* disable the doorbell aperture */ 1034c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 1035c6b6a421SHawking Zhang 1036c6b6a421SHawking Zhang return 0; 1037c6b6a421SHawking Zhang } 1038c6b6a421SHawking Zhang 1039c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 1040c6b6a421SHawking Zhang { 1041c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1042c6b6a421SHawking Zhang 1043c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 1044c6b6a421SHawking Zhang } 1045c6b6a421SHawking Zhang 1046c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 1047c6b6a421SHawking Zhang { 1048c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1049c6b6a421SHawking Zhang 1050c6b6a421SHawking Zhang return nv_common_hw_init(adev); 1051c6b6a421SHawking Zhang } 1052c6b6a421SHawking Zhang 1053c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 1054c6b6a421SHawking Zhang { 1055c6b6a421SHawking Zhang return true; 1056c6b6a421SHawking Zhang } 1057c6b6a421SHawking Zhang 1058c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 1059c6b6a421SHawking Zhang { 1060c6b6a421SHawking Zhang return 0; 1061c6b6a421SHawking Zhang } 1062c6b6a421SHawking Zhang 1063c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 1064c6b6a421SHawking Zhang { 1065c6b6a421SHawking Zhang return 0; 1066c6b6a421SHawking Zhang } 1067c6b6a421SHawking Zhang 1068c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1069c6b6a421SHawking Zhang enum amd_clockgating_state state) 1070c6b6a421SHawking Zhang { 1071c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1072c6b6a421SHawking Zhang 1073c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1074c6b6a421SHawking Zhang return 0; 1075c6b6a421SHawking Zhang 10761d789535SAlex Deucher switch (adev->ip_versions[NBIO_HWIP][0]) { 10773e67f4f2SAlex Deucher case IP_VERSION(2, 3, 0): 10783e67f4f2SAlex Deucher case IP_VERSION(2, 3, 1): 10793e67f4f2SAlex Deucher case IP_VERSION(2, 3, 2): 10803e67f4f2SAlex Deucher case IP_VERSION(3, 3, 0): 10813e67f4f2SAlex Deucher case IP_VERSION(3, 3, 1): 10823e67f4f2SAlex Deucher case IP_VERSION(3, 3, 2): 10833e67f4f2SAlex Deucher case IP_VERSION(3, 3, 3): 1084bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1085a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1086bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1087a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1088bf087285SLikun Gao adev->hdp.funcs->update_clock_gating(adev, 1089a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 10901001f2a1SLikun Gao adev->smuio.funcs->update_rom_clock_gating(adev, 10911001f2a1SLikun Gao state == AMD_CG_STATE_GATE); 1092c6b6a421SHawking Zhang break; 1093c6b6a421SHawking Zhang default: 1094c6b6a421SHawking Zhang break; 1095c6b6a421SHawking Zhang } 1096c6b6a421SHawking Zhang return 0; 1097c6b6a421SHawking Zhang } 1098c6b6a421SHawking Zhang 1099c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1100c6b6a421SHawking Zhang enum amd_powergating_state state) 1101c6b6a421SHawking Zhang { 1102c6b6a421SHawking Zhang /* TODO */ 1103c6b6a421SHawking Zhang return 0; 1104c6b6a421SHawking Zhang } 1105c6b6a421SHawking Zhang 1106c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1107c6b6a421SHawking Zhang { 1108c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1109c6b6a421SHawking Zhang 1110c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1111c6b6a421SHawking Zhang *flags = 0; 1112c6b6a421SHawking Zhang 1113bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1114c6b6a421SHawking Zhang 1115bf087285SLikun Gao adev->hdp.funcs->get_clock_gating_state(adev, flags); 1116c6b6a421SHawking Zhang 11171001f2a1SLikun Gao adev->smuio.funcs->get_clock_gating_state(adev, flags); 11181001f2a1SLikun Gao 1119c6b6a421SHawking Zhang return; 1120c6b6a421SHawking Zhang } 1121c6b6a421SHawking Zhang 1122c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1123c6b6a421SHawking Zhang .name = "nv_common", 1124c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1125c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1126c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1127c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1128c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1129c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1130c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1131c6b6a421SHawking Zhang .resume = nv_common_resume, 1132c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1133c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1134c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1135c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1136c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1137c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1138c6b6a421SHawking Zhang }; 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