1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 28c6b6a421SHawking Zhang #include "amdgpu.h" 29c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 30c6b6a421SHawking Zhang #include "amdgpu_ih.h" 31c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 32c6b6a421SHawking Zhang #include "amdgpu_vce.h" 33c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 34c6b6a421SHawking Zhang #include "amdgpu_psp.h" 35767acabdSKevin Wang #include "amdgpu_smu.h" 36c6b6a421SHawking Zhang #include "atom.h" 37c6b6a421SHawking Zhang #include "amd_pcie.h" 38c6b6a421SHawking Zhang 39c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 41c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_offset.h" 42c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_sh_mask.h" 4329bc37b4SAlex Deucher #include "smuio/smuio_11_0_0_offset.h" 443967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 45c6b6a421SHawking Zhang 46c6b6a421SHawking Zhang #include "soc15.h" 47c6b6a421SHawking Zhang #include "soc15_common.h" 48c6b6a421SHawking Zhang #include "gmc_v10_0.h" 49c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 50c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 51bebc0762SHawking Zhang #include "nbio_v2_3.h" 52a7e91bd7SHuang Rui #include "nbio_v7_2.h" 53c6b6a421SHawking Zhang #include "nv.h" 54c6b6a421SHawking Zhang #include "navi10_ih.h" 55c6b6a421SHawking Zhang #include "gfx_v10_0.h" 56c6b6a421SHawking Zhang #include "sdma_v5_0.h" 57157e72e8SLikun Gao #include "sdma_v5_2.h" 58c6b6a421SHawking Zhang #include "vcn_v2_0.h" 595be45a26SLeo Liu #include "jpeg_v2_0.h" 60b8f10585SLeo Liu #include "vcn_v3_0.h" 614d72dd12SLeo Liu #include "jpeg_v3_0.h" 62c6b6a421SHawking Zhang #include "dce_virtual.h" 63c6b6a421SHawking Zhang #include "mes_v10_1.h" 64b05b6903SJiange Zhao #include "mxgpu_nv.h" 65c6b6a421SHawking Zhang 66c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 67c6b6a421SHawking Zhang 68c6b6a421SHawking Zhang /* 69c6b6a421SHawking Zhang * Indirect registers accessor 70c6b6a421SHawking Zhang */ 71c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 72c6b6a421SHawking Zhang { 73705a2b5bSHawking Zhang unsigned long address, data; 74bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 75bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 76c6b6a421SHawking Zhang 77705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg(adev, address, data, reg); 78c6b6a421SHawking Zhang } 79c6b6a421SHawking Zhang 80c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 81c6b6a421SHawking Zhang { 82705a2b5bSHawking Zhang unsigned long address, data; 83c6b6a421SHawking Zhang 84bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 85bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 86c6b6a421SHawking Zhang 87705a2b5bSHawking Zhang amdgpu_device_indirect_wreg(adev, address, data, reg, v); 88c6b6a421SHawking Zhang } 89c6b6a421SHawking Zhang 904922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 914922f1bcSJohn Clements { 92705a2b5bSHawking Zhang unsigned long address, data; 934922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 944922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 954922f1bcSJohn Clements 96705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg64(adev, address, data, reg); 974922f1bcSJohn Clements } 984922f1bcSJohn Clements 995de54343SHuang Rui static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 1005de54343SHuang Rui { 1015de54343SHuang Rui unsigned long flags, address, data; 1025de54343SHuang Rui u32 r; 1035de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 1045de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 1055de54343SHuang Rui 1065de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1075de54343SHuang Rui WREG32(address, reg * 4); 1085de54343SHuang Rui (void)RREG32(address); 1095de54343SHuang Rui r = RREG32(data); 1105de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1115de54343SHuang Rui return r; 1125de54343SHuang Rui } 1135de54343SHuang Rui 1144922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 1154922f1bcSJohn Clements { 116705a2b5bSHawking Zhang unsigned long address, data; 1174922f1bcSJohn Clements 1184922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 1194922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 1204922f1bcSJohn Clements 121705a2b5bSHawking Zhang amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 1224922f1bcSJohn Clements } 1234922f1bcSJohn Clements 1245de54343SHuang Rui static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1255de54343SHuang Rui { 1265de54343SHuang Rui unsigned long flags, address, data; 1275de54343SHuang Rui 1285de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 1295de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 1305de54343SHuang Rui 1315de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1325de54343SHuang Rui WREG32(address, reg * 4); 1335de54343SHuang Rui (void)RREG32(address); 1345de54343SHuang Rui WREG32(data, v); 1355de54343SHuang Rui (void)RREG32(data); 1365de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1375de54343SHuang Rui } 1385de54343SHuang Rui 139c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 140c6b6a421SHawking Zhang { 141c6b6a421SHawking Zhang unsigned long flags, address, data; 142c6b6a421SHawking Zhang u32 r; 143c6b6a421SHawking Zhang 144c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 145c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 146c6b6a421SHawking Zhang 147c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 148c6b6a421SHawking Zhang WREG32(address, (reg)); 149c6b6a421SHawking Zhang r = RREG32(data); 150c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 151c6b6a421SHawking Zhang return r; 152c6b6a421SHawking Zhang } 153c6b6a421SHawking Zhang 154c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 155c6b6a421SHawking Zhang { 156c6b6a421SHawking Zhang unsigned long flags, address, data; 157c6b6a421SHawking Zhang 158c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 159c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 160c6b6a421SHawking Zhang 161c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 162c6b6a421SHawking Zhang WREG32(address, (reg)); 163c6b6a421SHawking Zhang WREG32(data, (v)); 164c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 165c6b6a421SHawking Zhang } 166c6b6a421SHawking Zhang 167c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 168c6b6a421SHawking Zhang { 169bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 170c6b6a421SHawking Zhang } 171c6b6a421SHawking Zhang 172c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 173c6b6a421SHawking Zhang { 174462a70d8STao Zhou return adev->clock.spll.reference_freq; 175c6b6a421SHawking Zhang } 176c6b6a421SHawking Zhang 177c6b6a421SHawking Zhang 178c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 179c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 180c6b6a421SHawking Zhang { 181c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 182c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 183c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 184c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 185c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 186c6b6a421SHawking Zhang 187c6b6a421SHawking Zhang WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 188c6b6a421SHawking Zhang } 189c6b6a421SHawking Zhang 190c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 191c6b6a421SHawking Zhang { 192c6b6a421SHawking Zhang /* todo */ 193c6b6a421SHawking Zhang } 194c6b6a421SHawking Zhang 195c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 196c6b6a421SHawking Zhang { 197c6b6a421SHawking Zhang /* todo */ 198c6b6a421SHawking Zhang return false; 199c6b6a421SHawking Zhang } 200c6b6a421SHawking Zhang 201c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 202c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 203c6b6a421SHawking Zhang { 20429bc37b4SAlex Deucher u32 *dw_ptr; 20529bc37b4SAlex Deucher u32 i, length_dw; 20629bc37b4SAlex Deucher 20729bc37b4SAlex Deucher if (bios == NULL) 208c6b6a421SHawking Zhang return false; 20929bc37b4SAlex Deucher if (length_bytes == 0) 21029bc37b4SAlex Deucher return false; 21129bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 21229bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 21329bc37b4SAlex Deucher return false; 21429bc37b4SAlex Deucher 21529bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 21629bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 21729bc37b4SAlex Deucher 21829bc37b4SAlex Deucher /* set rom index to 0 */ 21929bc37b4SAlex Deucher WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 22029bc37b4SAlex Deucher /* read out the rom data */ 22129bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 22229bc37b4SAlex Deucher dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 22329bc37b4SAlex Deucher 22429bc37b4SAlex Deucher return true; 225c6b6a421SHawking Zhang } 226c6b6a421SHawking Zhang 227c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 228c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 229c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 230c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 231c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 232c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 233c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 234c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 235c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 236c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 237c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 238c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 239c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 240c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 241c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 242c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 243664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 244c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 245c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 246c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 247c6b6a421SHawking Zhang }; 248c6b6a421SHawking Zhang 249c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 250c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 251c6b6a421SHawking Zhang { 252c6b6a421SHawking Zhang uint32_t val; 253c6b6a421SHawking Zhang 254c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 255c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 256c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 257c6b6a421SHawking Zhang 258c6b6a421SHawking Zhang val = RREG32(reg_offset); 259c6b6a421SHawking Zhang 260c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 261c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 262c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 263c6b6a421SHawking Zhang return val; 264c6b6a421SHawking Zhang } 265c6b6a421SHawking Zhang 266c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 267c6b6a421SHawking Zhang bool indexed, u32 se_num, 268c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 269c6b6a421SHawking Zhang { 270c6b6a421SHawking Zhang if (indexed) { 271c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 272c6b6a421SHawking Zhang } else { 273c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 274c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 275c6b6a421SHawking Zhang return RREG32(reg_offset); 276c6b6a421SHawking Zhang } 277c6b6a421SHawking Zhang } 278c6b6a421SHawking Zhang 279c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 280c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 281c6b6a421SHawking Zhang { 282c6b6a421SHawking Zhang uint32_t i; 283c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 284c6b6a421SHawking Zhang 285c6b6a421SHawking Zhang *value = 0; 286c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 287c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 288fced3c3aSHuang Rui if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 289fced3c3aSHuang Rui reg_offset != 290c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 291c6b6a421SHawking Zhang continue; 292c6b6a421SHawking Zhang 293c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 294c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 295c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 296c6b6a421SHawking Zhang return 0; 297c6b6a421SHawking Zhang } 298c6b6a421SHawking Zhang return -EINVAL; 299c6b6a421SHawking Zhang } 300c6b6a421SHawking Zhang 3013e2bb60aSKevin Wang static int nv_asic_mode1_reset(struct amdgpu_device *adev) 3023e2bb60aSKevin Wang { 3033e2bb60aSKevin Wang u32 i; 3043e2bb60aSKevin Wang int ret = 0; 3053e2bb60aSKevin Wang 3063e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, true); 3073e2bb60aSKevin Wang 3083e2bb60aSKevin Wang /* disable BM */ 3093e2bb60aSKevin Wang pci_clear_master(adev->pdev); 3103e2bb60aSKevin Wang 311c1dd4aa6SAndrey Grodzovsky amdgpu_device_cache_pci_state(adev->pdev); 3123e2bb60aSKevin Wang 313311531f0SWenhui Sheng if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 314311531f0SWenhui Sheng dev_info(adev->dev, "GPU smu mode1 reset\n"); 315311531f0SWenhui Sheng ret = amdgpu_dpm_mode1_reset(adev); 316311531f0SWenhui Sheng } else { 317311531f0SWenhui Sheng dev_info(adev->dev, "GPU psp mode1 reset\n"); 3183e2bb60aSKevin Wang ret = psp_gpu_reset(adev); 319311531f0SWenhui Sheng } 320311531f0SWenhui Sheng 3213e2bb60aSKevin Wang if (ret) 3223e2bb60aSKevin Wang dev_err(adev->dev, "GPU mode1 reset failed\n"); 323c1dd4aa6SAndrey Grodzovsky amdgpu_device_load_pci_state(adev->pdev); 3243e2bb60aSKevin Wang 3253e2bb60aSKevin Wang /* wait for asic to come out of reset */ 3263e2bb60aSKevin Wang for (i = 0; i < adev->usec_timeout; i++) { 327bebc0762SHawking Zhang u32 memsize = adev->nbio.funcs->get_memsize(adev); 3283e2bb60aSKevin Wang 3293e2bb60aSKevin Wang if (memsize != 0xffffffff) 3303e2bb60aSKevin Wang break; 3313e2bb60aSKevin Wang udelay(1); 3323e2bb60aSKevin Wang } 3333e2bb60aSKevin Wang 3343e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, false); 3353e2bb60aSKevin Wang 3363e2bb60aSKevin Wang return ret; 3373e2bb60aSKevin Wang } 3382ddc6c3eSAlex Deucher 339ac742616SAlex Deucher static bool nv_asic_supports_baco(struct amdgpu_device *adev) 340ac742616SAlex Deucher { 341ac742616SAlex Deucher struct smu_context *smu = &adev->smu; 342ac742616SAlex Deucher 343ac742616SAlex Deucher if (smu_baco_is_support(smu)) 344ac742616SAlex Deucher return true; 345ac742616SAlex Deucher else 346ac742616SAlex Deucher return false; 347ac742616SAlex Deucher } 348ac742616SAlex Deucher 3492ddc6c3eSAlex Deucher static enum amd_reset_method 3502ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 3512ddc6c3eSAlex Deucher { 3522ddc6c3eSAlex Deucher struct smu_context *smu = &adev->smu; 3532ddc6c3eSAlex Deucher 354273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 355273da6ffSWenhui Sheng amdgpu_reset_method == AMD_RESET_METHOD_BACO) 356273da6ffSWenhui Sheng return amdgpu_reset_method; 357273da6ffSWenhui Sheng 358273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 359273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 360273da6ffSWenhui Sheng amdgpu_reset_method); 361273da6ffSWenhui Sheng 362ca6fd7a6SLikun Gao switch (adev->asic_type) { 363ca6fd7a6SLikun Gao case CHIP_SIENNA_CICHLID: 36422dd44f4SJiansong Chen case CHIP_NAVY_FLOUNDER: 365ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 366ca6fd7a6SLikun Gao default: 367311531f0SWenhui Sheng if (smu_baco_is_support(smu)) 3682ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 3692ddc6c3eSAlex Deucher else 3702ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 3712ddc6c3eSAlex Deucher } 372ca6fd7a6SLikun Gao } 3732ddc6c3eSAlex Deucher 374c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 375c6b6a421SHawking Zhang { 376767acabdSKevin Wang int ret = 0; 377767acabdSKevin Wang struct smu_context *smu = &adev->smu; 378c6b6a421SHawking Zhang 379e3526257SMonk Liu if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 38011043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 381311531f0SWenhui Sheng 38211520f27SAlex Deucher ret = smu_baco_enter(smu); 38311520f27SAlex Deucher if (ret) 38411520f27SAlex Deucher return ret; 38511520f27SAlex Deucher ret = smu_baco_exit(smu); 38611520f27SAlex Deucher if (ret) 38711520f27SAlex Deucher return ret; 38811043b7aSAlex Deucher } else { 38911043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 3903e2bb60aSKevin Wang ret = nv_asic_mode1_reset(adev); 39111043b7aSAlex Deucher } 392767acabdSKevin Wang 393767acabdSKevin Wang return ret; 394c6b6a421SHawking Zhang } 395c6b6a421SHawking Zhang 396c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 397c6b6a421SHawking Zhang { 398c6b6a421SHawking Zhang /* todo */ 399c6b6a421SHawking Zhang return 0; 400c6b6a421SHawking Zhang } 401c6b6a421SHawking Zhang 402c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 403c6b6a421SHawking Zhang { 404c6b6a421SHawking Zhang /* todo */ 405c6b6a421SHawking Zhang return 0; 406c6b6a421SHawking Zhang } 407c6b6a421SHawking Zhang 408c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 409c6b6a421SHawking Zhang { 410c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 411c6b6a421SHawking Zhang return; 412c6b6a421SHawking Zhang 413c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 414c6b6a421SHawking Zhang return; 415c6b6a421SHawking Zhang 416c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 417c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 418c6b6a421SHawking Zhang return; 419c6b6a421SHawking Zhang 420c6b6a421SHawking Zhang /* todo */ 421c6b6a421SHawking Zhang } 422c6b6a421SHawking Zhang 423c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 424c6b6a421SHawking Zhang { 425c6b6a421SHawking Zhang 426c6b6a421SHawking Zhang if (amdgpu_aspm == 0) 427c6b6a421SHawking Zhang return; 428c6b6a421SHawking Zhang 429c6b6a421SHawking Zhang /* todo */ 430c6b6a421SHawking Zhang } 431c6b6a421SHawking Zhang 432c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 433c6b6a421SHawking Zhang bool enable) 434c6b6a421SHawking Zhang { 435bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 436bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 437c6b6a421SHawking Zhang } 438c6b6a421SHawking Zhang 439c6b6a421SHawking Zhang static const struct amdgpu_ip_block_version nv_common_ip_block = 440c6b6a421SHawking Zhang { 441c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 442c6b6a421SHawking Zhang .major = 1, 443c6b6a421SHawking Zhang .minor = 0, 444c6b6a421SHawking Zhang .rev = 0, 445c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 446c6b6a421SHawking Zhang }; 447c6b6a421SHawking Zhang 448b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 449c6b6a421SHawking Zhang { 450b5c73856SXiaojie Yuan int r; 451b5c73856SXiaojie Yuan 452*8bb3aa1aSAlex Deucher /* IP discovery table is not available yet */ 453*8bb3aa1aSAlex Deucher if (adev->asic_type == CHIP_VANGOGH) 454*8bb3aa1aSAlex Deucher goto legacy_init; 455*8bb3aa1aSAlex Deucher 456b5c73856SXiaojie Yuan if (amdgpu_discovery) { 457b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 458b5c73856SXiaojie Yuan if (r) { 459b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 460b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 461b5c73856SXiaojie Yuan goto legacy_init; 462b5c73856SXiaojie Yuan } 463b5c73856SXiaojie Yuan 464b5c73856SXiaojie Yuan return 0; 465b5c73856SXiaojie Yuan } 466b5c73856SXiaojie Yuan 467b5c73856SXiaojie Yuan legacy_init: 468c6b6a421SHawking Zhang switch (adev->asic_type) { 469c6b6a421SHawking Zhang case CHIP_NAVI10: 470c6b6a421SHawking Zhang navi10_reg_base_init(adev); 471c6b6a421SHawking Zhang break; 472a0f6d926SXiaojie Yuan case CHIP_NAVI14: 473a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 474a0f6d926SXiaojie Yuan break; 47503d0a073SXiaojie Yuan case CHIP_NAVI12: 47603d0a073SXiaojie Yuan navi12_reg_base_init(adev); 47703d0a073SXiaojie Yuan break; 478dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 479c8c959f6SJiansong Chen case CHIP_NAVY_FLOUNDER: 480dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 481dccdbf3fSLikun Gao break; 482026570e6SHuang Rui case CHIP_VANGOGH: 483026570e6SHuang Rui vangogh_reg_base_init(adev); 484026570e6SHuang Rui break; 485c6b6a421SHawking Zhang default: 486c6b6a421SHawking Zhang return -EINVAL; 487c6b6a421SHawking Zhang } 488c6b6a421SHawking Zhang 489b5c73856SXiaojie Yuan return 0; 490b5c73856SXiaojie Yuan } 491b5c73856SXiaojie Yuan 492c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 493c1299461SWenhui Sheng { 494c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 495c1299461SWenhui Sheng } 496c1299461SWenhui Sheng 497b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 498b5c73856SXiaojie Yuan { 499b5c73856SXiaojie Yuan int r; 500b5c73856SXiaojie Yuan 501a7e91bd7SHuang Rui if (adev->flags & AMD_IS_APU) { 502a7e91bd7SHuang Rui adev->nbio.funcs = &nbio_v7_2_funcs; 503a7e91bd7SHuang Rui adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 504a7e91bd7SHuang Rui } else { 505122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 506122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 507a7e91bd7SHuang Rui } 508122078deSMonk Liu 509c652923aSJohn Clements if (adev->asic_type == CHIP_SIENNA_CICHLID) 510c652923aSJohn Clements adev->gmc.xgmi.supported = true; 511c652923aSJohn Clements 512b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 513b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 514b5c73856SXiaojie Yuan if (r) 515b5c73856SXiaojie Yuan return r; 516b5c73856SXiaojie Yuan 517c6b6a421SHawking Zhang switch (adev->asic_type) { 518c6b6a421SHawking Zhang case CHIP_NAVI10: 519d1daf850SAlex Deucher case CHIP_NAVI14: 520c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 521c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 522c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 523c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 524c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5259530273eSEvan Quan !amdgpu_sriov_vf(adev)) 526c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 527c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 528c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 529f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 530b4f199c7SHarry Wentland else if (amdgpu_device_has_dc_support(adev)) 531b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 532f8a7976bSAlex Deucher #endif 533c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 534c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 535c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 5369530273eSEvan Quan !amdgpu_sriov_vf(adev)) 537c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 538c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 5395be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 540c6b6a421SHawking Zhang if (adev->enable_mes) 541c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 542c6b6a421SHawking Zhang break; 54344e9e7c9SXiaojie Yuan case CHIP_NAVI12: 54444e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 54544e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 54644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 5476b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 54879bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 5497f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 55079902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 55179902029SXiaojie Yuan amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 55220c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 553078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 554078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 55520c14ee1SPetr Cvek #endif 55644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 55744e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 5587f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 5599530273eSEvan Quan !amdgpu_sriov_vf(adev)) 5607f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5611fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 562fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 5635be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 56444e9e7c9SXiaojie Yuan break; 5652e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 5662e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 5670b3df16bSLikun Gao amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 568757b3af8SLikun Gao amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 56956304e72SLikun Gao if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 5705aa02350SLikun Gao amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 571b07e5c60SLikun Gao if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 57238d5bbefSshaoyunl is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 573b07e5c60SLikun Gao amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5749a986760SLikun Gao if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 5759a986760SLikun Gao amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 576464ab91aSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 577464ab91aSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 578464ab91aSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 579464ab91aSBhawanpreet Lakha #endif 580933c8a93SLikun Gao amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 581157e72e8SLikun Gao amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 582b8f10585SLeo Liu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 583c45fbe1bSJack Zhang if (!amdgpu_sriov_vf(adev)) 5844d72dd12SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 585c45fbe1bSJack Zhang 586a346ef86SJack Xiao if (adev->enable_mes) 587a346ef86SJack Xiao amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 5882e1ba10eSLikun Gao break; 5898515e0a4SJiansong Chen case CHIP_NAVY_FLOUNDER: 5908515e0a4SJiansong Chen amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 591fc8f07daSJiansong Chen amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 592026c396bSJiansong Chen amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 5937420eab2SJiansong Chen if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 5947420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 5957420eab2SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5967420eab2SJiansong Chen is_support_sw_smu(adev)) 5977420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5985404f073SJiansong Chen if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 5995404f073SJiansong Chen amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 600a6c5308fSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 601a6c5308fSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 602a6c5308fSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 603a6c5308fSBhawanpreet Lakha #endif 604885eb3faSJiansong Chen amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 605df2d15dfSJiansong Chen amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 606290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 607290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 608f4497d10SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 609f4497d10SJiansong Chen is_support_sw_smu(adev)) 610f4497d10SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 6118515e0a4SJiansong Chen break; 61288edbad6SHuang Rui case CHIP_VANGOGH: 61388edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 61488edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 61588edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 616ed3b7353SHuang Rui if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 617ed3b7353SHuang Rui amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 618c821e0fbSHuang Rui amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 61988edbad6SHuang Rui if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 62088edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 62188edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 62288edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 623b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 624b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 62588edbad6SHuang Rui break; 626c6b6a421SHawking Zhang default: 627c6b6a421SHawking Zhang return -EINVAL; 628c6b6a421SHawking Zhang } 629c6b6a421SHawking Zhang 630c6b6a421SHawking Zhang return 0; 631c6b6a421SHawking Zhang } 632c6b6a421SHawking Zhang 633c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 634c6b6a421SHawking Zhang { 635bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 636c6b6a421SHawking Zhang } 637c6b6a421SHawking Zhang 638c6b6a421SHawking Zhang static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 639c6b6a421SHawking Zhang { 640bebc0762SHawking Zhang adev->nbio.funcs->hdp_flush(adev, ring); 641c6b6a421SHawking Zhang } 642c6b6a421SHawking Zhang 643c6b6a421SHawking Zhang static void nv_invalidate_hdp(struct amdgpu_device *adev, 644c6b6a421SHawking Zhang struct amdgpu_ring *ring) 645c6b6a421SHawking Zhang { 646c6b6a421SHawking Zhang if (!ring || !ring->funcs->emit_wreg) { 64778f0aef1SStanley.Yang WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 648c6b6a421SHawking Zhang } else { 649c6b6a421SHawking Zhang amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 650c6b6a421SHawking Zhang HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 651c6b6a421SHawking Zhang } 652c6b6a421SHawking Zhang } 653c6b6a421SHawking Zhang 654c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 655c6b6a421SHawking Zhang { 656c6b6a421SHawking Zhang return true; 657c6b6a421SHawking Zhang } 658c6b6a421SHawking Zhang 659c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 660c6b6a421SHawking Zhang { 661c6b6a421SHawking Zhang u32 sol_reg; 662c6b6a421SHawking Zhang 663c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 664c6b6a421SHawking Zhang return false; 665c6b6a421SHawking Zhang 666c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 667c6b6a421SHawking Zhang * are already been loaded. 668c6b6a421SHawking Zhang */ 669c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 670c6b6a421SHawking Zhang if (sol_reg) 671c6b6a421SHawking Zhang return true; 6723967ae6dSAlex Deucher 673c6b6a421SHawking Zhang return false; 674c6b6a421SHawking Zhang } 675c6b6a421SHawking Zhang 6762af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 6772af81531SKevin Wang { 6782af81531SKevin Wang 6792af81531SKevin Wang /* TODO 6802af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 6812af81531SKevin Wang * */ 6822af81531SKevin Wang 6832af81531SKevin Wang return 0; 6842af81531SKevin Wang } 6852af81531SKevin Wang 686c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 687c6b6a421SHawking Zhang { 688c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 689c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 690c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 691c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 692c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 693c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 694c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 695c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 696c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 697c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 698c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 699c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 700c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 70120519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 702c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 703c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 704157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 705157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 706c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 707c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 708c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 709c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 710c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 711c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 712c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 713c6b6a421SHawking Zhang 714c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 715c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 716c6b6a421SHawking Zhang } 717c6b6a421SHawking Zhang 718a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 719a7173731SAlex Deucher { 720a7173731SAlex Deucher } 721a7173731SAlex Deucher 722c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 723c6b6a421SHawking Zhang { 724c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 725c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 726c6b6a421SHawking Zhang .read_register = &nv_read_register, 727c6b6a421SHawking Zhang .reset = &nv_asic_reset, 7282ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 729c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 730c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 731c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 732c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 733c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 734c6b6a421SHawking Zhang .flush_hdp = &nv_flush_hdp, 735c6b6a421SHawking Zhang .invalidate_hdp = &nv_invalidate_hdp, 736c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 737c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 738c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 7392af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 740ac742616SAlex Deucher .supports_baco = &nv_asic_supports_baco, 741a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 742c6b6a421SHawking Zhang }; 743c6b6a421SHawking Zhang 744c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 745c6b6a421SHawking Zhang { 746923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 747c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 748c6b6a421SHawking Zhang 749923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 750923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 751c6b6a421SHawking Zhang adev->smc_rreg = NULL; 752c6b6a421SHawking Zhang adev->smc_wreg = NULL; 753c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 754c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 7554922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 7564922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 7575de54343SHuang Rui adev->pciep_rreg = &nv_pcie_port_rreg; 7585de54343SHuang Rui adev->pciep_wreg = &nv_pcie_port_wreg; 759c6b6a421SHawking Zhang 760c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 761c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 762c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 763c6b6a421SHawking Zhang 764c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 765c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 766c6b6a421SHawking Zhang 767c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 768c6b6a421SHawking Zhang 769c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 770c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 771c6b6a421SHawking Zhang switch (adev->asic_type) { 772c6b6a421SHawking Zhang case CHIP_NAVI10: 773c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 774c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 775c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 776c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 777c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 778c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 779c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 780c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 781c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 782c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 783c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 784c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 785099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 786c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 787c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 788157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 789c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 790099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 791a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 792c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 793c6b6a421SHawking Zhang break; 7945e71e011SXiaojie Yuan case CHIP_NAVI14: 795d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 796d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 797d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 798d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 799d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 800d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 801d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 802d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 803d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 804d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 805d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 806d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 807099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 808d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 809d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 8100377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 811099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 8120377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 81335ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 8145e71e011SXiaojie Yuan break; 81574b5e509SXiaojie Yuan case CHIP_NAVI12: 816dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 817dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 818dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 819dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 8205211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 821fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 8225211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 823358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 824358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 8258b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 8268b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 827ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 828ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 82965872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 830099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 831099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 832c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 8335ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 834099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 8351b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 836df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 837df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 838df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 839df5e984cSTiecheng Zhou */ 840df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 841df5e984cSTiecheng Zhou adev->rev_id = 0; 84274b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 84374b5e509SXiaojie Yuan break; 844117910edSLikun Gao case CHIP_SIENNA_CICHLID: 84500194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 84600194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 84700194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 84898f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 84900194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 850ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 851ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 8523a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 853bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 854bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 855b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 856d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 857b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 8581b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 8591b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 860c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 861c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 862c45fbe1bSJack Zhang adev->cg_flags = 0; 863c45fbe1bSJack Zhang adev->pg_flags = 0; 864c45fbe1bSJack Zhang } 865117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 866117910edSLikun Gao break; 867543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 86840582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 86940582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 87040582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 87140582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 87292c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 87392c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 8744759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 8754759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 87685e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 87785e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 878c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 87900740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 88047fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 88147fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 88247fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 883543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 884543aa259SJiansong Chen break; 885543aa259SJiansong Chen 886026570e6SHuang Rui case CHIP_VANGOGH: 887026570e6SHuang Rui adev->cg_flags = 0; 888026570e6SHuang Rui adev->pg_flags = 0; 889026570e6SHuang Rui adev->external_rev_id = adev->rev_id + 0x01; 890026570e6SHuang Rui break; 891c6b6a421SHawking Zhang default: 892c6b6a421SHawking Zhang /* FIXME: not supported yet */ 893c6b6a421SHawking Zhang return -EINVAL; 894c6b6a421SHawking Zhang } 895c6b6a421SHawking Zhang 896b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 897b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 898b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 899b05b6903SJiange Zhao } 900b05b6903SJiange Zhao 901c6b6a421SHawking Zhang return 0; 902c6b6a421SHawking Zhang } 903c6b6a421SHawking Zhang 904c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 905c6b6a421SHawking Zhang { 906b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 907b05b6903SJiange Zhao 908b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 909b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 910b05b6903SJiange Zhao 911c6b6a421SHawking Zhang return 0; 912c6b6a421SHawking Zhang } 913c6b6a421SHawking Zhang 914c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 915c6b6a421SHawking Zhang { 916b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 917b05b6903SJiange Zhao 918b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 919b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 920b05b6903SJiange Zhao 921c6b6a421SHawking Zhang return 0; 922c6b6a421SHawking Zhang } 923c6b6a421SHawking Zhang 924c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 925c6b6a421SHawking Zhang { 926c6b6a421SHawking Zhang return 0; 927c6b6a421SHawking Zhang } 928c6b6a421SHawking Zhang 929c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 930c6b6a421SHawking Zhang { 931c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 932c6b6a421SHawking Zhang 933c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 934c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 935c6b6a421SHawking Zhang /* enable aspm */ 936c6b6a421SHawking Zhang nv_program_aspm(adev); 937c6b6a421SHawking Zhang /* setup nbio registers */ 938bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 939923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 940923c087aSYong Zhao * for the purpose of expose those registers 941923c087aSYong Zhao * to process space 942923c087aSYong Zhao */ 943923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 944923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 945c6b6a421SHawking Zhang /* enable the doorbell aperture */ 946c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 947c6b6a421SHawking Zhang 948c6b6a421SHawking Zhang return 0; 949c6b6a421SHawking Zhang } 950c6b6a421SHawking Zhang 951c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 952c6b6a421SHawking Zhang { 953c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 954c6b6a421SHawking Zhang 955c6b6a421SHawking Zhang /* disable the doorbell aperture */ 956c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 957c6b6a421SHawking Zhang 958c6b6a421SHawking Zhang return 0; 959c6b6a421SHawking Zhang } 960c6b6a421SHawking Zhang 961c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 962c6b6a421SHawking Zhang { 963c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 964c6b6a421SHawking Zhang 965c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 966c6b6a421SHawking Zhang } 967c6b6a421SHawking Zhang 968c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 969c6b6a421SHawking Zhang { 970c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 971c6b6a421SHawking Zhang 972c6b6a421SHawking Zhang return nv_common_hw_init(adev); 973c6b6a421SHawking Zhang } 974c6b6a421SHawking Zhang 975c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 976c6b6a421SHawking Zhang { 977c6b6a421SHawking Zhang return true; 978c6b6a421SHawking Zhang } 979c6b6a421SHawking Zhang 980c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 981c6b6a421SHawking Zhang { 982c6b6a421SHawking Zhang return 0; 983c6b6a421SHawking Zhang } 984c6b6a421SHawking Zhang 985c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 986c6b6a421SHawking Zhang { 987c6b6a421SHawking Zhang return 0; 988c6b6a421SHawking Zhang } 989c6b6a421SHawking Zhang 990c6b6a421SHawking Zhang static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 991c6b6a421SHawking Zhang bool enable) 992c6b6a421SHawking Zhang { 993c6b6a421SHawking Zhang uint32_t hdp_clk_cntl, hdp_clk_cntl1; 994c6b6a421SHawking Zhang uint32_t hdp_mem_pwr_cntl; 995c6b6a421SHawking Zhang 996c6b6a421SHawking Zhang if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 997c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_DS | 998c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_SD))) 999c6b6a421SHawking Zhang return; 1000c6b6a421SHawking Zhang 1001c6b6a421SHawking Zhang hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1002c6b6a421SHawking Zhang hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1003c6b6a421SHawking Zhang 1004c6b6a421SHawking Zhang /* Before doing clock/power mode switch, 1005c6b6a421SHawking Zhang * forced on IPH & RC clock */ 1006c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 1007c6b6a421SHawking Zhang IPH_MEM_CLK_SOFT_OVERRIDE, 1); 1008c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 1009c6b6a421SHawking Zhang RC_MEM_CLK_SOFT_OVERRIDE, 1); 1010c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1011c6b6a421SHawking Zhang 1012c6b6a421SHawking Zhang /* HDP 5.0 doesn't support dynamic power mode switch, 1013c6b6a421SHawking Zhang * disable clock and power gating before any changing */ 1014c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1015c6b6a421SHawking Zhang IPH_MEM_POWER_CTRL_EN, 0); 1016c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1017c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, 0); 1018c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1019c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, 0); 1020c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1021c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, 0); 1022c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1023c6b6a421SHawking Zhang RC_MEM_POWER_CTRL_EN, 0); 1024c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1025c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, 0); 1026c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1027c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, 0); 1028c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1029c6b6a421SHawking Zhang RC_MEM_POWER_SD_EN, 0); 1030c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1031c6b6a421SHawking Zhang 1032c6b6a421SHawking Zhang /* only one clock gating mode (LS/DS/SD) can be enabled */ 1033c6b6a421SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1034c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1035c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1036c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, enable); 1037c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1038c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1039c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, enable); 1040c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 1041c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1042c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1043c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, enable); 1044c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1045c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1046c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 1047c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 1048c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1049c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1050c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, enable); 1051c6b6a421SHawking Zhang /* RC should not use shut down mode, fallback to ds */ 1052c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1053c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1054c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 1055c6b6a421SHawking Zhang } 1056c6b6a421SHawking Zhang 105791c6adf8SKenneth Feng /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 105891c6adf8SKenneth Feng * be set for SRAM LS/DS/SD */ 105991c6adf8SKenneth Feng if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 106091c6adf8SKenneth Feng AMD_CG_SUPPORT_HDP_SD)) { 106191c6adf8SKenneth Feng hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 106291c6adf8SKenneth Feng IPH_MEM_POWER_CTRL_EN, 1); 106391c6adf8SKenneth Feng hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 106491c6adf8SKenneth Feng RC_MEM_POWER_CTRL_EN, 1); 106591c6adf8SKenneth Feng } 106691c6adf8SKenneth Feng 1067c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1068c6b6a421SHawking Zhang 1069c6b6a421SHawking Zhang /* restore IPH & RC clock override after clock/power mode changing */ 1070c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 1071c6b6a421SHawking Zhang } 1072c6b6a421SHawking Zhang 1073c6b6a421SHawking Zhang static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 1074c6b6a421SHawking Zhang bool enable) 1075c6b6a421SHawking Zhang { 1076c6b6a421SHawking Zhang uint32_t hdp_clk_cntl; 1077c6b6a421SHawking Zhang 1078c6b6a421SHawking Zhang if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1079c6b6a421SHawking Zhang return; 1080c6b6a421SHawking Zhang 1081c6b6a421SHawking Zhang hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1082c6b6a421SHawking Zhang 1083c6b6a421SHawking Zhang if (enable) { 1084c6b6a421SHawking Zhang hdp_clk_cntl &= 1085c6b6a421SHawking Zhang ~(uint32_t) 1086c6b6a421SHawking Zhang (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1087c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1088c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1089c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1090c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1091c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 1092c6b6a421SHawking Zhang } else { 1093c6b6a421SHawking Zhang hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1094c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1095c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1096c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1097c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1098c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 1099c6b6a421SHawking Zhang } 1100c6b6a421SHawking Zhang 1101c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1102c6b6a421SHawking Zhang } 1103c6b6a421SHawking Zhang 1104c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1105c6b6a421SHawking Zhang enum amd_clockgating_state state) 1106c6b6a421SHawking Zhang { 1107c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1108c6b6a421SHawking Zhang 1109c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1110c6b6a421SHawking Zhang return 0; 1111c6b6a421SHawking Zhang 1112c6b6a421SHawking Zhang switch (adev->asic_type) { 1113c6b6a421SHawking Zhang case CHIP_NAVI10: 11145e71e011SXiaojie Yuan case CHIP_NAVI14: 11157e17e58bSXiaojie Yuan case CHIP_NAVI12: 1116117910edSLikun Gao case CHIP_SIENNA_CICHLID: 1117543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 1118bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1119a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1120bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1121a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1122c6b6a421SHawking Zhang nv_update_hdp_mem_power_gating(adev, 1123a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1124c6b6a421SHawking Zhang nv_update_hdp_clock_gating(adev, 1125a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1126c6b6a421SHawking Zhang break; 1127c6b6a421SHawking Zhang default: 1128c6b6a421SHawking Zhang break; 1129c6b6a421SHawking Zhang } 1130c6b6a421SHawking Zhang return 0; 1131c6b6a421SHawking Zhang } 1132c6b6a421SHawking Zhang 1133c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1134c6b6a421SHawking Zhang enum amd_powergating_state state) 1135c6b6a421SHawking Zhang { 1136c6b6a421SHawking Zhang /* TODO */ 1137c6b6a421SHawking Zhang return 0; 1138c6b6a421SHawking Zhang } 1139c6b6a421SHawking Zhang 1140c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1141c6b6a421SHawking Zhang { 1142c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1143c6b6a421SHawking Zhang uint32_t tmp; 1144c6b6a421SHawking Zhang 1145c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1146c6b6a421SHawking Zhang *flags = 0; 1147c6b6a421SHawking Zhang 1148bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1149c6b6a421SHawking Zhang 1150c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_MGCG */ 1151c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1152c6b6a421SHawking Zhang if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1153c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1154c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1155c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1156c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1157c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 1158c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1159c6b6a421SHawking Zhang 1160c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 1161c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1162c6b6a421SHawking Zhang if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 1163c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_LS; 1164c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1165c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_DS; 1166c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1167c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_SD; 1168c6b6a421SHawking Zhang 1169c6b6a421SHawking Zhang return; 1170c6b6a421SHawking Zhang } 1171c6b6a421SHawking Zhang 1172c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1173c6b6a421SHawking Zhang .name = "nv_common", 1174c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1175c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1176c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1177c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1178c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1179c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1180c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1181c6b6a421SHawking Zhang .resume = nv_common_resume, 1182c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1183c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1184c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1185c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1186c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1187c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1188c6b6a421SHawking Zhang }; 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